llvm-mirror/docs/AMDGPU/gfx10_addr_mimg.rst

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.. _amdgpu_synid10_addr_mimg:

vaddr
===========================

Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.

This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.

*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.

* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.


*Operands:* :ref:`v<amdgpu_synid_v>`
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347 2019-07-08 18:50:11 +02:00			`..`
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			`.. _amdgpu_synid10_addr_mimg:`

			`vaddr`
			`===========================`

			`Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.`

			This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.

			Size: 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.

			* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of MTBUF instructions and format modifier; - described limitations of f16 inline constants when used with integer operands; - updated description of gfx9+ flat global addressing modes; - v_accvgpr_write_b32 src0 corrections (gfx908); - minor bugfixing and improvements. 2020-08-21 13:22:25 +02:00			* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347 2019-07-08 18:50:11 +02:00

			Operands: :ref:`v<amdgpu_synid_v>`