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llvm-mirror/test/CodeGen/ARM/fpcmp-opt.ll

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Split -enable-finite-only-fp-math to two options: -enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. llvm-svn: 108465
2010-07-16 00:07:12 +02:00
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck -check-prefix=NAN %s
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: 1. The arguments are f32. 2. The arguments are loads and they have no uses other than the comparison. 3. The comparison code is EQ or NE. e.g. vldr.32 s0, [r1] vldr.32 s1, [r0] vcmpe.f32 s1, s0 vmrs apsr_nzcv, fpscr beq LBB0_2 => ldr r1, [r1] ldr r0, [r0] cmp r0, r1 beq LBB0_2 More complicated cases will be implemented in subsequent patches. llvm-svn: 107852
2010-07-08 04:08:50 +02:00
; rdar://7461510
define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
entry:
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
; FINITE: t1:
; FINITE-NOT: vldr
; FINITE: ldr
; FINITE: ldr
; FINITE: cmp r0, r1
; FINITE-NOT: vcmpe.f32
; FINITE-NOT: vmrs
; FINITE: beq
; NAN: t1:
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
2011-11-15 00:03:21 +01:00
; NAN: vldr s0,
; NAN: vldr s1,
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
; NAN: vcmpe.f32 s1, s0
; NAN: vmrs apsr_nzcv, fpscr
; NAN: beq
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: 1. The arguments are f32. 2. The arguments are loads and they have no uses other than the comparison. 3. The comparison code is EQ or NE. e.g. vldr.32 s0, [r1] vldr.32 s1, [r0] vcmpe.f32 s1, s0 vmrs apsr_nzcv, fpscr beq LBB0_2 => ldr r1, [r1] ldr r0, [r0] cmp r0, r1 beq LBB0_2 More complicated cases will be implemented in subsequent patches. llvm-svn: 107852
2010-07-08 04:08:50 +02:00
%0 = load float* %a
%1 = load float* %b
%2 = fcmp une float %0, %1
br i1 %2, label %bb1, label %bb2
bb1:
%3 = call i32 @bar()
ret i32 %3
bb2:
%4 = call i32 @foo()
ret i32 %4
}
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
entry:
; FINITE: t2:
; FINITE-NOT: vldr
LDRD/STRD instructions should print both Rt and Rt2 in the asm string. llvm-svn: 128736
2011-04-01 22:26:57 +02:00
; FINITE: ldrd r0, r1, [r0]
Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions. If the basic block containing the BCCi64 (or BCCZi64) instruction ends with an unconditional branch, that branch needs to be deleted before appending the expansion of the BCCi64 to the end of the block. llvm-svn: 122521
2010-12-23 23:45:49 +01:00
; FINITE-NOT: b LBB
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
; FINITE: cmp r0, #0
; FINITE: cmpeq r1, #0
; FINITE-NOT: vcmpe.f32
; FINITE-NOT: vmrs
; FINITE: bne
%0 = load double* %a
%1 = fcmp oeq double %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb1:
%2 = call i32 @bar()
ret i32 %2
bb2:
%3 = call i32 @foo()
ret i32 %3
}
define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
entry:
; FINITE: t3:
; FINITE-NOT: vldr
; FINITE: ldr r0, [r0]
; FINITE: cmp r0, #0
; FINITE-NOT: vcmpe.f32
; FINITE-NOT: vmrs
; FINITE: bne
%0 = load float* %a
%1 = fcmp oeq float %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb1:
%2 = call i32 @bar()
ret i32 %2
bb2:
%3 = call i32 @foo()
ret i32 %3
}
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: 1. The arguments are f32. 2. The arguments are loads and they have no uses other than the comparison. 3. The comparison code is EQ or NE. e.g. vldr.32 s0, [r1] vldr.32 s1, [r0] vcmpe.f32 s1, s0 vmrs apsr_nzcv, fpscr beq LBB0_2 => ldr r1, [r1] ldr r0, [r0] cmp r0, r1 beq LBB0_2 More complicated cases will be implemented in subsequent patches. llvm-svn: 107852
2010-07-08 04:08:50 +02:00
declare i32 @bar()
declare i32 @foo()
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