Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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//===- AMDGPURegisterBankInfo.cpp -------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterBankInfo.h"
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#include "AMDGPUInstrInfo.h"
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AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
Summary:
MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction
and register defintions, which are huge so we only want to include
them where needed.
This will also make it easier if we want to split the R600 and GCN
definitions into separate tablegenerated files.
I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h
because it uses some enums from the header to initialize default values
for the SIMachineFunction class, so I ended up having to remove includes of
SIMachineFunctionInfo.h from headers too.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46272
llvm-svn: 332930
2018-05-22 04:03:23 +02:00
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#include "SIMachineFunctionInfo.h"
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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#include "SIRegisterInfo.h"
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AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
Summary:
MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction
and register defintions, which are huge so we only want to include
them where needed.
This will also make it easier if we want to split the R600 and GCN
definitions into separate tablegenerated files.
I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h
because it uses some enums from the header to initialize default values
for the SIMachineFunction class, so I ended up having to remove includes of
SIMachineFunctionInfo.h from headers too.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46272
llvm-svn: 332930
2018-05-22 04:03:23 +02:00
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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2017-11-17 02:07:10 +01:00
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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#include "llvm/IR/Constants.h"
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#define GET_TARGET_REGBANK_IMPL
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#include "AMDGPUGenRegisterBank.inc"
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// This file will be TableGen'ed at some point.
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#include "AMDGPUGenRegisterBankInfo.def"
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using namespace llvm;
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AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
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: AMDGPUGenRegisterBankInfo(),
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TRI(static_cast<const SIRegisterInfo*>(&TRI)) {
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// HACK: Until this is fully tablegen'd
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static bool AlreadyInit = false;
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if (AlreadyInit)
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return;
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AlreadyInit = true;
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const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID);
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2017-01-30 23:02:58 +01:00
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(void)RBSGPR;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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assert(&RBSGPR == &AMDGPU::SGPRRegBank);
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const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID);
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2017-01-30 23:02:58 +01:00
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(void)RBVGPR;
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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assert(&RBVGPR == &AMDGPU::VGPRRegBank);
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}
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2018-03-12 14:35:53 +01:00
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static bool isConstant(const MachineOperand &MO, int64_t &C) {
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const MachineFunction *MF = MO.getParent()->getParent()->getParent();
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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const MachineInstr *Def = MRI.getVRegDef(MO.getReg());
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if (!Def)
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return false;
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if (Def->getOpcode() == AMDGPU::G_CONSTANT) {
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C = Def->getOperand(1).getCImm()->getSExtValue();
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return true;
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}
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if (Def->getOpcode() == AMDGPU::COPY)
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return isConstant(Def->getOperand(1), C);
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return false;
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}
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2018-03-01 20:09:25 +01:00
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unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
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const RegisterBank &Src,
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unsigned Size) const {
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if (Dst.getID() == AMDGPU::SGPRRegBankID &&
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Src.getID() == AMDGPU::VGPRRegBankID)
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return std::numeric_limits<unsigned>::max();
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2018-03-01 20:27:10 +01:00
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// SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
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// the valu.
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if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&
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Src.getID() == AMDGPU::SGPRRegBankID)
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return std::numeric_limits<unsigned>::max();
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2018-03-01 20:09:25 +01:00
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return RegisterBankInfo::copyCost(Dst, Src, Size);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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}
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const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
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const TargetRegisterClass &RC) const {
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if (TRI->isSGPRClass(&RC))
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return getRegBank(AMDGPU::SGPRRegBankID);
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return getRegBank(AMDGPU::VGPRRegBankID);
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}
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RegisterBankInfo::InstructionMappings
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AMDGPURegisterBankInfo::getInstrAlternativeMappings(
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const MachineInstr &MI) const {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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InstructionMappings AltMappings;
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switch (MI.getOpcode()) {
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case TargetOpcode::G_LOAD: {
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2018-03-01 20:27:10 +01:00
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unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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// FIXME: Should we be hard coding the size for these mappings?
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2017-05-06 00:48:22 +02:00
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const InstructionMapping &SSMapping = getInstructionMapping(
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1, 1, getOperandsMapping(
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{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64)}),
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2); // Num Operands
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AltMappings.push_back(&SSMapping);
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const InstructionMapping &VVMapping = getInstructionMapping(
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2, 1, getOperandsMapping(
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{AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64)}),
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2); // Num Operands
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AltMappings.push_back(&VVMapping);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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// FIXME: Should this be the pointer-size (64-bits) or the size of the
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// register that will hold the bufffer resourc (128-bits).
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2017-05-06 00:48:22 +02:00
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const InstructionMapping &VSMapping = getInstructionMapping(
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3, 1, getOperandsMapping(
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{AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64)}),
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2); // Num Operands
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AltMappings.push_back(&VSMapping);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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return AltMappings;
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}
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2018-03-01 20:27:10 +01:00
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case TargetOpcode::G_ICMP: {
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unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
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const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
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nullptr, // Predicate operand.
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&SSMapping);
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const InstructionMapping &SVMapping = getInstructionMapping(2, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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nullptr, // Predicate operand.
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&SVMapping);
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const InstructionMapping &VSMapping = getInstructionMapping(3, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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nullptr, // Predicate operand.
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&VSMapping);
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const InstructionMapping &VVMapping = getInstructionMapping(4, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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nullptr, // Predicate operand.
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&VVMapping);
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return AltMappings;
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}
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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default:
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break;
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}
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return RegisterBankInfo::getInstrAlternativeMappings(MI);
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}
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void AMDGPURegisterBankInfo::applyMappingImpl(
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const OperandsMapper &OpdMapper) const {
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return applyDefaultMapping(OpdMapper);
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}
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static bool isInstrUniform(const MachineInstr &MI) {
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if (!MI.hasOneMemOperand())
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return false;
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const MachineMemOperand *MMO = *MI.memoperands_begin();
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2018-02-09 17:57:48 +01:00
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return AMDGPUInstrInfo::isUniformMMO(MMO);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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}
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2018-03-01 22:25:25 +01:00
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bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) {
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unsigned Reg = MI.getOperand(i).getReg();
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const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
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if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID)
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return false;
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}
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return true;
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}
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const RegisterBankInfo::InstructionMapping &
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AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
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OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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}
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return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
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MI.getNumOperands());
|
|
|
|
}
|
|
|
|
|
|
|
|
const RegisterBankInfo::InstructionMapping &
|
|
|
|
AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
|
|
|
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
|
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
|
|
|
|
unsigned OpdIdx = 0;
|
|
|
|
|
|
|
|
unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
|
|
|
|
OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0);
|
|
|
|
|
2018-03-01 22:25:30 +01:00
|
|
|
if (MI.getOperand(OpdIdx).isIntrinsicID())
|
|
|
|
OpdsMapping[OpdIdx++] = nullptr;
|
|
|
|
|
|
|
|
unsigned Reg1 = MI.getOperand(OpdIdx).getReg();
|
2018-03-01 22:25:25 +01:00
|
|
|
unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);
|
|
|
|
unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI);
|
|
|
|
OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
|
|
|
|
|
|
|
|
for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
|
|
|
|
unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
|
|
|
|
OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
|
|
|
|
MI.getNumOperands());
|
|
|
|
}
|
|
|
|
|
2017-05-06 00:48:22 +02:00
|
|
|
const RegisterBankInfo::InstructionMapping &
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {
|
|
|
|
|
|
|
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
|
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
|
|
|
|
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
|
|
|
|
unsigned PtrSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
|
|
|
|
|
|
|
|
const ValueMapping *ValMapping;
|
|
|
|
const ValueMapping *PtrMapping;
|
|
|
|
|
|
|
|
if (isInstrUniform(MI)) {
|
|
|
|
// We have a uniform instruction so we want to use an SMRD load
|
|
|
|
ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
|
|
|
|
PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize);
|
|
|
|
} else {
|
|
|
|
ValMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
|
|
|
|
// FIXME: What would happen if we used SGPRRegBankID here?
|
|
|
|
PtrMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize);
|
|
|
|
}
|
|
|
|
|
|
|
|
OpdsMapping[0] = ValMapping;
|
|
|
|
OpdsMapping[1] = PtrMapping;
|
2017-05-06 00:48:22 +02:00
|
|
|
const RegisterBankInfo::InstructionMapping &Mapping = getInstructionMapping(
|
|
|
|
1, 1, getOperandsMapping(OpdsMapping), MI.getNumOperands());
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
return Mapping;
|
|
|
|
|
|
|
|
// FIXME: Do we want to add a mapping for FLAT load, or should we just
|
|
|
|
// handle that during instruction selection?
|
|
|
|
}
|
|
|
|
|
2018-03-01 20:27:10 +01:00
|
|
|
unsigned
|
|
|
|
AMDGPURegisterBankInfo::getRegBankID(unsigned Reg,
|
|
|
|
const MachineRegisterInfo &MRI,
|
|
|
|
const TargetRegisterInfo &TRI,
|
|
|
|
unsigned Default) const {
|
|
|
|
|
|
|
|
const RegisterBank *Bank = getRegBank(Reg, MRI, TRI);
|
|
|
|
return Bank ? Bank->getID() : Default;
|
|
|
|
}
|
|
|
|
|
|
|
|
///
|
|
|
|
/// This function must return a legal mapping, because
|
|
|
|
/// AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called
|
|
|
|
/// in RegBankSelect::Mode::Fast. Any mapping that would cause a
|
|
|
|
/// VGPR to SGPR generated is illegal.
|
|
|
|
///
|
2017-05-06 00:48:22 +02:00
|
|
|
const RegisterBankInfo::InstructionMapping &
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
2017-05-06 00:48:22 +02:00
|
|
|
const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
|
|
|
|
if (Mapping.isValid())
|
|
|
|
return Mapping;
|
|
|
|
|
|
|
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
|
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
|
|
|
|
|
|
|
|
switch (MI.getOpcode()) {
|
2017-05-06 00:48:22 +02:00
|
|
|
default:
|
2018-03-01 22:20:44 +01:00
|
|
|
return getInvalidInstructionMapping();
|
2018-03-19 15:07:23 +01:00
|
|
|
case AMDGPU::G_ADD:
|
|
|
|
case AMDGPU::G_SUB:
|
|
|
|
case AMDGPU::G_MUL:
|
2018-03-02 02:22:01 +01:00
|
|
|
case AMDGPU::G_AND:
|
2018-03-01 22:25:25 +01:00
|
|
|
case AMDGPU::G_OR:
|
2018-03-02 02:22:06 +01:00
|
|
|
case AMDGPU::G_XOR:
|
2018-03-02 02:22:10 +01:00
|
|
|
case AMDGPU::G_SHL:
|
2018-03-01 22:25:25 +01:00
|
|
|
if (isSALUMapping(MI))
|
|
|
|
return getDefaultMappingSOP(MI);
|
2018-03-02 02:22:13 +01:00
|
|
|
// Fall-through
|
|
|
|
|
|
|
|
case AMDGPU::G_FADD:
|
2018-03-02 03:19:16 +01:00
|
|
|
case AMDGPU::G_FPTOSI:
|
2018-03-02 03:19:11 +01:00
|
|
|
case AMDGPU::G_FPTOUI:
|
2018-03-02 03:17:01 +01:00
|
|
|
case AMDGPU::G_FMUL:
|
2018-03-01 22:25:25 +01:00
|
|
|
return getDefaultMappingVOP(MI);
|
2018-03-01 20:16:52 +01:00
|
|
|
case AMDGPU::G_IMPLICIT_DEF: {
|
|
|
|
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
|
|
|
|
break;
|
|
|
|
}
|
2018-03-01 20:13:30 +01:00
|
|
|
case AMDGPU::G_FCONSTANT:
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
case AMDGPU::G_CONSTANT: {
|
|
|
|
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
|
2017-05-06 00:48:22 +02:00
|
|
|
break;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
}
|
2018-03-05 17:25:18 +01:00
|
|
|
case AMDGPU::G_EXTRACT: {
|
|
|
|
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
|
|
|
|
unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
|
|
|
|
unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
|
|
|
|
OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
|
|
|
|
OpdsMapping[2] = nullptr;
|
|
|
|
break;
|
|
|
|
}
|
2018-03-12 14:35:49 +01:00
|
|
|
case AMDGPU::G_MERGE_VALUES: {
|
|
|
|
unsigned Bank = isSALUMapping(MI) ?
|
|
|
|
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
|
|
|
|
unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
|
|
|
|
unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
|
|
|
|
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
|
|
|
|
// Op1 and Dst should use the same register bank.
|
|
|
|
for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i)
|
|
|
|
OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
|
|
|
|
break;
|
|
|
|
}
|
2018-03-01 21:59:44 +01:00
|
|
|
case AMDGPU::G_BITCAST: {
|
|
|
|
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
|
|
|
|
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
|
|
|
|
OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size);
|
|
|
|
break;
|
|
|
|
}
|
2018-03-02 17:55:33 +01:00
|
|
|
case AMDGPU::G_TRUNC: {
|
|
|
|
unsigned Dst = MI.getOperand(0).getReg();
|
|
|
|
unsigned Src = MI.getOperand(1).getReg();
|
|
|
|
unsigned Bank = getRegBankID(Src, MRI, *TRI);
|
|
|
|
unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
|
|
|
|
unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
|
|
|
|
OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize);
|
|
|
|
break;
|
|
|
|
}
|
2018-03-02 17:55:37 +01:00
|
|
|
case AMDGPU::G_ZEXT: {
|
|
|
|
unsigned Dst = MI.getOperand(0).getReg();
|
|
|
|
unsigned Src = MI.getOperand(1).getReg();
|
|
|
|
unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
|
|
|
|
unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
|
|
|
|
unsigned SrcBank = getRegBankID(Src, MRI, *TRI,
|
|
|
|
SrcSize == 1 ? AMDGPU::SGPRRegBankID :
|
|
|
|
AMDGPU::VGPRRegBankID);
|
|
|
|
unsigned DstBank = SrcBank;
|
|
|
|
if (SrcSize == 1) {
|
|
|
|
if (SrcBank == AMDGPU::SGPRRegBankID)
|
|
|
|
DstBank = AMDGPU::VGPRRegBankID;
|
|
|
|
else
|
|
|
|
DstBank = AMDGPU::SGPRRegBankID;
|
|
|
|
}
|
|
|
|
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize);
|
|
|
|
OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank, SrcSize);
|
|
|
|
break;
|
|
|
|
}
|
2018-03-02 17:53:15 +01:00
|
|
|
case AMDGPU::G_FCMP: {
|
|
|
|
unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
|
|
|
|
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 1);
|
|
|
|
OpdsMapping[1] = nullptr; // Predicate Operand.
|
|
|
|
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
|
|
|
|
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
|
|
|
|
break;
|
|
|
|
}
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
case AMDGPU::G_GEP: {
|
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
if (!MI.getOperand(i).isReg())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
unsigned Size = MRI.getType(MI.getOperand(i).getReg()).getSizeInBits();
|
|
|
|
OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
|
|
|
|
}
|
2017-05-06 00:48:22 +02:00
|
|
|
break;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
}
|
|
|
|
case AMDGPU::G_STORE: {
|
|
|
|
assert(MI.getOperand(0).isReg());
|
|
|
|
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
|
|
|
|
// FIXME: We need to specify a different reg bank once scalar stores
|
|
|
|
// are supported.
|
|
|
|
const ValueMapping *ValMapping =
|
|
|
|
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
|
|
|
|
// FIXME: Depending on the type of store, the pointer could be in
|
|
|
|
// the SGPR Reg bank.
|
|
|
|
// FIXME: Pointer size should be based on the address space.
|
|
|
|
const ValueMapping *PtrMapping =
|
|
|
|
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64);
|
|
|
|
|
|
|
|
OpdsMapping[0] = ValMapping;
|
|
|
|
OpdsMapping[1] = PtrMapping;
|
2017-05-06 00:48:22 +02:00
|
|
|
break;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
}
|
|
|
|
|
2018-03-01 20:27:10 +01:00
|
|
|
case AMDGPU::G_ICMP: {
|
|
|
|
unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
|
|
|
|
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
|
|
|
|
unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
|
|
|
|
unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&
|
|
|
|
Op3Bank == AMDGPU::SGPRRegBankID ?
|
|
|
|
AMDGPU::SCCRegBankID : AMDGPU::VGPRRegBankID;
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
|
|
|
|
OpdsMapping[1] = nullptr; // Predicate Operand.
|
|
|
|
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
|
|
|
|
OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
|
|
|
|
break;
|
|
|
|
}
|
2018-03-12 14:35:53 +01:00
|
|
|
|
|
|
|
|
|
|
|
case AMDGPU::G_EXTRACT_VECTOR_ELT: {
|
|
|
|
unsigned IdxOp = 2;
|
|
|
|
int64_t Imm;
|
|
|
|
// XXX - Do we really need to fully handle these? The constant case should
|
|
|
|
// be legalized away before RegBankSelect?
|
|
|
|
|
|
|
|
unsigned OutputBankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
|
|
|
|
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
|
|
|
|
|
|
|
|
unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(0).getReg()).getSizeInBits());
|
|
|
|
OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(1).getReg()).getSizeInBits());
|
|
|
|
|
|
|
|
// The index can be either if the source vector is VGPR.
|
|
|
|
OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, MRI.getType(MI.getOperand(2).getReg()).getSizeInBits());
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case AMDGPU::G_INSERT_VECTOR_ELT: {
|
|
|
|
// XXX - Do we really need to fully handle these? The constant case should
|
|
|
|
// be legalized away before RegBankSelect?
|
|
|
|
|
|
|
|
int64_t Imm;
|
|
|
|
|
|
|
|
unsigned IdxOp = MI.getOpcode() == AMDGPU::G_EXTRACT_VECTOR_ELT ? 2 : 3;
|
|
|
|
unsigned BankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
|
|
|
|
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// TODO: Can do SGPR indexing, which would obviate the need for the
|
|
|
|
// isConstant check.
|
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
|
|
|
|
OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
2018-03-01 22:25:30 +01:00
|
|
|
case AMDGPU::G_INTRINSIC: {
|
2018-06-25 18:17:48 +02:00
|
|
|
switch (MI.getOperand(1).getIntrinsicID()) {
|
2018-03-01 22:25:30 +01:00
|
|
|
default:
|
|
|
|
return getInvalidInstructionMapping();
|
2018-03-02 13:23:00 +01:00
|
|
|
case Intrinsic::maxnum:
|
2018-03-02 17:40:17 +01:00
|
|
|
case Intrinsic::minnum:
|
2018-03-01 22:25:30 +01:00
|
|
|
case Intrinsic::amdgcn_cvt_pkrtz:
|
|
|
|
return getDefaultMappingVOP(MI);
|
2018-06-25 18:17:48 +02:00
|
|
|
case Intrinsic::amdgcn_kernarg_segment_ptr: {
|
|
|
|
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
|
|
|
|
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
|
|
|
|
break;
|
|
|
|
}
|
2018-03-01 22:25:30 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2018-03-01 21:24:37 +01:00
|
|
|
case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
|
2018-03-01 21:40:55 +01:00
|
|
|
switch (MI.getOperand(0).getIntrinsicID()) {
|
|
|
|
default:
|
|
|
|
return getInvalidInstructionMapping();
|
|
|
|
case Intrinsic::amdgcn_exp_compr:
|
|
|
|
OpdsMapping[0] = nullptr; // IntrinsicID
|
|
|
|
// FIXME: These are immediate values which can't be read from registers.
|
|
|
|
OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
|
|
|
|
OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
|
|
|
|
// FIXME: Could we support packed types here?
|
|
|
|
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
|
|
|
|
OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
|
|
|
|
// FIXME: These are immediate values which can't be read from registers.
|
|
|
|
OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
|
|
|
|
OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
|
|
|
|
break;
|
|
|
|
case Intrinsic::amdgcn_exp:
|
2018-03-01 21:24:37 +01:00
|
|
|
OpdsMapping[0] = nullptr; // IntrinsicID
|
|
|
|
// FIXME: These are immediate values which can't be read from registers.
|
|
|
|
OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
|
|
|
|
OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
|
|
|
|
// FIXME: Could we support packed types here?
|
|
|
|
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
|
|
|
|
OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
|
|
|
|
OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
|
|
|
|
OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
|
|
|
|
// FIXME: These are immediate values which can't be read from registers.
|
|
|
|
OpdsMapping[7] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
|
|
|
|
OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
case AMDGPU::G_LOAD:
|
|
|
|
return getInstrMappingForLoad(MI);
|
|
|
|
}
|
|
|
|
|
2017-05-06 00:48:22 +02:00
|
|
|
return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
|
|
|
|
MI.getNumOperands());
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
}
|