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52 lines
2.2 KiB
LLVM
52 lines
2.2 KiB
LLVM
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; TODO: Add RUN and CHECK lines for SI once this test works there
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@local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
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@local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
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; CHECK: @local_memory_two_objects
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; Check that the LDS size emitted correctly
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; CHECK: .long 166120
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; CHECK-NEXT: .long 8
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; Make sure the lds writes are using different addresses.
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; CHECK: LDS_WRITE {{[*]*}} {{PV|T}}[[ADDRW:[0-9]*\.[XYZW]]]
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; CHECK-NOT: LDS_WRITE {{[*]*}} T[[ADDRW]]
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; GROUP_BARRIER must be the last instruction in a clause
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; CHECK: GROUP_BARRIER
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; CHECK-NEXT: ALU clause
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; Make sure the lds reads are using different addresses.
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; CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
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; CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
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define void @local_memory_two_objects(i32 addrspace(1)* %out) {
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entry:
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
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store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
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%mul = shl nsw i32 %x.i, 1
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%arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
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store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
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%sub = sub nsw i32 3, %x.i
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call void @llvm.AMDGPU.barrier.local()
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%arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
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%0 = load i32 addrspace(3)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i
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store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
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%1 = load i32 addrspace(3)* %arrayidx4, align 4
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%add = add nsw i32 %x.i, 4
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%arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add
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store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #0
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declare void @llvm.AMDGPU.barrier.local()
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attributes #0 = { readnone }
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