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llvm-mirror/lib/Target/X86/X86RegisterInfo.cpp

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Added methods to read/write values to stack in .h, fixed implementation in .cpp to return the iterator correctly. llvm-svn: 4827
2002-11-22 23:43:47 +01:00
//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
//
Added LLVM project notice to the top of every C++ source file. Header files will be on the way. llvm-svn: 9298
2003-10-20 21:43:21 +02:00
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
//
Added LLVM project notice to the top of every C++ source file. Header files will be on the way. llvm-svn: 9298
2003-10-20 21:43:21 +02:00
//===----------------------------------------------------------------------===//
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 00:55:53 +02:00
//
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
// This file contains the X86 implementation of the MRegisterInfo class. This
// file is responsible for the frame pointer elimination optimization on X86.
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 00:55:53 +02:00
//
//===----------------------------------------------------------------------===//
Add definitions for function headers from MRegisterInfo.h: Some functions are in X86RegisterInfo.cpp, others, because of the data they need, are in X86RegisterClasses.cpp, which also defines some register classes: byte, short, and int. llvm-svn: 4784
2002-11-20 19:59:43 +01:00
#include "X86.h"
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 00:55:53 +02:00
#include "X86RegisterInfo.h"
Added methods to read/write values to stack in .h, fixed implementation in .cpp to return the iterator correctly. llvm-svn: 4827
2002-11-22 23:43:47 +01:00
#include "X86InstrBuilder.h"
Add definitions for function headers from MRegisterInfo.h: Some functions are in X86RegisterInfo.cpp, others, because of the data they need, are in X86RegisterClasses.cpp, which also defines some register classes: byte, short, and int. llvm-svn: 4784
2002-11-20 19:59:43 +01:00
#include "llvm/Constants.h"
#include "llvm/Type.h"
Move "register flags" definition the type of registers to be fully fledged value types llvm-svn: 7377
2003-07-29 07:14:16 +02:00
#include "llvm/CodeGen/ValueTypes.h"
Add definitions for function headers from MRegisterInfo.h: Some functions are in X86RegisterInfo.cpp, others, because of the data they need, are in X86RegisterClasses.cpp, which also defines some register classes: byte, short, and int. llvm-svn: 4784
2002-11-20 19:59:43 +01:00
#include "llvm/CodeGen/MachineInstrBuilder.h"
Simplify interfaces used by regalloc to insert code llvm-svn: 5052
2002-12-15 21:06:35 +01:00
#include "llvm/CodeGen/MachineFunction.h"
Rename FunctionFrameInfo to MachineFrameInfo llvm-svn: 5201
2002-12-28 22:08:28 +01:00
#include "llvm/CodeGen/MachineFrameInfo.h"
Implement code to keep the stack pointer aligned to an 8 byte boundary. This improves the performance of the power benchmark by a few percent. This will be neccesary for SSE code, which requires 16 byte alignment of the stack. llvm-svn: 5320
2003-01-16 03:20:12 +01:00
#include "llvm/Target/TargetFrameInfo.h"
Use the common `NoFPElim' setting instead of our own. llvm-svn: 14298
2004-06-21 23:10:24 +02:00
#include "llvm/Target/TargetMachine.h"
Delete the allocate*TargetMachine function, which is now dead . The shared command line options are now in a header that makes sense. llvm-svn: 14756
2004-07-11 06:17:10 +02:00
#include "llvm/Target/TargetOptions.h"
Changes For Bug 352 Move include/Config and include/Support into include/llvm/Config, include/llvm/ADT and include/llvm/Support. From here on out, all LLVM public header files must be under include/llvm/. llvm-svn: 16137
2004-09-02 00:55:40 +02:00
#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/STLExtras.h"
Add #include <iostream> since Value.h does not #include it any more. llvm-svn: 14622
2004-07-04 14:19:56 +02:00
#include <iostream>
finegrainify namespacification, fix 80col prob llvm-svn: 11445
2004-02-14 07:00:36 +01:00
using namespace llvm;
Put all LLVM code into the llvm namespace, as per bug 109. llvm-svn: 9903
2003-11-11 23:41:34 +01:00
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
namespace {
cl::opt<bool>
Add an option to disable spill fusing in the X86 backend llvm-svn: 11531
2004-02-17 07:30:34 +01:00
NoFusing("disable-spill-fusing",
cl::desc("Disable fusing of spill code into instructions"));
Add a (hidden) option to print instructions that fail to fuse. It's looking like compares and test's would be the next huge win... llvm-svn: 11539
2004-02-17 09:03:47 +01:00
cl::opt<bool>
PrintFailedFusing("print-failed-fuse-candidates",
cl::desc("Print instructions that the allocator wants to"
" fuse, but the X86 backend currently can't"),
cl::Hidden);
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
}
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 00:55:53 +02:00
Switch over to TableGen generated register file description llvm-svn: 7511
2003-08-03 17:48:14 +02:00
X86RegisterInfo::X86RegisterInfo()
: X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
Reduce uses of getRegClass llvm-svn: 15973
2004-08-21 22:13:52 +02:00
static unsigned getIdx(unsigned SpillSize) {
switch (SpillSize) {
Fix warning llvm-svn: 5109
2002-12-20 05:13:28 +01:00
default: assert(0 && "Invalid data size!");
Reduce uses of getRegClass llvm-svn: 15973
2004-08-21 22:13:52 +02:00
case 8: return 0;
case 16: return 1;
case 32: return 2;
Spill/restore X86 floating point stack registers with 64-bits of precision instead of 80-bits of precision. This fixes PR467. This change speeds up fldry on X86 with LLC from 7.32s on apoc to 4.68s. llvm-svn: 18433
2004-12-02 19:17:31 +01:00
case 64: return 3; // FP in 64-bit spill mode.
case 80: return 4; // FP in 80-bit spill mode.
First round of support for doing scalar FP using the SSE2 ISA extension and XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
2005-07-06 20:59:04 +02:00
case 128: return 5; // XMM reg in 128 bit mode.
Cleaned up the code: factored out switch/case into a separate function, put constants in an array for quick lookup. Stole the idea from elsewhere in Jello. llvm-svn: 5017
2002-12-13 13:00:06 +01:00
}
}
Code insertion methods now return void instead of an int. llvm-svn: 15780
2004-08-16 00:15:11 +02:00
void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx) const {
New simpler spill interface llvm-svn: 5148
2002-12-25 06:07:09 +01:00
static const unsigned Opcode[] =
First round of support for doing scalar FP using the SSE2 ISA extension and XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
2005-07-06 20:59:04 +02:00
{ X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST64m, X86::FSTP80m,
X86::MOVAPDmr };
Reduce uses of getRegClass llvm-svn: 15973
2004-08-21 22:13:52 +02:00
unsigned Idx = getIdx(getSpillSize(SrcReg));
First round of support for doing scalar FP using the SSE2 ISA extension and XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
2005-07-06 20:59:04 +02:00
unsigned Opc = Opcode[Idx];
if (X86ScalarSSE && Opc == X86::FST64m) Opc = X86::MOVSDmr;
addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
Add definitions for function headers from MRegisterInfo.h: Some functions are in X86RegisterInfo.cpp, others, because of the data they need, are in X86RegisterClasses.cpp, which also defines some register classes: byte, short, and int. llvm-svn: 4784
2002-11-20 19:59:43 +01:00
}
Code insertion methods now return void instead of an int. llvm-svn: 15780
2004-08-16 00:15:11 +02:00
void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx)const{
New simpler spill interface llvm-svn: 5148
2002-12-25 06:07:09 +01:00
static const unsigned Opcode[] =
First round of support for doing scalar FP using the SSE2 ISA extension and XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
2005-07-06 20:59:04 +02:00
{ X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD64m, X86::FLD80m,
X86::MOVAPDrm };
Reduce uses of getRegClass llvm-svn: 15973
2004-08-21 22:13:52 +02:00
unsigned Idx = getIdx(getSpillSize(DestReg));
First round of support for doing scalar FP using the SSE2 ISA extension and XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
2005-07-06 20:59:04 +02:00
unsigned Opc = Opcode[Idx];
if (X86ScalarSSE && Opc == X86::FLD64m) Opc = X86::MOVSDrm;
addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
Add definitions for function headers from MRegisterInfo.h: Some functions are in X86RegisterInfo.cpp, others, because of the data they need, are in X86RegisterClasses.cpp, which also defines some register classes: byte, short, and int. llvm-svn: 4784
2002-11-20 19:59:43 +01:00
}
Code insertion methods now return void instead of an int. llvm-svn: 15780
2004-08-16 00:15:11 +02:00
void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
New simpler spill interface llvm-svn: 5148
2002-12-25 06:07:09 +01:00
static const unsigned Opcode[] =
First round of support for doing scalar FP using the SSE2 ISA extension and XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
2005-07-06 20:59:04 +02:00
{ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::FpMOV,
X86::MOVAPDrr };
unsigned Opc = Opcode[getIdx(RC->getSize()*8)];
if (X86ScalarSSE && Opc == X86::FpMOV) Opc = X86::MOVAPDrr;
BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due to PHI nodes. llvm-svn: 5001
2002-12-13 10:54:12 +01:00
}
Add memory operand folding for CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions. llvm-svn: 11545
2004-02-17 09:49:20 +01:00
static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
Instructiosn with 1 memory operand have 4 operands in our representation.. duh! llvm-svn: 11554
2004-02-17 16:58:13 +01:00
return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
Add memory operand folding for CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions. llvm-svn: 11545
2004-02-17 09:49:20 +01:00
}
Scrunchify code, by adding helpers. No functionality changes. llvm-svn: 11522
2004-02-17 06:35:13 +01:00
static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addReg(MI->getOperand(1).getReg());
}
Add memory operand folding support for SHLD and SHRD instructions. llvm-svn: 11905
2004-02-27 16:03:18 +01:00
static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
Reserve the correct amt of space. llvm-svn: 14913
2004-07-17 22:24:05 +02:00
return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
Add memory operand folding support for SHLD and SHRD instructions. llvm-svn: 11905
2004-02-27 16:03:18 +01:00
.addReg(MI->getOperand(1).getReg())
.addZImm(MI->getOperand(2).getImmedValue());
}
Scrunchify code, by adding helpers. No functionality changes. llvm-svn: 11522
2004-02-17 06:35:13 +01:00
static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
Add support for GlobalAddress's for alkis llvm-svn: 11560
2004-02-17 19:23:55 +01:00
if (MI->getOperand(1).isImmediate())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addZImm(MI->getOperand(1).getImmedValue());
else if (MI->getOperand(1).isGlobalAddress())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addGlobalAddress(MI->getOperand(1).getGlobal());
assert(0 && "Unknown operand for MakeMI!");
return 0;
Scrunchify code, by adding helpers. No functionality changes. llvm-svn: 11522
2004-02-17 06:35:13 +01:00
}
static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
When folding memory operands in machine instructions be careful to leave register operands with the same use/def flags as the original instruction. llvm-svn: 11709
2004-02-22 07:54:26 +01:00
const MachineOperand& op = MI->getOperand(0);
return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
Add support for folding memory operands into AND and IMUL's llvm-svn: 11523
2004-02-17 06:46:06 +01:00
FrameIndex);
Scrunchify code, by adding helpers. No functionality changes. llvm-svn: 11522
2004-02-17 06:35:13 +01:00
}
Add support for folding memory operands into AND and IMUL's llvm-svn: 11523
2004-02-17 06:46:06 +01:00
static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
When folding memory operands in machine instructions be careful to leave register operands with the same use/def flags as the original instruction. llvm-svn: 11709
2004-02-22 07:54:26 +01:00
const MachineOperand& op = MI->getOperand(0);
Reserve the correct amt of space. llvm-svn: 14913
2004-07-17 22:24:05 +02:00
return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
Add support for folding memory operands into AND and IMUL's llvm-svn: 11523
2004-02-17 06:46:06 +01:00
FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
}
Another API change to MRegisterInfo::foldMemoryOperand. Instead of a MachineBasicBlock::iterator take a MachineInstr*. llvm-svn: 12392
2004-03-14 21:14:27 +01:00
MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
unsigned i,
int FrameIndex) const {
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
if (NoFusing) return NULL;
Add an option to disable spill fusing in the X86 backend llvm-svn: 11531
2004-02-17 07:30:34 +01:00
Scrunchify code, by adding helpers. No functionality changes. llvm-svn: 11522
2004-02-17 06:35:13 +01:00
/// FIXME: This should obviously be autogenerated by tablegen when patterns
/// are available!
Add API to check and fold memory operands into instructions. llvm-svn: 11519
2004-02-17 05:33:18 +01:00
MachineBasicBlock& MBB = *MI->getParent();
Scrunchify code, by adding helpers. No functionality changes. llvm-svn: 11522
2004-02-17 06:35:13 +01:00
if (i == 0) {
switch(MI->getOpcode()) {
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::XCHG8rr: return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI);
case X86::XCHG16rr: return MakeMRInst(X86::XCHG16mr,FrameIndex, MI);
case X86::XCHG32rr: return MakeMRInst(X86::XCHG32mr,FrameIndex, MI);
case X86::MOV8rr: return MakeMRInst(X86::MOV8mr , FrameIndex, MI);
case X86::MOV16rr: return MakeMRInst(X86::MOV16mr, FrameIndex, MI);
case X86::MOV32rr: return MakeMRInst(X86::MOV32mr, FrameIndex, MI);
case X86::MOV8ri: return MakeMIInst(X86::MOV8mi , FrameIndex, MI);
case X86::MOV16ri: return MakeMIInst(X86::MOV16mi, FrameIndex, MI);
case X86::MOV32ri: return MakeMIInst(X86::MOV32mi, FrameIndex, MI);
case X86::MUL8r: return MakeMInst( X86::MUL8m , FrameIndex, MI);
case X86::MUL16r: return MakeMInst( X86::MUL16m, FrameIndex, MI);
case X86::MUL32r: return MakeMInst( X86::MUL32m, FrameIndex, MI);
add signed versions of the extra precision multiplies llvm-svn: 21106
2005-04-06 06:19:22 +02:00
case X86::IMUL8r: return MakeMInst( X86::IMUL8m , FrameIndex, MI);
case X86::IMUL16r: return MakeMInst( X86::IMUL16m, FrameIndex, MI);
case X86::IMUL32r: return MakeMInst( X86::IMUL32m, FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::DIV8r: return MakeMInst( X86::DIV8m , FrameIndex, MI);
case X86::DIV16r: return MakeMInst( X86::DIV16m, FrameIndex, MI);
case X86::DIV32r: return MakeMInst( X86::DIV32m, FrameIndex, MI);
case X86::IDIV8r: return MakeMInst( X86::IDIV8m , FrameIndex, MI);
case X86::IDIV16r: return MakeMInst( X86::IDIV16m, FrameIndex, MI);
case X86::IDIV32r: return MakeMInst( X86::IDIV32m, FrameIndex, MI);
case X86::NEG8r: return MakeMInst( X86::NEG8m , FrameIndex, MI);
case X86::NEG16r: return MakeMInst( X86::NEG16m, FrameIndex, MI);
case X86::NEG32r: return MakeMInst( X86::NEG32m, FrameIndex, MI);
case X86::NOT8r: return MakeMInst( X86::NOT8m , FrameIndex, MI);
case X86::NOT16r: return MakeMInst( X86::NOT16m, FrameIndex, MI);
case X86::NOT32r: return MakeMInst( X86::NOT32m, FrameIndex, MI);
case X86::INC8r: return MakeMInst( X86::INC8m , FrameIndex, MI);
case X86::INC16r: return MakeMInst( X86::INC16m, FrameIndex, MI);
case X86::INC32r: return MakeMInst( X86::INC32m, FrameIndex, MI);
case X86::DEC8r: return MakeMInst( X86::DEC8m , FrameIndex, MI);
case X86::DEC16r: return MakeMInst( X86::DEC16m, FrameIndex, MI);
case X86::DEC32r: return MakeMInst( X86::DEC32m, FrameIndex, MI);
case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
Add more ADC and SBB variants llvm-svn: 12607
2004-04-02 09:11:10 +02:00
case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
Add some new instructions. Fix the asm string for sbb32rr llvm-svn: 16759
2004-10-06 06:01:02 +02:00
case X86::SBB8ri: return MakeMIInst(X86::SBB8mi, FrameIndex, MI);
case X86::SBB16ri: return MakeMIInst(X86::SBB16mi, FrameIndex, MI);
Add more ADC and SBB variants llvm-svn: 12607
2004-04-02 09:11:10 +02:00
case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI);
case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI);
case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI);
case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI);
case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI);
case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI);
case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI);
case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI);
case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI);
case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI);
case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI);
case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI);
case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
Add rotate instructions. llvm-svn: 19690
2005-01-19 08:50:03 +01:00
case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI);
case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI);
case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI);
case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI);
case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI);
case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI);
case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI);
case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI);
case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI);
case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI);
case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI);
case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);
Improve coverage of the X86 instruction set by adding 16-bit shift doubles. llvm-svn: 19687
2005-01-19 08:31:24 +01:00
case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI);
case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI);
case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI);
case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::SETBr: return MakeMInst( X86::SETBm, FrameIndex, MI);
case X86::SETAEr: return MakeMInst( X86::SETAEm, FrameIndex, MI);
case X86::SETEr: return MakeMInst( X86::SETEm, FrameIndex, MI);
case X86::SETNEr: return MakeMInst( X86::SETNEm, FrameIndex, MI);
case X86::SETBEr: return MakeMInst( X86::SETBEm, FrameIndex, MI);
case X86::SETAr: return MakeMInst( X86::SETAm, FrameIndex, MI);
case X86::SETSr: return MakeMInst( X86::SETSm, FrameIndex, MI);
case X86::SETNSr: return MakeMInst( X86::SETNSm, FrameIndex, MI);
Add support for the setp instructions llvm-svn: 14140
2004-06-11 06:30:06 +02:00
case X86::SETPr: return MakeMInst( X86::SETPm, FrameIndex, MI);
Add support for SETNPr to lower to memory form. llvm-svn: 19248
2005-01-02 03:37:46 +01:00
case X86::SETNPr: return MakeMInst( X86::SETNPm, FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::SETLr: return MakeMInst( X86::SETLm, FrameIndex, MI);
case X86::SETGEr: return MakeMInst( X86::SETGEm, FrameIndex, MI);
case X86::SETLEr: return MakeMInst( X86::SETLEm, FrameIndex, MI);
case X86::SETGr: return MakeMInst( X86::SETGm, FrameIndex, MI);
case X86::TEST8rr: return MakeMRInst(X86::TEST8mr ,FrameIndex, MI);
case X86::TEST16rr: return MakeMRInst(X86::TEST16mr,FrameIndex, MI);
case X86::TEST32rr: return MakeMRInst(X86::TEST32mr,FrameIndex, MI);
case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
case X86::CMP8rr: return MakeMRInst(X86::CMP8mr , FrameIndex, MI);
case X86::CMP16rr: return MakeMRInst(X86::CMP16mr, FrameIndex, MI);
case X86::CMP32rr: return MakeMRInst(X86::CMP32mr, FrameIndex, MI);
case X86::CMP8ri: return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
Scrunchify code, by adding helpers. No functionality changes. llvm-svn: 11522
2004-02-17 06:35:13 +01:00
}
} else if (i == 1) {
switch(MI->getOpcode()) {
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::XCHG8rr: return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI);
case X86::XCHG16rr: return MakeRMInst(X86::XCHG16rm,FrameIndex, MI);
case X86::XCHG32rr: return MakeRMInst(X86::XCHG32rm,FrameIndex, MI);
case X86::MOV8rr: return MakeRMInst(X86::MOV8rm , FrameIndex, MI);
case X86::MOV16rr: return MakeRMInst(X86::MOV16rm, FrameIndex, MI);
case X86::MOV32rr: return MakeRMInst(X86::MOV32rm, FrameIndex, MI);
Implement spill code folding for all of the conditional move instructions llvm-svn: 12554
2004-03-30 23:29:47 +02:00
case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI);
case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI);
case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI);
case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI);
Implement spill code folding for all of the conditional move instructions llvm-svn: 12554
2004-03-30 23:29:47 +02:00
case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI);
case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI);
Implement spill code folding for all of the conditional move instructions llvm-svn: 12554
2004-03-30 23:29:47 +02:00
case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI);
case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI);
case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI);
case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI);
case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI);
Implement spill code folding for all of the conditional move instructions llvm-svn: 12554
2004-03-30 23:29:47 +02:00
case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI);
case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI);
Add conditional moves for the parity flag. llvm-svn: 19437
2005-01-10 23:09:33 +01:00
case X86::CMOVP16rr: return MakeRMInst(X86::CMOVP16rm , FrameIndex, MI);
case X86::CMOVP32rr: return MakeRMInst(X86::CMOVP32rm , FrameIndex, MI);
case X86::CMOVNP16rr: return MakeRMInst(X86::CMOVNP16rm , FrameIndex, MI);
case X86::CMOVNP32rr: return MakeRMInst(X86::CMOVNP32rm , FrameIndex, MI);
Implement spill code folding for all of the conditional move instructions llvm-svn: 12554
2004-03-30 23:29:47 +02:00
case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI);
case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI);
case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI);
case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI);
case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI);
case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI);
case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI);
case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI);
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
case X86::ADD8rr: return MakeRMInst(X86::ADD8rm , FrameIndex, MI);
case X86::ADD16rr: return MakeRMInst(X86::ADD16rm, FrameIndex, MI);
case X86::ADD32rr: return MakeRMInst(X86::ADD32rm, FrameIndex, MI);
case X86::ADC32rr: return MakeRMInst(X86::ADC32rm, FrameIndex, MI);
case X86::SUB8rr: return MakeRMInst(X86::SUB8rm , FrameIndex, MI);
case X86::SUB16rr: return MakeRMInst(X86::SUB16rm, FrameIndex, MI);
case X86::SUB32rr: return MakeRMInst(X86::SUB32rm, FrameIndex, MI);
case X86::SBB32rr: return MakeRMInst(X86::SBB32rm, FrameIndex, MI);
case X86::AND8rr: return MakeRMInst(X86::AND8rm , FrameIndex, MI);
case X86::AND16rr: return MakeRMInst(X86::AND16rm, FrameIndex, MI);
case X86::AND32rr: return MakeRMInst(X86::AND32rm, FrameIndex, MI);
case X86::OR8rr: return MakeRMInst(X86::OR8rm , FrameIndex, MI);
case X86::OR16rr: return MakeRMInst(X86::OR16rm, FrameIndex, MI);
case X86::OR32rr: return MakeRMInst(X86::OR32rm, FrameIndex, MI);
case X86::XOR8rr: return MakeRMInst(X86::XOR8rm , FrameIndex, MI);
case X86::XOR16rr: return MakeRMInst(X86::XOR16rm, FrameIndex, MI);
case X86::XOR32rr: return MakeRMInst(X86::XOR32rm, FrameIndex, MI);
case X86::TEST8rr: return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
case X86::TEST16rr: return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
case X86::TEST32rr: return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
case X86::IMUL16rr: return MakeRMInst(X86::IMUL16rm,FrameIndex, MI);
case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI);
case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI);
case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI);
case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI);
case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
case X86::MOVZX32rr8: return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
Scrunchify code, by adding helpers. No functionality changes. llvm-svn: 11522
2004-02-17 06:35:13 +01:00
}
Add a (hidden) option to print instructions that fail to fuse. It's looking like compares and test's would be the next huge win... llvm-svn: 11539
2004-02-17 09:03:47 +01:00
}
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
if (PrintFailedFusing)
std::cerr << "We failed to fuse: " << *MI;
return NULL;
Add API to check and fold memory operands into instructions. llvm-svn: 11519
2004-02-17 05:33:18 +01:00
}
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
// hasFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
//
static bool hasFP(MachineFunction &MF) {
Spell out `NoFramePointerElim' for readability. llvm-svn: 14299
2004-06-21 23:17:44 +02:00
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
Added methods to read/write values to stack in .h, fixed implementation in .cpp to return the iterator correctly. llvm-svn: 4827
2002-11-22 23:43:47 +01:00
}
The prologue/epilogue related method calls have no reason to return a value, make them return void. This allows us to avoid some costly MBB.size() calls llvm-svn: 11448
2004-02-14 20:49:54 +01:00
void X86RegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
if (hasFP(MF)) {
// If we have a frame pointer, turn the adjcallstackup instruction into a
// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
// <amt>'
The prologue/epilogue related method calls have no reason to return a value, make them return void. This allows us to avoid some costly MBB.size() calls llvm-svn: 11448
2004-02-14 20:49:54 +01:00
MachineInstr *Old = I;
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
unsigned Amount = Old->getOperand(0).getImmedValue();
if (Amount != 0) {
Implement code to keep the stack pointer aligned to an 8 byte boundary. This improves the performance of the power benchmark by a few percent. This will be neccesary for SSE code, which requires 16 byte alignment of the stack. llvm-svn: 5320
2003-01-16 03:20:12 +01:00
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
// alignment boundary.
Convert to the new TargetMachine interface. llvm-svn: 13952
2004-06-02 07:55:25 +02:00
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
Implement code to keep the stack pointer aligned to an 8 byte boundary. This improves the performance of the power benchmark by a few percent. This will be neccesary for SSE code, which requires 16 byte alignment of the stack. llvm-svn: 5320
2003-01-16 03:20:12 +01:00
Amount = (Amount+Align-1)/Align*Align;
switch to having the callee pop stack operands for fastcc. This is currently buggy do not use llvm-svn: 21984
2005-05-13 23:44:04 +02:00
MachineInstr *New = 0;
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
Eliminate all remaining tabs and trailing spaces. llvm-svn: 22523
2005-07-27 08:12:32 +02:00
New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
Move MOTy::UseType enum into MachineOperand. This eliminates the switch statements in the constructors and simplifies the implementation of the getUseType() member function. You will have to specify defs using MachineOperand::Def instead of MOTy::Def though (similarly for Use and UseAndDef). llvm-svn: 11715
2004-02-22 20:23:26 +01:00
.addZImm(Amount);
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
} else {
Eliminate all remaining tabs and trailing spaces. llvm-svn: 22523
2005-07-27 08:12:32 +02:00
assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
switch to having the callee pop stack operands for fastcc. This is currently buggy do not use llvm-svn: 21984
2005-05-13 23:44:04 +02:00
// factor out the amount the callee already popped.
unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
Amount -= CalleeAmt;
if (Amount)
New = BuildMI(X86::ADD32ri, 1, X86::ESP,
MachineOperand::UseAndDef).addZImm(Amount);
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
}
The prologue/epilogue related method calls have no reason to return a value, make them return void. This allows us to avoid some costly MBB.size() calls llvm-svn: 11448
2004-02-14 20:49:54 +01:00
// Replace the pseudo instruction with a new instruction...
switch to having the callee pop stack operands for fastcc. This is currently buggy do not use llvm-svn: 21984
2005-05-13 23:44:04 +02:00
if (New) MBB.insert(I, New);
}
} else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
// If we are performing frame pointer elimination and if the callee pops
// something off the stack pointer, add it back. We do this until we have
// more advanced stack pointer tracking ability.
if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
Eliminate all remaining tabs and trailing spaces. llvm-svn: 22523
2005-07-27 08:12:32 +02:00
MachineInstr *New =
switch to having the callee pop stack operands for fastcc. This is currently buggy do not use llvm-svn: 21984
2005-05-13 23:44:04 +02:00
BuildMI(X86::SUB32ri, 1, X86::ESP,
MachineOperand::UseAndDef).addZImm(CalleeAmt);
The prologue/epilogue related method calls have no reason to return a value, make them return void. This allows us to avoid some costly MBB.size() calls llvm-svn: 11448
2004-02-14 20:49:54 +01:00
MBB.insert(I, New);
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
}
}
The prologue/epilogue related method calls have no reason to return a value, make them return void. This allows us to avoid some costly MBB.size() calls llvm-svn: 11448
2004-02-14 20:49:54 +01:00
MBB.erase(I);
Added support for callee- and caller-save registers. llvm-svn: 4897
2002-12-04 00:11:21 +01:00
}
Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent llvm-svn: 15739
2004-08-15 00:05:10 +02:00
void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
* Move frame and constant pool indexes to first argument of memory reference so we can put an offset in there as well... * Fix long/ulong stuff llvm-svn: 5231
2003-01-13 01:50:33 +01:00
unsigned i = 0;
Change MachineBasicBlock's vector of MachineInstr pointers into an ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. llvm-svn: 11340
2004-02-12 03:27:10 +01:00
MachineInstr &MI = *II;
Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent llvm-svn: 15739
2004-08-15 00:05:10 +02:00
MachineFunction &MF = *MI.getParent()->getParent();
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
while (!MI.getOperand(i).isFrameIndex()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
* Move frame and constant pool indexes to first argument of memory reference so we can put an offset in there as well... * Fix long/ulong stuff llvm-svn: 5231
2003-01-13 01:50:33 +01:00
int FrameIndex = MI.getOperand(i).getFrameIndex();
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
// This must be part of a four operand memory reference. Replace the
* Move frame and constant pool indexes to first argument of memory reference so we can put an offset in there as well... * Fix long/ulong stuff llvm-svn: 5231
2003-01-13 01:50:33 +01:00
// FrameIndex with base register with EBP. Add add an offset to the offset.
MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
Added support for callee- and caller-save registers. llvm-svn: 4897
2002-12-04 00:11:21 +01:00
* Move frame and constant pool indexes to first argument of memory reference so we can put an offset in there as well... * Fix long/ulong stuff llvm-svn: 5231
2003-01-13 01:50:33 +01:00
// Now add the frame object offset to the offset from EBP.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
Handle frame offset due to return address pushed on the stack llvm-svn: 5319
2003-01-15 23:57:35 +01:00
MI.getOperand(i+3).getImmedValue()+4;
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
Disable the leaf function optimization, which is apparently not legal on X86/linux. :( The problem is that a signal delivered while the function is executing could clobber the functions stack. This is a partial fix for PR41. llvm-svn: 9113
2003-10-14 20:52:41 +02:00
if (!hasFP(MF))
Offset += MF.getFrameInfo()->getStackSize();
Fix the 'have a framepointer' case, so that the frame pointer always points to the old saved EBP. llvm-svn: 11455
2004-02-15 01:15:37 +01:00
else
Offset += 4; // Skip the saved EBP
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
* Move frame and constant pool indexes to first argument of memory reference so we can put an offset in there as well... * Fix long/ulong stuff llvm-svn: 5231
2003-01-13 01:50:33 +01:00
MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
Added support for callee- and caller-save registers. llvm-svn: 4897
2002-12-04 00:11:21 +01:00
}
Implemented functions for emitting prologues and epilogues; removed EBP from the list of callee-saved registers (it isn't one). llvm-svn: 4929
2002-12-05 00:57:03 +01:00
The prologue/epilogue related method calls have no reason to return a value, make them return void. This allows us to avoid some costly MBB.size() calls llvm-svn: 11448
2004-02-14 20:49:54 +01:00
void
X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
if (hasFP(MF)) {
// Create a frame entry for the EBP register that must be saved.
Fix the 'have a framepointer' case, so that the frame pointer always points to the old saved EBP. llvm-svn: 11455
2004-02-15 01:15:37 +01:00
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
"Slot for EBP register must be last in order to be found!");
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
}
}
The prologue/epilogue related method calls have no reason to return a value, make them return void. This allows us to avoid some costly MBB.size() calls llvm-svn: 11448
2004-02-14 20:49:54 +01:00
void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
Simplify interfaces used by regalloc to insert code llvm-svn: 5052
2002-12-15 21:06:35 +01:00
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
Handle frame offset due to return address pushed on the stack llvm-svn: 5319
2003-01-15 23:57:35 +01:00
MachineFrameInfo *MFI = MF.getFrameInfo();
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
MachineInstr *MI;
Implemented functions for emitting prologues and epilogues; removed EBP from the list of callee-saved registers (it isn't one). llvm-svn: 4929
2002-12-05 00:57:03 +01:00
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
// Get the number of bytes to allocate from the FrameInfo
Rename FunctionFrameInfo to MachineFrameInfo llvm-svn: 5201
2002-12-28 22:08:28 +01:00
unsigned NumBytes = MFI->getStackSize();
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
if (hasFP(MF)) {
// Get the offset of the stack slot for the EBP register... which is
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
Fix the 'have a framepointer' case, so that the frame pointer always points to the old saved EBP. llvm-svn: 11455
2004-02-15 01:15:37 +01:00
int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
Round number of bytes allocated on the stack up to a multiple of 4 so that the stack remains aligned llvm-svn: 5095
2002-12-17 04:15:26 +01:00
Output a contorted sequence of instructions to make sure that we don't access off the bottom of the stack. This fixes PR#41 llvm-svn: 9114
2003-10-14 21:09:05 +02:00
if (NumBytes) { // adjust stack pointer: ESP -= numbytes
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
Move MOTy::UseType enum into MachineOperand. This eliminates the switch statements in the constructors and simplifies the implementation of the getUseType() member function. You will have to specify defs using MachineOperand::Def instead of MOTy::Def though (similarly for Use and UseAndDef). llvm-svn: 11715
2004-02-22 20:23:26 +01:00
.addZImm(NumBytes);
Change MachineBasicBlock's vector of MachineInstr pointers into an ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. llvm-svn: 11340
2004-02-12 03:27:10 +01:00
MBB.insert(MBBI, MI);
Output a contorted sequence of instructions to make sure that we don't access off the bottom of the stack. This fixes PR#41 llvm-svn: 9114
2003-10-14 21:09:05 +02:00
}
// Save EBP into the appropriate stack slot...
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP
Eliminate all remaining tabs and trailing spaces. llvm-svn: 22523
2005-07-27 08:12:32 +02:00
X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
Change MachineBasicBlock's vector of MachineInstr pointers into an ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. llvm-svn: 11340
2004-02-12 03:27:10 +01:00
MBB.insert(MBBI, MI);
Output a contorted sequence of instructions to make sure that we don't access off the bottom of the stack. This fixes PR#41 llvm-svn: 9114
2003-10-14 21:09:05 +02:00
// Update EBP with the new base value...
Fix the 'have a framepointer' case, so that the frame pointer always points to the old saved EBP. llvm-svn: 11455
2004-02-15 01:15:37 +01:00
if (NumBytes == 4) // mov EBP, ESP
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
Output a contorted sequence of instructions to make sure that we don't access off the bottom of the stack. This fixes PR#41 llvm-svn: 9114
2003-10-14 21:09:05 +02:00
else // lea EBP, [ESP+StackSize]
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
Output a contorted sequence of instructions to make sure that we don't access off the bottom of the stack. This fixes PR#41 llvm-svn: 9114
2003-10-14 21:09:05 +02:00
Change MachineBasicBlock's vector of MachineInstr pointers into an ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. llvm-svn: 11340
2004-02-12 03:27:10 +01:00
MBB.insert(MBBI, MI);
Output a contorted sequence of instructions to make sure that we don't access off the bottom of the stack. This fixes PR#41 llvm-svn: 9114
2003-10-14 21:09:05 +02:00
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
} else {
There is no reason to align the stack pointer if there are no callees of this function! llvm-svn: 11450
2004-02-14 21:11:07 +01:00
if (MFI->hasCalls()) {
// When we have no frame pointer, we reserve argument space for call sites
// in the function immediately on entry to the current function. This
// eliminates the need for add/sub ESP brackets around call sites.
//
NumBytes += MFI->getMaxCallFrameSize();
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
There is no reason to align the stack pointer if there are no callees of this function! llvm-svn: 11450
2004-02-14 21:11:07 +01:00
// Round the size to a multiple of the alignment (don't forget the 4 byte
// offset though).
Convert to the new TargetMachine interface. llvm-svn: 13952
2004-06-02 07:55:25 +02:00
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
There is no reason to align the stack pointer if there are no callees of this function! llvm-svn: 11450
2004-02-14 21:11:07 +01:00
NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
}
Implement code to keep the stack pointer aligned to an 8 byte boundary. This improves the performance of the power benchmark by a few percent. This will be neccesary for SSE code, which requires 16 byte alignment of the stack. llvm-svn: 5320
2003-01-16 03:20:12 +01:00
Handle frame offset due to return address pushed on the stack llvm-svn: 5319
2003-01-15 23:57:35 +01:00
// Update frame info to pretend that this is part of the stack...
MFI->setStackSize(NumBytes);
Implemented functions for emitting prologues and epilogues; removed EBP from the list of callee-saved registers (it isn't one). llvm-svn: 4929
2002-12-05 00:57:03 +01:00
Output a contorted sequence of instructions to make sure that we don't access off the bottom of the stack. This fixes PR#41 llvm-svn: 9114
2003-10-14 21:09:05 +02:00
if (NumBytes) {
// adjust stack pointer: ESP -= numbytes
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
Move MOTy::UseType enum into MachineOperand. This eliminates the switch statements in the constructors and simplifies the implementation of the getUseType() member function. You will have to specify defs using MachineOperand::Def instead of MOTy::Def though (similarly for Use and UseAndDef). llvm-svn: 11715
2004-02-22 20:23:26 +01:00
.addZImm(NumBytes);
Output a contorted sequence of instructions to make sure that we don't access off the bottom of the stack. This fixes PR#41 llvm-svn: 9114
2003-10-14 21:09:05 +02:00
MBB.insert(MBBI, MI);
}
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
}
Implemented functions for emitting prologues and epilogues; removed EBP from the list of callee-saved registers (it isn't one). llvm-svn: 4929
2002-12-05 00:57:03 +01:00
}
The prologue/epilogue related method calls have no reason to return a value, make them return void. This allows us to avoid some costly MBB.size() calls llvm-svn: 11448
2004-02-14 20:49:54 +01:00
void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
Rename FunctionFrameInfo to MachineFrameInfo llvm-svn: 5201
2002-12-28 22:08:28 +01:00
const MachineFrameInfo *MFI = MF.getFrameInfo();
Use newly added next() and prior() utility functions. llvm-svn: 11430
2004-02-14 02:18:34 +01:00
MachineBasicBlock::iterator MBBI = prior(MBB.end());
Add some new instructions llvm-svn: 22036
2005-05-15 01:35:21 +02:00
switch (MBBI->getOpcode()) {
case X86::RET:
case X86::RETI:
case X86::TAILJMPd:
case X86::TAILJMPr:
case X86::TAILJMPm: break; // These are ok
default:
assert(0 && "Can only insert epilog into returning blocks");
}
Implemented functions for emitting prologues and epilogues; removed EBP from the list of callee-saved registers (it isn't one). llvm-svn: 4929
2002-12-05 00:57:03 +01:00
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
if (hasFP(MF)) {
// Get the offset of the stack slot for the EBP register... which is
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
Handle frame offset due to return address pushed on the stack llvm-svn: 5319
2003-01-15 23:57:35 +01:00
int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
// mov ESP, EBP
When emitting the function epilog, check to see if there already a stack adjustment. If so, we merge the adjustment into the existing one. This allows us to generate: caller2: sub %ESP, 12 mov DWORD PTR [%ESP], 0 mov %EAX, 1234567890 mov %EDX, 0 call func2 add %ESP, 8 ret 4 intead of: caller2: sub %ESP, 12 mov DWORD PTR [%ESP], 0 mov %EAX, 1234567890 mov %EDX, 0 call func2 sub %ESP, 4 add %ESP, 12 ret 4 for X86/fast-cc-merge-stack-adj.ll llvm-svn: 22038
2005-05-15 01:53:43 +02:00
BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
Fix the 'have a framepointer' case, so that the frame pointer always points to the old saved EBP. llvm-svn: 11455
2004-02-15 01:15:37 +01:00
// pop EBP
When emitting the function epilog, check to see if there already a stack adjustment. If so, we merge the adjustment into the existing one. This allows us to generate: caller2: sub %ESP, 12 mov DWORD PTR [%ESP], 0 mov %EAX, 1234567890 mov %EDX, 0 call func2 add %ESP, 8 ret 4 intead of: caller2: sub %ESP, 12 mov DWORD PTR [%ESP], 0 mov %EAX, 1234567890 mov %EDX, 0 call func2 sub %ESP, 4 add %ESP, 12 ret 4 for X86/fast-cc-merge-stack-adj.ll llvm-svn: 22038
2005-05-15 01:53:43 +02:00
BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
} else {
// Get the number of bytes allocated from the FrameInfo...
Rename FunctionFrameInfo to MachineFrameInfo llvm-svn: 5201
2002-12-28 22:08:28 +01:00
unsigned NumBytes = MFI->getStackSize();
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
if (NumBytes) { // adjust stack pointer back: ESP += numbytes
When emitting the function epilog, check to see if there already a stack adjustment. If so, we merge the adjustment into the existing one. This allows us to generate: caller2: sub %ESP, 12 mov DWORD PTR [%ESP], 0 mov %EAX, 1234567890 mov %EDX, 0 call func2 add %ESP, 8 ret 4 intead of: caller2: sub %ESP, 12 mov DWORD PTR [%ESP], 0 mov %EAX, 1234567890 mov %EDX, 0 call func2 sub %ESP, 4 add %ESP, 12 ret 4 for X86/fast-cc-merge-stack-adj.ll llvm-svn: 22038
2005-05-15 01:53:43 +02:00
// If there is an ADD32ri or SUB32ri of ESP immediately before this
// instruction, merge the two instructions.
if (MBBI != MBB.begin()) {
MachineBasicBlock::iterator PI = prior(MBBI);
if (PI->getOpcode() == X86::ADD32ri &&
PI->getOperand(0).getReg() == X86::ESP) {
NumBytes += PI->getOperand(1).getImmedValue();
MBB.erase(PI);
} else if (PI->getOpcode() == X86::SUB32ri &&
PI->getOperand(0).getReg() == X86::ESP) {
NumBytes -= PI->getOperand(1).getImmedValue();
Teach reginfo how to deal with ADJSTACKPTRri, allowing us to generate: add %ESP, 20 jmp %EDX # TAIL CALL instead of: add %ESP, -8 add %ESP, 28 jmp %EDX # TAIL CALL llvm-svn: 22047
2005-05-15 07:49:58 +02:00
MBB.erase(PI);
} else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
NumBytes += PI->getOperand(1).getImmedValue();
When emitting the function epilog, check to see if there already a stack adjustment. If so, we merge the adjustment into the existing one. This allows us to generate: caller2: sub %ESP, 12 mov DWORD PTR [%ESP], 0 mov %EAX, 1234567890 mov %EDX, 0 call func2 add %ESP, 8 ret 4 intead of: caller2: sub %ESP, 12 mov DWORD PTR [%ESP], 0 mov %EAX, 1234567890 mov %EDX, 0 call func2 sub %ESP, 4 add %ESP, 12 ret 4 for X86/fast-cc-merge-stack-adj.ll llvm-svn: 22038
2005-05-15 01:53:43 +02:00
MBB.erase(PI);
}
}
if (NumBytes > 0)
BuildMI(MBB, MBBI, X86::ADD32ri, 2)
.addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes);
else if ((int)NumBytes < 0)
BuildMI(MBB, MBBI, X86::SUB32ri, 2)
.addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes);
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
}
}
}
Switch over to TableGen generated register file description llvm-svn: 7511
2003-08-03 17:48:14 +02:00
#include "X86GenRegisterInfo.inc"
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
const TargetRegisterClass*
X86RegisterInfo::getRegClassForType(const Type* Ty) const {
Rename Type::PrimitiveID to TypeId and ::getPrimitiveID() to ::getTypeID() llvm-svn: 14201
2004-06-17 20:19:28 +02:00
switch (Ty->getTypeID()) {
* Move frame and constant pool indexes to first argument of memory reference so we can put an offset in there as well... * Fix long/ulong stuff llvm-svn: 5231
2003-01-13 01:50:33 +01:00
case Type::LongTyID:
case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
default: assert(0 && "Invalid type to getClass!");
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
case Type::BoolTyID:
case Type::SByteTyID:
Rename register classes to be upper case to make it obvious that they are X86 specific in the tree patterns llvm-svn: 7578
2003-08-04 22:58:29 +02:00
case Type::UByteTyID: return &R8Instance;
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
case Type::ShortTyID:
Rename register classes to be upper case to make it obvious that they are X86 specific in the tree patterns llvm-svn: 7578
2003-08-04 22:58:29 +02:00
case Type::UShortTyID: return &R16Instance;
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
case Type::IntTyID:
case Type::UIntTyID:
Rename register classes to be upper case to make it obvious that they are X86 specific in the tree patterns llvm-svn: 7578
2003-08-04 22:58:29 +02:00
case Type::PointerTyID: return &R32Instance;
Change MRegisterInfo::foldMemoryOperand to return the folded instruction to make the API more flexible. llvm-svn: 12386
2004-03-14 08:19:51 +01:00
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
case Type::FloatTyID:
Rename register classes to be upper case to make it obvious that they are X86 specific in the tree patterns llvm-svn: 7578
2003-08-04 22:58:29 +02:00
case Type::DoubleTyID: return &RFPInstance;
*** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. llvm-svn: 5186
2002-12-28 21:32:28 +01:00
}
Implemented functions for emitting prologues and epilogues; removed EBP from the list of callee-saved registers (it isn't one). llvm-svn: 4929
2002-12-05 00:57:03 +01:00
}
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