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llvm-mirror/test/CodeGen/X86/prefetch.ll

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Prefetch has a MemOperand now. FileCheckize a test. This finishes up 8460971. llvm-svn: 119848
2010-11-19 22:49:38 +01:00
; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s
Add test for r146163. llvm-svn: 146167
2011-12-08 20:21:39 +01:00
; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
Fix PRFCHW test on non-x86 builds - 'prefetch' intrinsics are only lowered when SSE is available. On non-X86 builds, 'generic' CPU is used and stops lowering any prefetch intrinsics. llvm-svn: 178046
2013-03-26 19:15:45 +01:00
; RUN: llc < %s -march=x86 -mattr=+sse -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHW
Attempt to fix llvm-ppc64-linux2 buildbot failure by adding -march=x86 to SLM test. llvm-svn: 190958
2013-09-18 23:39:33 +02:00
; RUN: llc < %s -march=x86 -mcpu=slm | FileCheck %s -check-prefix=SLM
Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar, bulldozer and piledriver. Support for the instruction itself seems to have already been added in r178040. Differential Revision: http://llvm-reviews.chandlerc.com/D1933 llvm-svn: 192828
2013-10-16 21:04:11 +02:00
; RUN: llc < %s -march=x86 -mcpu=btver2 | FileCheck %s -check-prefix=PRFCHW
; RUN: llc < %s -march=x86 -mcpu=btver2 -mattr=-prfchw | FileCheck %s -check-prefix=NOPRFCHW
Add test for r146163. llvm-svn: 146167
2011-12-08 20:21:39 +01:00
; rdar://10538297
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. llvm-svn: 48042
2008-03-08 01:58:38 +01:00
define void @t(i8* %ptr) nounwind {
entry:
Prefetch has a MemOperand now. FileCheckize a test. This finishes up 8460971. llvm-svn: 119848
2010-11-19 22:49:38 +01:00
; CHECK: prefetcht2
; CHECK: prefetcht1
; CHECK: prefetcht0
; CHECK: prefetchnta
Add PREFETCHW codegen support - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
2013-03-26 18:47:11 +01:00
; PRFCHW: prefetchw
Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar, bulldozer and piledriver. Support for the instruction itself seems to have already been added in r178040. Differential Revision: http://llvm-reviews.chandlerc.com/D1933 llvm-svn: 192828
2013-10-16 21:04:11 +02:00
; NOPRFCHW-NOT: prefetchw
Verify that llvm can generate the prefetchw instruction when the CPU is Atom Silvermont. Patch by Sriram Murali. llvm-svn: 190957
2013-09-18 23:08:09 +02:00
; SLM: prefetchw
Add one more argument to the prefetch intrinsic to indicate whether it's a data or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
2011-06-14 06:58:37 +02:00
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
Add PREFETCHW codegen support - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
2013-03-26 18:47:11 +01:00
tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. llvm-svn: 48042
2008-03-08 01:58:38 +01:00
ret void
}
Add one more argument to the prefetch intrinsic to indicate whether it's a data or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
2011-06-14 06:58:37 +02:00
declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
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