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llvm-mirror/test/CodeGen/X86/sse42.ll

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290
2009-09-09 01:54:48 +02:00
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
ret i32 %tmp
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
; X32: _crc32_32_8:
Fixed the encoding problems of the crc32 instructions. All had the Operand size override prefix and only the r/m16 forms should have had that. Also for variant one, the AT&T syntax, added suffixes to all forms. Also added the missing 64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and tweaked one test case to add the needed suffixes. llvm-svn: 98980
2010-03-19 21:04:42 +01:00
; X32: crc32b 8(%esp), %eax
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
; X64: _crc32_32_8:
Fix a batch of x86 tests to be coalescer independent. Most of these tests require a single mov instruction that can come either before or after a 2-addr instruction. -join-physregs changes the behavior, but the results are equivalent. llvm-svn: 130891
2011-05-05 01:54:51 +02:00
; X64: crc32b %sil,
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
}
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
ret i32 %tmp
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
; X32: _crc32_32_16:
Fixed the encoding problems of the crc32 instructions. All had the Operand size override prefix and only the r/m16 forms should have had that. Also for variant one, the AT&T syntax, added suffixes to all forms. Also added the missing 64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and tweaked one test case to add the needed suffixes. llvm-svn: 98980
2010-03-19 21:04:42 +01:00
; X32: crc32w 8(%esp), %eax
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
; X64: _crc32_32_16:
Fix a batch of x86 tests to be coalescer independent. Most of these tests require a single mov instruction that can come either before or after a 2-addr instruction. -join-physregs changes the behavior, but the results are equivalent. llvm-svn: 130891
2011-05-05 01:54:51 +02:00
; X64: crc32w %si,
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
}
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
ret i32 %tmp
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
; X32: _crc32_32_32:
Fixed the encoding problems of the crc32 instructions. All had the Operand size override prefix and only the r/m16 forms should have had that. Also for variant one, the AT&T syntax, added suffixes to all forms. Also added the missing 64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and tweaked one test case to add the needed suffixes. llvm-svn: 98980
2010-03-19 21:04:42 +01:00
; X32: crc32l 8(%esp), %eax
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
; X64: _crc32_32_32:
Fix a batch of x86 tests to be coalescer independent. Most of these tests require a single mov instruction that can come either before or after a 2-addr instruction. -join-physregs changes the behavior, but the results are equivalent. llvm-svn: 130891
2011-05-05 01:54:51 +02:00
; X64: crc32l %esi,
Add crc32 instruction and intrinsics. Add a new class of prefix bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
2009-08-08 23:55:08 +02:00
}
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
2011-05-27 01:13:19 +02:00
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