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llvm-mirror/lib/Target/ARM/ARMSchedule.td

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Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. llvm-svn: 73747
2009-06-19 03:51:50 +02:00
//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM
//
Update Cortex-A8 instruction itineraries for integer instructions. llvm-svn: 79436
2009-08-19 20:00:44 +02:00
def IIC_iALUx : InstrItinClass;
def IIC_iALUi : InstrItinClass;
def IIC_iALUr : InstrItinClass;
def IIC_iALUsi : InstrItinClass;
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP pipeline forwarding path. llvm-svn: 115098
2010-09-30 00:42:35 +02:00
def IIC_iALUsir : InstrItinClass;
Update Cortex-A8 instruction itineraries for integer instructions. llvm-svn: 79436
2009-08-19 20:00:44 +02:00
def IIC_iALUsr : InstrItinClass;
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. llvm-svn: 115008
2010-09-29 02:27:46 +02:00
def IIC_iBITi : InstrItinClass;
def IIC_iBITr : InstrItinClass;
def IIC_iBITsi : InstrItinClass;
def IIC_iBITsr : InstrItinClass;
Update Cortex-A8 instruction itineraries for integer instructions. llvm-svn: 79436
2009-08-19 20:00:44 +02:00
def IIC_iUNAr : InstrItinClass;
def IIC_iUNAsi : InstrItinClass;
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 02:49:35 +02:00
def IIC_iEXTr : InstrItinClass;
def IIC_iEXTAr : InstrItinClass;
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. llvm-svn: 115008
2010-09-29 02:27:46 +02:00
def IIC_iEXTAsr : InstrItinClass;
Update Cortex-A8 instruction itineraries for integer instructions. llvm-svn: 79436
2009-08-19 20:00:44 +02:00
def IIC_iCMPi : InstrItinClass;
def IIC_iCMPr : InstrItinClass;
def IIC_iCMPsi : InstrItinClass;
def IIC_iCMPsr : InstrItinClass;
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 02:49:25 +02:00
def IIC_iTSTi : InstrItinClass;
def IIC_iTSTr : InstrItinClass;
def IIC_iTSTsi : InstrItinClass;
def IIC_iTSTsr : InstrItinClass;
Update Cortex-A8 instruction itineraries for integer instructions. llvm-svn: 79436
2009-08-19 20:00:44 +02:00
def IIC_iMOVi : InstrItinClass;
def IIC_iMOVr : InstrItinClass;
def IIC_iMOVsi : InstrItinClass;
def IIC_iMOVsr : InstrItinClass;
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 02:49:25 +02:00
def IIC_iMOVix2 : InstrItinClass;
Sorry, several patches in one. TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
2011-01-20 09:34:58 +01:00
def IIC_iMOVix2addpc : InstrItinClass;
def IIC_iMOVix2ld : InstrItinClass;
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 02:49:25 +02:00
def IIC_iMVNi : InstrItinClass;
def IIC_iMVNr : InstrItinClass;
def IIC_iMVNsi : InstrItinClass;
def IIC_iMVNsr : InstrItinClass;
Update Cortex-A8 instruction itineraries for integer instructions. llvm-svn: 79436
2009-08-19 20:00:44 +02:00
def IIC_iCMOVi : InstrItinClass;
def IIC_iCMOVr : InstrItinClass;
def IIC_iCMOVsi : InstrItinClass;
def IIC_iCMOVsr : InstrItinClass;
Conditional moves are slightly more expensive than moves. llvm-svn: 118985
2010-11-13 06:14:20 +01:00
def IIC_iCMOVix2 : InstrItinClass;
Update Cortex-A8 instruction itineraries for integer instructions. llvm-svn: 79436
2009-08-19 20:00:44 +02:00
def IIC_iMUL16 : InstrItinClass;
def IIC_iMAC16 : InstrItinClass;
def IIC_iMUL32 : InstrItinClass;
def IIC_iMAC32 : InstrItinClass;
def IIC_iMUL64 : InstrItinClass;
def IIC_iMAC64 : InstrItinClass;
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 03:08:25 +02:00
def IIC_iLoad_i : InstrItinClass;
def IIC_iLoad_r : InstrItinClass;
def IIC_iLoad_si : InstrItinClass;
def IIC_iLoad_iu : InstrItinClass;
def IIC_iLoad_ru : InstrItinClass;
def IIC_iLoad_siu : InstrItinClass;
def IIC_iLoad_bh_i : InstrItinClass;
def IIC_iLoad_bh_r : InstrItinClass;
def IIC_iLoad_bh_si : InstrItinClass;
def IIC_iLoad_bh_iu : InstrItinClass;
def IIC_iLoad_bh_ru : InstrItinClass;
def IIC_iLoad_bh_siu : InstrItinClass;
def IIC_iLoad_d_i : InstrItinClass;
def IIC_iLoad_d_r : InstrItinClass;
def IIC_iLoad_d_ru : InstrItinClass;
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 08:27:31 +02:00
def IIC_iLoad_m : InstrItinClass<0>; // micro-coded
def IIC_iLoad_mu : InstrItinClass<0>; // micro-coded
def IIC_iLoad_mBr : InstrItinClass<0>; // micro-coded
def IIC_iPop : InstrItinClass<0>; // micro-coded
def IIC_iPop_Br : InstrItinClass<0>; // micro-coded
More pseudo instruction scheduling itinerary fixes. llvm-svn: 114768
2010-09-25 00:41:41 +02:00
def IIC_iLoadiALU : InstrItinClass;
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 03:08:25 +02:00
def IIC_iStore_i : InstrItinClass;
def IIC_iStore_r : InstrItinClass;
def IIC_iStore_si : InstrItinClass;
def IIC_iStore_iu : InstrItinClass;
def IIC_iStore_ru : InstrItinClass;
def IIC_iStore_siu : InstrItinClass;
def IIC_iStore_bh_i : InstrItinClass;
def IIC_iStore_bh_r : InstrItinClass;
def IIC_iStore_bh_si : InstrItinClass;
def IIC_iStore_bh_iu : InstrItinClass;
def IIC_iStore_bh_ru : InstrItinClass;
def IIC_iStore_bh_siu : InstrItinClass;
def IIC_iStore_d_i : InstrItinClass;
def IIC_iStore_d_r : InstrItinClass;
def IIC_iStore_d_ru : InstrItinClass;
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 08:27:31 +02:00
def IIC_iStore_m : InstrItinClass<0>; // micro-coded
def IIC_iStore_mu : InstrItinClass<0>; // micro-coded
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160
2010-11-03 07:34:55 +01:00
def IIC_Preload : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_Br : InstrItinClass;
Add Cortex-A8 VFP model. llvm-svn: 82483
2009-09-21 22:52:17 +02:00
def IIC_fpSTAT : InstrItinClass;
def IIC_fpUNA32 : InstrItinClass;
def IIC_fpUNA64 : InstrItinClass;
def IIC_fpCMP32 : InstrItinClass;
def IIC_fpCMP64 : InstrItinClass;
def IIC_fpCVTSD : InstrItinClass;
def IIC_fpCVTDS : InstrItinClass;
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. llvm-svn: 100647
2010-04-07 20:19:46 +02:00
def IIC_fpCVTSH : InstrItinClass;
def IIC_fpCVTHS : InstrItinClass;
Add Cortex-A8 VFP model. llvm-svn: 82483
2009-09-21 22:52:17 +02:00
def IIC_fpCVTIS : InstrItinClass;
def IIC_fpCVTID : InstrItinClass;
def IIC_fpCVTSI : InstrItinClass;
def IIC_fpCVTDI : InstrItinClass;
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
2010-04-07 20:20:02 +02:00
def IIC_fpMOVIS : InstrItinClass;
def IIC_fpMOVID : InstrItinClass;
def IIC_fpMOVSI : InstrItinClass;
def IIC_fpMOVDI : InstrItinClass;
Add Cortex-A8 VFP model. llvm-svn: 82483
2009-09-21 22:52:17 +02:00
def IIC_fpALU32 : InstrItinClass;
def IIC_fpALU64 : InstrItinClass;
def IIC_fpMUL32 : InstrItinClass;
def IIC_fpMUL64 : InstrItinClass;
def IIC_fpMAC32 : InstrItinClass;
def IIC_fpMAC64 : InstrItinClass;
def IIC_fpDIV32 : InstrItinClass;
def IIC_fpDIV64 : InstrItinClass;
def IIC_fpSQRT32 : InstrItinClass;
def IIC_fpSQRT64 : InstrItinClass;
def IIC_fpLoad32 : InstrItinClass;
def IIC_fpLoad64 : InstrItinClass;
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. llvm-svn: 115898
2010-10-07 03:50:48 +02:00
def IIC_fpLoad_m : InstrItinClass<0>; // micro-coded
def IIC_fpLoad_mu : InstrItinClass<0>; // micro-coded
Add Cortex-A8 VFP model. llvm-svn: 82483
2009-09-21 22:52:17 +02:00
def IIC_fpStore32 : InstrItinClass;
def IIC_fpStore64 : InstrItinClass;
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. llvm-svn: 115898
2010-10-07 03:50:48 +02:00
def IIC_fpStore_m : InstrItinClass<0>; // micro-coded
def IIC_fpStore_mu : InstrItinClass<0>; // micro-coded
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VLD1 : InstrItinClass;
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 03:03:04 +02:00
def IIC_VLD1x2 : InstrItinClass;
def IIC_VLD1x3 : InstrItinClass;
def IIC_VLD1x4 : InstrItinClass;
def IIC_VLD1u : InstrItinClass;
def IIC_VLD1x2u : InstrItinClass;
def IIC_VLD1x3u : InstrItinClass;
def IIC_VLD1x4u : InstrItinClass;
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. llvm-svn: 117964
2010-11-01 23:04:05 +01:00
def IIC_VLD1ln : InstrItinClass;
def IIC_VLD1lnu : InstrItinClass;
Add NEON VLD1-dup instructions (load 1 element to all lanes). llvm-svn: 120194
2010-11-27 07:35:16 +01:00
def IIC_VLD1dup : InstrItinClass;
def IIC_VLD1dupu : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VLD2 : InstrItinClass;
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 03:03:04 +02:00
def IIC_VLD2x2 : InstrItinClass;
def IIC_VLD2u : InstrItinClass;
def IIC_VLD2x2u : InstrItinClass;
def IIC_VLD2ln : InstrItinClass;
def IIC_VLD2lnu : InstrItinClass;
Add support for NEON VLD2-dup instructions. llvm-svn: 120236
2010-11-28 07:51:26 +01:00
def IIC_VLD2dup : InstrItinClass;
def IIC_VLD2dupu : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VLD3 : InstrItinClass;
Finish vld3 and vld4. llvm-svn: 116140
2010-10-09 03:45:34 +02:00
def IIC_VLD3ln : InstrItinClass;
def IIC_VLD3u : InstrItinClass;
def IIC_VLD3lnu : InstrItinClass;
Add support for NEON VLD3-dup instructions. llvm-svn: 120312
2010-11-29 20:35:29 +01:00
def IIC_VLD3dup : InstrItinClass;
def IIC_VLD3dupu : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VLD4 : InstrItinClass;
Add VLD4 scheduling itineraries. llvm-svn: 116143
2010-10-09 06:07:58 +02:00
def IIC_VLD4ln : InstrItinClass;
def IIC_VLD4u : InstrItinClass;
def IIC_VLD4lnu : InstrItinClass;
Add support for NEON VLD3-dup instructions. The encoding for alignment in VLD4-dup instructions is still a work in progress. llvm-svn: 120356
2010-11-30 01:00:35 +01:00
def IIC_VLD4dup : InstrItinClass;
def IIC_VLD4dupu : InstrItinClass;
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 00:03:18 +02:00
def IIC_VST1 : InstrItinClass;
def IIC_VST1x2 : InstrItinClass;
def IIC_VST1x3 : InstrItinClass;
def IIC_VST1x4 : InstrItinClass;
def IIC_VST1u : InstrItinClass;
def IIC_VST1x2u : InstrItinClass;
def IIC_VST1x3u : InstrItinClass;
def IIC_VST1x4u : InstrItinClass;
Add NEON VST1-lane instructions. Partial fix for Radar 8599955. llvm-svn: 118069
2010-11-02 22:18:25 +01:00
def IIC_VST1ln : InstrItinClass;
def IIC_VST1lnu : InstrItinClass;
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 00:03:18 +02:00
def IIC_VST2 : InstrItinClass;
def IIC_VST2x2 : InstrItinClass;
def IIC_VST2u : InstrItinClass;
def IIC_VST2x2u : InstrItinClass;
def IIC_VST2ln : InstrItinClass;
def IIC_VST2lnu : InstrItinClass;
def IIC_VST3 : InstrItinClass;
def IIC_VST3u : InstrItinClass;
def IIC_VST3ln : InstrItinClass;
def IIC_VST3lnu : InstrItinClass;
def IIC_VST4 : InstrItinClass;
def IIC_VST4u : InstrItinClass;
def IIC_VST4ln : InstrItinClass;
def IIC_VST4lnu : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VUNAD : InstrItinClass;
def IIC_VUNAQ : InstrItinClass;
def IIC_VBIND : InstrItinClass;
def IIC_VBINQ : InstrItinClass;
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 01:41:41 +02:00
def IIC_VPBIND : InstrItinClass;
def IIC_VFMULD : InstrItinClass;
def IIC_VFMULQ : InstrItinClass;
NEON scheduling info fix. vmov reg, reg are single cycle instructions. llvm-svn: 115344
2010-10-01 22:50:58 +02:00
def IIC_VMOV : InstrItinClass;
Finish scheduling itineraries for NEON. llvm-svn: 82788
2009-09-25 20:38:29 +02:00
def IIC_VMOVImm : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VMOVD : InstrItinClass;
def IIC_VMOVQ : InstrItinClass;
Finish scheduling itineraries for NEON. llvm-svn: 82788
2009-09-25 20:38:29 +02:00
def IIC_VMOVIS : InstrItinClass;
def IIC_VMOVID : InstrItinClass;
def IIC_VMOVISL : InstrItinClass;
def IIC_VMOVSI : InstrItinClass;
def IIC_VMOVDI : InstrItinClass;
NEON scheduling info fix. vmov reg, reg are single cycle instructions. llvm-svn: 115344
2010-10-01 22:50:58 +02:00
def IIC_VMOVN : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VPERMD : InstrItinClass;
def IIC_VPERMQ : InstrItinClass;
def IIC_VPERMQ3 : InstrItinClass;
Finish scheduling itineraries for NEON. llvm-svn: 82788
2009-09-25 20:38:29 +02:00
def IIC_VMACD : InstrItinClass;
def IIC_VMACQ : InstrItinClass;
def IIC_VRECSD : InstrItinClass;
def IIC_VRECSQ : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VCNTiD : InstrItinClass;
def IIC_VCNTiQ : InstrItinClass;
def IIC_VUNAiD : InstrItinClass;
def IIC_VUNAiQ : InstrItinClass;
def IIC_VQUNAiD : InstrItinClass;
def IIC_VQUNAiQ : InstrItinClass;
def IIC_VBINiD : InstrItinClass;
def IIC_VBINiQ : InstrItinClass;
def IIC_VSUBiD : InstrItinClass;
def IIC_VSUBiQ : InstrItinClass;
def IIC_VBINi4D : InstrItinClass;
def IIC_VBINi4Q : InstrItinClass;
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. llvm-svn: 100652
2010-04-07 20:20:13 +02:00
def IIC_VSUBi4D : InstrItinClass;
def IIC_VSUBi4Q : InstrItinClass;
Fix itins for VABA llvm-svn: 100657
2010-04-07 20:20:42 +02:00
def IIC_VABAD : InstrItinClass;
def IIC_VABAQ : InstrItinClass;
Finish scheduling itineraries for NEON. llvm-svn: 82788
2009-09-25 20:38:29 +02:00
def IIC_VSHLiD : InstrItinClass;
def IIC_VSHLiQ : InstrItinClass;
def IIC_VSHLi4D : InstrItinClass;
def IIC_VSHLi4Q : InstrItinClass;
def IIC_VPALiD : InstrItinClass;
def IIC_VPALiQ : InstrItinClass;
Checkpoint NEON scheduling itineraries. llvm-svn: 82657
2009-09-23 23:38:08 +02:00
def IIC_VMULi16D : InstrItinClass;
def IIC_VMULi32D : InstrItinClass;
def IIC_VMULi16Q : InstrItinClass;
def IIC_VMULi32Q : InstrItinClass;
Finish scheduling itineraries for NEON. llvm-svn: 82788
2009-09-25 20:38:29 +02:00
def IIC_VMACi16D : InstrItinClass;
def IIC_VMACi32D : InstrItinClass;
def IIC_VMACi16Q : InstrItinClass;
def IIC_VMACi32Q : InstrItinClass;
def IIC_VEXTD : InstrItinClass;
def IIC_VEXTQ : InstrItinClass;
def IIC_VTB1 : InstrItinClass;
def IIC_VTB2 : InstrItinClass;
def IIC_VTB3 : InstrItinClass;
def IIC_VTB4 : InstrItinClass;
def IIC_VTBX1 : InstrItinClass;
def IIC_VTBX2 : InstrItinClass;
def IIC_VTBX3 : InstrItinClass;
def IIC_VTBX4 : InstrItinClass;
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. llvm-svn: 73747
2009-06-19 03:51:50 +02:00
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
Add support to model pipeline bypass / forwarding. llvm-svn: 115005
2010-09-29 01:50:49 +02:00
def GenericItineraries : ProcessorItineraries<[], [], []>;
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. llvm-svn: 73747
2009-06-19 03:51:50 +02:00
include "ARMScheduleV6.td"
Split A8/A9 itins - they already were too big. llvm-svn: 100672
2010-04-07 20:22:11 +02:00
include "ARMScheduleA8.td"
include "ARMScheduleA9.td"
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