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llvm-mirror/lib/Target/AMDGPU/GCNProcessors.td

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AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
//===-- GCNProcessors.td - GCN Processor definitions ----------------------===//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 09:50:56 +01:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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//
//===----------------------------------------------------------------------===//
// The code produced for "generic" is only useful for tests and cannot
// reasonably be expected to execute on any particular target.
def : ProcessorModel<"generic", NoSchedModel,
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[FeatureWavefrontSize64]
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>;
AMDGPU: Partially fix default device for HSA There are a few different issues, mostly stemming from using generation based checks for anything instead of subtarget features. Stop adding flat-address-space as a feature for HSA, as it should only be a device property. This was incorrectly allowing flat instructions to select for SI. Increase the default generation for HSA to avoid the encoding error when emitting objects. This has some other side effects from various checks which probably should be separate subtarget features (in the cost model and for dealing with the DS offset folding issue). Partial fix for bug 41070. It should probably be an error to try using amdhsa without flat support. llvm-svn: 356347
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def : ProcessorModel<"generic-hsa", NoSchedModel,
[FeatureWavefrontSize64, FeatureFlatAddressSpace]
>;
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
//===------------------------------------------------------------===//
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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// GCN GFX6 (Southern Islands (SI)).
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
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//===------------------------------------------------------------===//
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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def : ProcessorModel<"gfx600", SIFullSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion6_0_0.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
def : ProcessorModel<"tahiti", SIFullSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion6_0_0.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
def : ProcessorModel<"gfx601", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion6_0_1.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
[AMDGPU] Add gfx602, gfx705, gfx805 targets At AMD, in an internal audit of our code, we found some corner cases where we were not quite differentiating targets enough for some old hardware. This commit is part of fixing that by adding three new targets: * The "Oland" and "Hainan" variants of gfx601 are now split out into gfx602. LLPC (in the GPUOpen driver) and other front-ends could use that to avoid using the shaderZExport workaround on gfx602. * One variant of gfx703 is now split out into gfx705. LLPC and other front-ends could use that to avoid using the shaderSpiCsRegAllocFragmentation workaround on gfx705. * The "TongaPro" variant of gfx802 is now split out into gfx805. TongaPro has a faster 64-bit shift than its former friends in gfx802, and a subtarget feature could be set up for that to take advantage of it. This commit does not make that change; it just adds the target. V2: Add clang changes. Put TargetParser list in order. V3: AMDGCNGPUs table in TargetParser.cpp needs to be in GPUKind order, so fix the GPUKind order. Differential Revision: https://reviews.llvm.org/D88916 Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
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def : ProcessorModel<"pitcairn", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion6_0_1.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
[AMDGPU] Add gfx602, gfx705, gfx805 targets At AMD, in an internal audit of our code, we found some corner cases where we were not quite differentiating targets enough for some old hardware. This commit is part of fixing that by adding three new targets: * The "Oland" and "Hainan" variants of gfx601 are now split out into gfx602. LLPC (in the GPUOpen driver) and other front-ends could use that to avoid using the shaderZExport workaround on gfx602. * One variant of gfx703 is now split out into gfx705. LLPC and other front-ends could use that to avoid using the shaderSpiCsRegAllocFragmentation workaround on gfx705. * The "TongaPro" variant of gfx802 is now split out into gfx805. TongaPro has a faster 64-bit shift than its former friends in gfx802, and a subtarget feature could be set up for that to take advantage of it. This commit does not make that change; it just adds the target. V2: Add clang changes. Put TargetParser list in order. V3: AMDGCNGPUs table in TargetParser.cpp needs to be in GPUKind order, so fix the GPUKind order. Differential Revision: https://reviews.llvm.org/D88916 Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
2020-10-06 19:23:59 +02:00
def : ProcessorModel<"verde", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion6_0_1.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
[AMDGPU] Add gfx602, gfx705, gfx805 targets At AMD, in an internal audit of our code, we found some corner cases where we were not quite differentiating targets enough for some old hardware. This commit is part of fixing that by adding three new targets: * The "Oland" and "Hainan" variants of gfx601 are now split out into gfx602. LLPC (in the GPUOpen driver) and other front-ends could use that to avoid using the shaderZExport workaround on gfx602. * One variant of gfx703 is now split out into gfx705. LLPC and other front-ends could use that to avoid using the shaderSpiCsRegAllocFragmentation workaround on gfx705. * The "TongaPro" variant of gfx802 is now split out into gfx805. TongaPro has a faster 64-bit shift than its former friends in gfx802, and a subtarget feature could be set up for that to take advantage of it. This commit does not make that change; it just adds the target. V2: Add clang changes. Put TargetParser list in order. V3: AMDGCNGPUs table in TargetParser.cpp needs to be in GPUKind order, so fix the GPUKind order. Differential Revision: https://reviews.llvm.org/D88916 Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
2020-10-06 19:23:59 +02:00
def : ProcessorModel<"gfx602", SIQuarterSpeedModel,
FeatureISAVersion6_0_2.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
[AMDGPU] Add gfx602, gfx705, gfx805 targets At AMD, in an internal audit of our code, we found some corner cases where we were not quite differentiating targets enough for some old hardware. This commit is part of fixing that by adding three new targets: * The "Oland" and "Hainan" variants of gfx601 are now split out into gfx602. LLPC (in the GPUOpen driver) and other front-ends could use that to avoid using the shaderZExport workaround on gfx602. * One variant of gfx703 is now split out into gfx705. LLPC and other front-ends could use that to avoid using the shaderSpiCsRegAllocFragmentation workaround on gfx705. * The "TongaPro" variant of gfx802 is now split out into gfx805. TongaPro has a faster 64-bit shift than its former friends in gfx802, and a subtarget feature could be set up for that to take advantage of it. This commit does not make that change; it just adds the target. V2: Add clang changes. Put TargetParser list in order. V3: AMDGCNGPUs table in TargetParser.cpp needs to be in GPUKind order, so fix the GPUKind order. Differential Revision: https://reviews.llvm.org/D88916 Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
2020-10-06 19:23:59 +02:00
def : ProcessorModel<"hainan", SIQuarterSpeedModel,
FeatureISAVersion6_0_2.Features
>;
def : ProcessorModel<"oland", SIQuarterSpeedModel,
FeatureISAVersion6_0_2.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
//===------------------------------------------------------------===//
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
// GCN GFX7 (Sea Islands (CI)).
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
//===------------------------------------------------------------===//
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
def : ProcessorModel<"gfx700", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_0.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"kaveri", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_0.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"gfx701", SIFullSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_1.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"hawaii", SIFullSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_1.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"gfx702", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_2.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
def : ProcessorModel<"gfx703", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_3.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
def : ProcessorModel<"kabini", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_3.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
def : ProcessorModel<"mullins", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_3.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage - Add gfx704 - Change bonaire to gfx704 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40046 llvm-svn: 320194
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def : ProcessorModel<"gfx704", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_4.Features
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage - Add gfx704 - Change bonaire to gfx704 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40046 llvm-svn: 320194
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>;
def : ProcessorModel<"bonaire", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion7_0_4.Features
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage - Add gfx704 - Change bonaire to gfx704 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40046 llvm-svn: 320194
2017-12-08 21:52:28 +01:00
>;
[AMDGPU] Add gfx602, gfx705, gfx805 targets At AMD, in an internal audit of our code, we found some corner cases where we were not quite differentiating targets enough for some old hardware. This commit is part of fixing that by adding three new targets: * The "Oland" and "Hainan" variants of gfx601 are now split out into gfx602. LLPC (in the GPUOpen driver) and other front-ends could use that to avoid using the shaderZExport workaround on gfx602. * One variant of gfx703 is now split out into gfx705. LLPC and other front-ends could use that to avoid using the shaderSpiCsRegAllocFragmentation workaround on gfx705. * The "TongaPro" variant of gfx802 is now split out into gfx805. TongaPro has a faster 64-bit shift than its former friends in gfx802, and a subtarget feature could be set up for that to take advantage of it. This commit does not make that change; it just adds the target. V2: Add clang changes. Put TargetParser list in order. V3: AMDGCNGPUs table in TargetParser.cpp needs to be in GPUKind order, so fix the GPUKind order. Differential Revision: https://reviews.llvm.org/D88916 Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
2020-10-06 19:23:59 +02:00
def : ProcessorModel<"gfx705", SIQuarterSpeedModel,
FeatureISAVersion7_0_5.Features
>;
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
//===------------------------------------------------------------===//
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
// GCN GFX8 (Volcanic Islands (VI)).
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
//===------------------------------------------------------------===//
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
def : ProcessorModel<"gfx801", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_1.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
def : ProcessorModel<"carrizo", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_1.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
def : ProcessorModel<"gfx802", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_2.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
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>;
AMDGPU: Bring processors and features in sync with the spec - Remove gfx800 - Make iceland gfx802 - Add xnack to gfx902 Differential Revision: https://reviews.llvm.org/D43355 llvm-svn: 325393
2018-02-16 22:26:25 +01:00
def : ProcessorModel<"iceland", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_2.Features
AMDGPU: Bring processors and features in sync with the spec - Remove gfx800 - Make iceland gfx802 - Add xnack to gfx902 Differential Revision: https://reviews.llvm.org/D43355 llvm-svn: 325393
2018-02-16 22:26:25 +01:00
>;
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
def : ProcessorModel<"tonga", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_2.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"gfx803", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_3.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"fiji", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_3.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"polaris10", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_3.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"polaris11", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_0_3.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
[AMDGPU] Add gfx602, gfx705, gfx805 targets At AMD, in an internal audit of our code, we found some corner cases where we were not quite differentiating targets enough for some old hardware. This commit is part of fixing that by adding three new targets: * The "Oland" and "Hainan" variants of gfx601 are now split out into gfx602. LLPC (in the GPUOpen driver) and other front-ends could use that to avoid using the shaderZExport workaround on gfx602. * One variant of gfx703 is now split out into gfx705. LLPC and other front-ends could use that to avoid using the shaderSpiCsRegAllocFragmentation workaround on gfx705. * The "TongaPro" variant of gfx802 is now split out into gfx805. TongaPro has a faster 64-bit shift than its former friends in gfx802, and a subtarget feature could be set up for that to take advantage of it. This commit does not make that change; it just adds the target. V2: Add clang changes. Put TargetParser list in order. V3: AMDGCNGPUs table in TargetParser.cpp needs to be in GPUKind order, so fix the GPUKind order. Differential Revision: https://reviews.llvm.org/D88916 Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
2020-10-06 19:23:59 +02:00
def : ProcessorModel<"gfx805", SIQuarterSpeedModel,
FeatureISAVersion8_0_5.Features
>;
def : ProcessorModel<"tongapro", SIQuarterSpeedModel,
FeatureISAVersion8_0_5.Features
>;
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
def : ProcessorModel<"gfx810", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_1_0.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"stoney", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion8_1_0.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
//===------------------------------------------------------------===//
// GCN GFX9.
//===------------------------------------------------------------===//
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
def : ProcessorModel<"gfx900", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion9_0_0.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
def : ProcessorModel<"gfx902", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion9_0_2.Features
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-10 21:01:58 +01:00
>;
AMDGPU: Add Vega12 and Vega20 Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
2018-04-30 21:08:16 +02:00
def : ProcessorModel<"gfx904", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion9_0_4.Features
AMDGPU: Add Vega12 and Vega20 Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
2018-04-30 21:08:16 +02:00
>;
def : ProcessorModel<"gfx906", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion9_0_6.Features
AMDGPU: Add Vega12 and Vega20 Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
2018-04-30 21:08:16 +02:00
>;
[AMDGPU] Defined gfx909 Raven Ridge 2 Differential Revision: https://reviews.llvm.org/D53418 Change-Id: Ie3d054f2e956c2768988c0f4c0ffd29a47294eef llvm-svn: 345120
2018-10-24 10:14:07 +02:00
[AMDGPU] gfx908 target Differential Revision: https://reviews.llvm.org/D64429 llvm-svn: 365525
2019-07-09 20:10:06 +02:00
def : ProcessorModel<"gfx908", SIQuarterSpeedModel,
FeatureISAVersion9_0_8.Features
>;
[AMDGPU] Defined gfx909 Raven Ridge 2 Differential Revision: https://reviews.llvm.org/D53418 Change-Id: Ie3d054f2e956c2768988c0f4c0ffd29a47294eef llvm-svn: 345120
2018-10-24 10:14:07 +02:00
def : ProcessorModel<"gfx909", SIQuarterSpeedModel,
AMDGPU: Eliminate GPU specific SubtargetFeatures Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
2019-02-08 20:59:32 +01:00
FeatureISAVersion9_0_9.Features
[AMDGPU] Defined gfx909 Raven Ridge 2 Differential Revision: https://reviews.llvm.org/D53418 Change-Id: Ie3d054f2e956c2768988c0f4c0ffd29a47294eef llvm-svn: 345120
2018-10-24 10:14:07 +02:00
>;
[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906
2021-02-17 22:37:46 +01:00
def : ProcessorModel<"gfx90a", SIDPFullSpeedModel,
FeatureISAVersion9_0_A.Features
>;
[AMDGPU] Add gfx90c target This differentiates the Ryzen 4000/4300/4500/4700 series APUs that were previously included in gfx909. Differential Revision: https://reviews.llvm.org/D90419 Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
2020-10-06 19:23:59 +02:00
def : ProcessorModel<"gfx90c", SIQuarterSpeedModel,
FeatureISAVersion9_0_C.Features
>;
[AMDGPU] Add gfx1010 target definitions Differential Revision: https://reviews.llvm.org/D61041 llvm-svn: 359113
2019-04-24 19:03:15 +02:00
//===----------------------------------------------------------------------===//
// GCN GFX10.
//===----------------------------------------------------------------------===//
def : ProcessorModel<"gfx1010", GFX10SpeedModel,
FeatureISAVersion10_1_0.Features
>;
[AMDGPU] gfx1011/gfx1012 targets Differential Revision: https://reviews.llvm.org/D63307 llvm-svn: 363344
2019-06-14 02:33:31 +02:00
def : ProcessorModel<"gfx1011", GFX10SpeedModel,
FeatureISAVersion10_1_1.Features
>;
def : ProcessorModel<"gfx1012", GFX10SpeedModel,
FeatureISAVersion10_1_2.Features
>;
[AMDGPU] Add gfx1030 target Differential Revision: https://reviews.llvm.org/D81886
2020-06-15 23:10:39 +02:00
Reland "[AMDGPU] Add gfx1013 target" This reverts commit 211e584fa2a4c032e4d573e7cdbffd622aad0a8f. Fixed a use-after-free error that caused the sanitizers to fail.
2021-06-08 22:54:42 +02:00
def : ProcessorModel<"gfx1013", GFX10SpeedModel,
FeatureISAVersion10_1_3.Features
>;
[AMDGPU] Add gfx1030 target Differential Revision: https://reviews.llvm.org/D81886
2020-06-15 23:10:39 +02:00
def : ProcessorModel<"gfx1030", GFX10SpeedModel,
FeatureISAVersion10_3_0.Features
>;
[AMDGPU] gfx1031 target Differential Revision: https://reviews.llvm.org/D85337
2020-08-05 21:00:52 +02:00
def : ProcessorModel<"gfx1031", GFX10SpeedModel,
FeatureISAVersion10_3_0.Features
>;
[AMDGPU] gfx1032 target Differential Revision: https://reviews.llvm.org/D89487
2020-10-15 19:48:46 +02:00
def : ProcessorModel<"gfx1032", GFX10SpeedModel,
FeatureISAVersion10_3_0.Features
>;
[AMDGPU] Add gfx1033 target Differential Revision: https://reviews.llvm.org/D90447 Change-Id: If2650fc7f31bbdd49c76e74a9ca8e3734d769761
2020-10-30 09:21:12 +01:00
def : ProcessorModel<"gfx1033", GFX10SpeedModel,
FeatureISAVersion10_3_0.Features
>;
[AMDGPU] Add gfx1034 target Differential Revision: https://reviews.llvm.org/D102306
2021-05-13 20:21:40 +02:00
def : ProcessorModel<"gfx1034", GFX10SpeedModel,
FeatureISAVersion10_3_0.Features
>;
[AMDGPU] Add gfx1035 target Differential Revision: https://reviews.llvm.org/D104804
2021-06-24 20:32:41 +02:00
def : ProcessorModel<"gfx1035", GFX10SpeedModel,
FeatureISAVersion10_3_0.Features
>;
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