RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 16:33:37 +01:00
Code Issues Projects Releases Wiki Activity
add3022a37
llvm-mirror/test/MC/Disassembler/ARM/thumb-tests.txt

304 lines
4.5 KiB
Plaintext
Raw Normal View History

Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. llvm-svn: 139250
2011-09-07 21:42:28 +02:00
# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mattr +t2xtpk,+mp | FileCheck %s
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: add r5, sp, #68
0x11 0xad
# CHECK: adcs r0, r0, #1
0x50 0xf1 0x01 0x00
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset. Remove the offending logic and update the test cases. llvm-svn: 127843
2011-03-18 01:38:03 +01:00
# CHECK: b #30
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
0x0f 0xe0
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
2011-04-13 23:35:49 +02:00
# CHECK: bgt.w #-16
0x3f 0xf7 0xf8 0xaf
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. llvm-svn: 101817
2010-04-19 23:19:52 +02:00
Thumb2 BFC was insufficiently encoded. rdar://problem/9292717 llvm-svn: 129619
2011-04-16 00:52:15 +02:00
# CHECK: bfc r0, #10, #10
0x6f 0xf3 0x93 0x20
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: bfi r2, r10, #0, #1
0x6a 0xf3 0x00 0x02
# CHECK: cbnz r7, #20
0x57 0xb9
# CHECK: cmp r3, r4
0xa3 0x42
# CHECK: cmn.w r0, #31
0x10 0xf1 0x1f 0x0f
Thumb assembly parsing and encoding for LDM instruction. Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
2011-08-18 23:50:53 +02:00
# CHECK: ldm r0!, {r1}
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
0x02 0xc8
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
2011-04-22 21:12:43 +02:00
# CHECK: ldr r5, #432
0x6c 0x4d
It used to be that t_addrmode_s4 was used for both: o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. llvm-svn: 127833
2011-03-17 23:04:05 +01:00
# CHECK: str r0, [r3]
0x18 0x60
# CHECK: str r0, [r3, #4]
0x58 0x60
# CHECK: str r2, [r5, r3]
0xea 0x50
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. llvm-svn: 140283
2011-09-22 01:44:46 +02:00
# CHECK: ldrb.w r8, [pc, #-24]
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT llvm-svn: 101915
2010-04-20 19:28:50 +02:00
0x1f 0xf8 0x18 0x80
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: ldrd r0, r1, [r7, #64]!
0xf7 0xe9 0x10 0x01
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. llvm-svn: 128913
2011-04-05 21:42:11 +02:00
# CHECK: lsls.w r0, r5, #1
0x5f 0xea 0x45 0x00
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: mov r11, r7
0xbb 0x46
# CHECK: pkhtb r2, r4, r6, asr #16
0xc4 0xea 0x26 0x42
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. llvm-svn: 111251
2010-08-17 19:23:19 +02:00
# CHECK-NOT: pkhbt r2, r4, r6, lsl #0
# CHECK: pkhbt r2, r4, r6
0xc4 0xea 0x06 0x02
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 32-bit wide version by adding the .w suffix. llvm-svn: 120838
2010-12-03 21:33:01 +01:00
# CHECK: pop.w {r2, r4, r6, r8, r10, r12}
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
0xbd 0xe8 0x54 0x15
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 32-bit wide version by adding the .w suffix. llvm-svn: 120838
2010-12-03 21:33:01 +01:00
# CHECK: push.w {r2, r4, r6, r8, r10, r12}
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
0x2d 0xe9 0x54 0x15
# CHECK: rsbs r0, r0, #0
0x40 0x42
Add a Thumb2 t2RSBrr instruction for disassembly only. This fixes another part of PR7792. llvm-svn: 111057
2010-08-14 01:24:25 +02:00
# CHECK-NOT: rsb r0, r2, r0, lsl #0
# CHECK: rsb r0, r2, r0
0xc2 0xeb 0x00 0x00
Move the Thumb2 SSAT and USAT optional shift operator out of the instruction opcode. This fixes part of PR7792. llvm-svn: 111047
2010-08-13 23:48:10 +02:00
# CHECK-NOT: ssat r0, #17, r12, lsl #0
# CHECK: ssat r0, #17, r12
0x0c 0xf3 0x10 0x00
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. llvm-svn: 120589
2010-12-01 20:18:46 +01:00
# CHECK: strd r0, r1, [r7, #64]
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
0xc7 0xe9 0x10 0x01
# CHECK: sub sp, #60
0x8f 0xb0
# CHECK: subw r0, pc, #1
0xaf 0xf2 0x01 0x00
When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12, as their generic counterparts t2ADDri12/t2SUBri12 should suffice. llvm-svn: 101929
2010-04-20 20:45:24 +02:00
# CHECK: subw r0, sp, #835
0xad 0xf2 0x43 0x30
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: uqadd16 r3, r4, r5
0x94 0xfa 0x55 0xf3
# CHECK: usada8 r5, r4, r3, r2
0x74 0xfb 0x03 0x25
# CHECK: uxtab16 r1, r2, r3, ror #8
0x32 0xfa 0x93 0xf1
# IT block begin
# CHECK: ittte eq
0x03 0xbf
# CHECK: moveq r3, #3
0x03 0x23
# CHECK: asreq r1, r0, #5
0x41 0x11
# CHECK: lsleq r1, r0, #28
0x01 0x07
Thumb assembly parsing and encoding for LDM instruction. Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
2011-08-18 23:50:53 +02:00
# CHECK: stmne r0!, {r1, r2, r3}
Thumb instructions which have reglist operands at the end and predicate operands before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. llvm-svn: 101974
2010-04-21 03:01:19 +02:00
0x0e 0xc0
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# IT block end
Thumb instructions which have reglist operands at the end and predicate operands before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. llvm-svn: 101974
2010-04-21 03:01:19 +02:00
# CHECK: rsbs r1, r2, #0
0x51 0x42
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 14:09:44 +01:00
# CHECK: cpsid.w f
0xaf 0xf3 0x20 0x86
# CHECK: cps #15
0xaf 0xf3 0x0f 0x81
# CHECK: cpsie.w if, #10
0xaf 0xf3 0x6a 0x85
# CHECK: cpsie aif
0x67 0xb6
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
Tweak ARM assembly parsing and printing of MSR instruction. The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
2011-07-20 00:45:10 +02:00
# CHECK: msr CPSR_fc, r0
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
0x80 0xf3 0x00 0x89
Fix the arm's disassembler for blx that was building an MCInst without the needed two predicate operands before the imm operand. llvm-svn: 126662
2011-02-28 19:46:31 +01:00
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset. Remove the offending logic and update the test cases. llvm-svn: 127843
2011-03-18 01:38:03 +01:00
# CHECK: blx #-4
Fix the arm's disassembler for blx that was building an MCInst without the needed two predicate operands before the imm operand. llvm-svn: 126662
2011-02-28 19:46:31 +01:00
0xff 0xf7 0xfe 0xef
A8.6.399 VSTM: VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm() to reflect the change. Also add a test case. llvm-svn: 128103
2011-03-22 21:00:10 +01:00
# CHECK: vpush {d8, d9, d10}
0x2d 0xed 0x06 0x8b
Add disassembly test cases for: A8.6.292 VCMPE llvm-svn: 128120
2011-03-23 00:08:56 +01:00
# CHECK: vcmpe.f64 d8, #0
0xb5 0xee 0xc0 0x8b
T2 Load/Store Multiple: These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. llvm-svn: 128240
2011-03-24 22:36:56 +01:00
Update test for 139243 llvm-svn: 139244
2011-09-07 20:40:06 +02:00
# CHECK: stmdb sp, {r0, r2, r3, r8, r11, lr}
T2 Load/Store Multiple: These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. llvm-svn: 128240
2011-03-24 22:36:56 +01:00
0x0d 0xe9 0x0d 0x49
The ARM disassembler was confused with the 16-bit tSTMIA instruction. According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. llvm-svn: 128246
2011-03-25 00:21:14 +01:00
Thumb assembly parsing and encoding for LDM instruction. Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
2011-08-18 23:50:53 +02:00
# CHECK: stm r5!, {r0, r1, r2, r3, r4}
The ARM disassembler was confused with the 16-bit tSTMIA instruction. According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. llvm-svn: 128246
2011-03-25 00:21:14 +01:00
0x1f 0xc5
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. llvm-svn: 128247
2011-03-25 00:42:31 +01:00
Thumb assembly parsing and encoding for LDM instruction. Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
2011-08-18 23:50:53 +02:00
# CHECK: ldm r5, {r0, r1, r2, r3, r4, r5}
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. llvm-svn: 128247
2011-03-25 00:42:31 +01:00
0x3f 0xcd
Thumb assembly parsing and encoding for LDM instruction. Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
2011-08-18 23:50:53 +02:00
# CHECK: ldm r5!, {r0, r1, r2, r3, r4}
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. llvm-svn: 128247
2011-03-25 00:42:31 +01:00
0x1f 0xcd
delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. llvm-svn: 128249
2011-03-25 01:17:42 +01:00
# CHECK: addw r0, pc, #1050
0x0f 0xf2 0x1a 0x40
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. llvm-svn: 128252
2011-03-25 02:09:48 +01:00
# CHECK: ldrd r3, r8, [r11, #-60]
0x5b 0xe9 0x0f 0x38
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to t2LDREX/t2STREX instructions. Add two test cases. llvm-svn: 128293
2011-03-25 19:29:49 +01:00
# CHECK: ldrex r8, [r2]
0x52 0xe8 0x00 0x8f
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. llvm-svn: 129531
2011-04-14 21:13:28 +02:00
# CHECK: ldrexd r8, r9, [r2]
0xd2 0xe8 0x7f 0x89
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to t2LDREX/t2STREX instructions. Add two test cases. llvm-svn: 128293
2011-03-25 19:29:49 +01:00
# CHECK: strexd r1, r7, r8, [r2]
0xc2 0xe8 0x71 0x78
A8.6.226 TBB, TBH: Add two test cases. llvm-svn: 128295
2011-03-25 19:40:21 +01:00
# CHECK: tbh [r5, r4, lsl #1]
0xd5 0xe8 0x14 0xf0
# CHECK: tbb [r5, r4]
0xd5 0xe8 0x04 0xf0
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. rdar://problem/9182892 llvm-svn: 128299
2011-03-25 20:35:37 +01:00
# CHECK: ldr.w r4, [sp, r4, lsl #3]
0x5d 0xf8 0x34 0x40
# CHECK: ldr.w r5, [r6, #30]
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
2011-04-12 20:48:00 +02:00
0xd6 0xf8 0x1e 0x50
# CHECK: ldrh.w r5, [r6, #30]
0xb6 0xf8 0x1e 0x50
# CHECK: ldrt r5, [r6, #30]
0x56 0xf8 0x1e 0x5e
# CHECK: ldr r5, [r6, #-30]
0x56 0xf8 0x1e 0x5c
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. Also add some test cases. rdar://problem/9189829 llvm-svn: 128304
2011-03-25 23:19:07 +01:00
# CHECK: sel r7, r3, r5
0xa3 0xfa 0x85 0xf7
# CHECK: lsl.w r7, r3, r5
0x03 0xfa 0x05 0xf7
# CHECK: adds.w r7, r3, r5
0x13 0xeb 0x05 0x07
Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul(). llvm-svn: 128305
2011-03-25 23:43:28 +01:00
# CHECK: smlabt r4, r3, r2, r1
0x13 0xfb 0x12 0x14
# CHECK: smmulr r7, r8, r9
0x58 0xfb 0x19 0xf7
Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt. llvm-svn: 128306
2011-03-26 00:02:58 +01:00
# CHECK: umull r1, r2, r3, r4
0xa3 0xfb 0x04 0x12
Fixed the t2PLD and friends disassembly and add two test cases. llvm-svn: 128322
2011-03-26 02:32:48 +01:00
# CHECK: pld [r5, r0, lsl #1]
0x15 0xf8 0x10 0xf0
# CHECK: pld [pc, #-16]
0x1f 0xf8 0x10 0xf0
Add a test case for thumb stc2 instruction. llvm-svn: 128517
2011-03-30 03:02:06 +02:00
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
2011-04-12 20:48:00 +02:00
# CHECK: pld [r5, #30]
0x95 0xf8 0x1e 0xf0
Create Thumb2 versions of STC/LDC, and reenable the relevant tests. llvm-svn: 139256
2011-09-07 23:10:42 +02:00
# CHECK: stc p12, cr15, [r9], {137}
0x89 0xfc 0x89 0xfc
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
2011-04-06 22:49:02 +02:00
# CHECK: vmov r1, r0, d11
0x50 0xec 0x1b 0x1b
Sanity check the option operand for DMB/DSB. PR9648 rdar://problem/9257634 llvm-svn: 129146
2011-04-08 21:18:07 +02:00
# CHECK: dsb nsh
0xbf 0xf3 0x47 0x8f
# CHECK: isb
0xbf 0xf3 0x6f 0x8f
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. rdar://problem/9266265 llvm-svn: 129298
2011-04-11 23:14:35 +02:00
# CHECK: asrs r1, r0, #32
0x1 0x10
# CHECK: lsr.w r10, r0, #32
0x4f 0xea 0x10 0x0a
Thumb disassembler was erroneously rejecting "blx sp" instruction. rdar://problem/9267838 llvm-svn: 129320
2011-04-12 01:33:30 +02:00
# CHECK: blx sp
0xe8 0x47
# CHECK: bx lr
0x70 0x47
# CHECK: bx pc
0x78 0x47
Add one test case (svc). llvm-svn: 129327
2011-04-12 02:21:48 +02:00
# CHECK: svc #230
0xe6 0xdf
The Thumb2 RFE instructions need to have their second halfword fully specified. In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
2011-04-12 23:41:51 +02:00
# CHECK: rfedb lr
0x1e 0xe8 0x00 0xc0
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. rdar://problem/9276427 llvm-svn: 129456
2011-04-13 19:51:02 +02:00
# CHECK: mov.w r3, #4294967295
0x4f 0xf0 0xff 0x33
Thumb disassembler did not handle tBRIND (indirect branch) properly. rdar://problem/9280370 llvm-svn: 129480
2011-04-13 23:59:01 +02:00
# CHECK: mov pc, sp
0xef 0x46
Add tests for A8.6.110 NOP. llvm-svn: 130345
2011-04-28 01:29:21 +02:00
# CHECK: nop
0x00 0xbf
# CHECK: nop.w
0xaf 0xf3 0x00 0x80
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. llvm-svn: 131565
2011-05-18 22:32:41 +02:00
# CHECK: bne #24
0x0c 0xd1
Add initial support for decoding NEON instructions in Thumb2 mode. llvm-svn: 137236
2011-08-10 21:01:10 +02:00
# CHECK: vadd.f32 q0, q1, q2
0x02 0xef 0x44 0x0d
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. llvm-svn: 137636
2011-08-15 21:00:06 +02:00
# CHECK: ldrsb r1, [r0, r0]
0x01 0x56
Add a test for Thumb1 LDRSH decoding. llvm-svn: 137645
2011-08-15 22:15:43 +02:00
# CHECK: ldrsh r1, [r0, r0]
0x01 0x5E
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. llvm-svn: 138292
2011-08-23 01:10:16 +02:00
# CHECK: and.w r5, r1, r10, ror #7
0x1 0xea 0xfa 0x95
Match operand naming to allow correct decoding of t2LDRSH_POST. llvm-svn: 138298
2011-08-23 01:22:05 +02:00
# CHECK: ldrsh r6, [sp], #81
0x3d 0xf9 0x51 0x6b
Correct operand naming of t2USAT16 to allow proper decoding. llvm-svn: 138300
2011-08-23 01:27:47 +02:00
# CHECK: usat16 r4, #10, r1
Fix incorrect disassembly test. llvm-svn: 140423
2011-09-24 00:05:54 +02:00
0xa1 0xf3 0x0a 0x04
t2SMLAD is a four-register instruction, not a three-register one. llvm-svn: 138301
2011-08-23 01:31:45 +02:00
# CHECK: smlad r5, r12, r8, r11
0x2c 0xfb 0x8 0xb5
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing. llvm-svn: 138337
2011-08-23 19:37:32 +02:00
# CHECK: teq.w r0, r11
0x90 0xea 0xb 0x8f
# CHECK: uxtb16 r9, r12, ror #16
0x3f 0xfa 0xec 0xf9
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. llvm-svn: 138341
2011-08-23 19:51:38 +02:00
# CHECK: pldw [r11, r12, lsl #2]
0x3b 0xf8 0x2c 0xf0
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
2011-09-28 16:21:38 +02:00
# CHECK: msr CPSR_fc, r0
0x80 0xf3 0x00 0x89
# CHECK: mrs r0, apsr
0xef 0xf3 0x00 0x80
Reference in New Issue Copy Permalink