2018-12-17 18:38:11 +01:00
|
|
|
..
|
|
|
|
|
**************************************************
|
|
|
|
|
* *
|
|
|
|
|
* Automatically generated file, do not edit! *
|
|
|
|
|
* *
|
|
|
|
|
**************************************************
|
|
|
|
|
|
2021-07-23 11:51:37 +02:00
|
|
|
.. _amdgpu_synid_gfx9_vdst_6:
|
2018-12-17 18:38:11 +01:00
|
|
|
|
|
|
|
|
vdst
|
2021-07-23 11:51:37 +02:00
|
|
|
====
|
2018-12-17 18:38:11 +01:00
|
|
|
|
|
|
|
|
Image data to load by an *image_gather4* instruction.
|
|
|
|
|
|
|
|
|
|
*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
|
|
|
|
|
|
|
|
|
|
:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
|
|
|
|
|
|
|
|
|
|
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
|
|
|
|
|
* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
|
|
|
|
|
|
|
|
|
|
*Operands:* :ref:`v<amdgpu_synid_v>`
|
