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[AMDGPU][MC][GFX9][NFC][DOC] Updated AMD GPU assembler syntax description.

Browse Source 
Fixed bugs 48639, 49447, 49448, 49449.
This commit is contained in:
Dmitry Preobrazhensky 2021-07-23 12:51:37 +03:00
parent c98a4cb73f
commit 1d7a6567dd
119 changed files with 2439 additions and 2387 deletions
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3896
docs/AMDGPU/AMDGPUAsmGFX9.rst
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4
docs/AMDGPU/gfx9_attr.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_attr:
.. _amdgpu_synid_gfx9_attr:
attr
===========================
====
Interpolation attribute and channel:

4
docs/AMDGPU/gfx9_ret.rst → docs/AMDGPU/gfx9_dst.rst
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@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_ret:
.. _amdgpu_synid_gfx9_dst:
dst
===========================
===
This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.

4
docs/AMDGPU/gfx9_hwreg.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_hwreg:
.. _amdgpu_synid_gfx9_hwreg:
hwreg
===========================
=====
Bits of a hardware register being accessed.

4
docs/AMDGPU/gfx9_imask.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_imask:
.. _amdgpu_synid_gfx9_imask:
imask
===========================
=====
This operand is a mask which controls indexing mode for operands of subsequent instructions.
Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.

4
docs/AMDGPU/gfx9_simm16.rst → docs/AMDGPU/gfx9_imm16.rst
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@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_simm16:
.. _amdgpu_synid_gfx9_imm16:
imm16
===========================
=====
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

4
docs/AMDGPU/gfx9_uimm16.rst → docs/AMDGPU/gfx9_imm16_1.rst
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@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_uimm16:
.. _amdgpu_synid_gfx9_imm16_1:
imm16
===========================
=====
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.

4
docs/AMDGPU/gfx9_bimm16.rst → docs/AMDGPU/gfx9_imm16_2.rst
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@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_bimm16:
.. _amdgpu_synid_gfx9_imm16_2:
imm16
===========================
=====
A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

4
docs/AMDGPU/gfx9_label.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_label:
.. _amdgpu_synid_gfx9_label:
label
===========================
=====
A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.

4
docs/AMDGPU/gfx9_mod_sdwa_sext.rst → docs/AMDGPU/gfx9_m.rst
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@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_mod_sdwa_sext:
.. _amdgpu_synid_gfx9_m:
m
===========================
=
This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.

4
docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst → docs/AMDGPU/gfx9_m_1.rst
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@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_mod_vop3_abs_neg:
.. _amdgpu_synid_gfx9_m_1:
m
===========================
=
This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.

13
docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
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@ -1,13 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_mod_dpp_sdwa_abs_neg:
m
===========================
This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.

5
docs/AMDGPU/gfx9_msg.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_msg:
.. _amdgpu_synid_gfx9_msg:
msg
===========================
===
A 16-bit message code. The bits of this operand have the following meaning:
@ -94,4 +94,3 @@ Examples:
stream = 1
s_sendmsg sendmsg(msg, op, stream)
s_sendmsg sendmsg(2, GS_OP_CUT)

4
docs/AMDGPU/gfx9_opt.rst
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@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_opt:
.. _amdgpu_synid_gfx9_opt:
opt
===========================
===
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.

4
docs/AMDGPU/gfx9_param.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_param:
.. _amdgpu_synid_gfx9_param:
param
===========================
=====
Interpolation parameter to read:

6
docs/AMDGPU/gfx9_perm_smem.rst → docs/AMDGPU/gfx9_probe.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_perm_smem:
.. _amdgpu_synid_gfx9_probe:
imm3
===========================
probe
=====
A bit mask which indicates request permissions.

8
docs/AMDGPU/gfx9_saddr_flat_global.rst → docs/AMDGPU/gfx9_saddr.rst
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@ -5,15 +5,15 @@
* *
**************************************************
.. _amdgpu_synid9_saddr_flat_global:
.. _amdgpu_synid_gfx9_saddr:
saddr
===========================
=====
An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
See :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` for description of available addressing modes.
See :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` for description of available addressing modes.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`

8
docs/AMDGPU/gfx9_saddr_flat_scratch.rst → docs/AMDGPU/gfx9_saddr_1.rst
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@ -5,15 +5,15 @@
* *
**************************************************
.. _amdgpu_synid9_saddr_flat_scratch:
.. _amdgpu_synid_gfx9_saddr_1:
saddr
===========================
=====
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
Either this operand or :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
Either this operand or :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`

6
docs/AMDGPU/gfx9_base_smem_addr.rst → docs/AMDGPU/gfx9_sbase.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_base_smem_addr:
.. _amdgpu_synid_gfx9_sbase:
sbase
===========================
=====
A 64-bit base address for scalar memory operations.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

4
docs/AMDGPU/gfx9_base_smem_buf.rst → docs/AMDGPU/gfx9_sbase_1.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_base_smem_buf:
.. _amdgpu_synid_gfx9_sbase_1:
sbase
===========================
=====
A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.

6
docs/AMDGPU/gfx9_base_smem_scratch.rst → docs/AMDGPU/gfx9_sbase_2.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_base_smem_scratch:
.. _amdgpu_synid_gfx9_sbase_2:
sbase
===========================
=====
This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

6
docs/AMDGPU/gfx9_data_smem_atomic32.rst → docs/AMDGPU/gfx9_sdata.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_smem_atomic32:
.. _amdgpu_synid_gfx9_sdata:
sdata
===========================
=====
Input data for an atomic instruction.
@ -18,4 +18,4 @@ Optionally may serve as an output data:
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

6
docs/AMDGPU/gfx9_data_smem_atomic64.rst → docs/AMDGPU/gfx9_sdata_1.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_smem_atomic64:
.. _amdgpu_synid_gfx9_sdata_1:
sdata
===========================
=====
Input data for an atomic instruction.
@ -18,4 +18,4 @@ Optionally may serve as an output data:
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

4
docs/AMDGPU/gfx9_data_smem_atomic128.rst → docs/AMDGPU/gfx9_sdata_2.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_smem_atomic128:
.. _amdgpu_synid_gfx9_sdata_2:
sdata
===========================
=====
Input data for an atomic instruction.

6
docs/AMDGPU/gfx9_sdata32_0.rst → docs/AMDGPU/gfx9_sdata_3.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_sdata32_0:
.. _amdgpu_synid_gfx9_sdata_3:
sdata
===========================
=====
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

6
docs/AMDGPU/gfx9_sdata64_0.rst → docs/AMDGPU/gfx9_sdata_4.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_sdata64_0:
.. _amdgpu_synid_gfx9_sdata_4:
sdata
===========================
=====
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

4
docs/AMDGPU/gfx9_sdata128_0.rst → docs/AMDGPU/gfx9_sdata_5.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_sdata128_0:
.. _amdgpu_synid_gfx9_sdata_5:
sdata
===========================
=====
Instruction input.

6
docs/AMDGPU/gfx9_sdst32_0.rst → docs/AMDGPU/gfx9_sdst.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_sdst32_0:
.. _amdgpu_synid_gfx9_sdst:
sdst
===========================
====
Instruction output.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

4
docs/AMDGPU/gfx9_sdst512_0.rst → docs/AMDGPU/gfx9_sdst_1.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_sdst512_0:
.. _amdgpu_synid_gfx9_sdst_1:
sdst
===========================
====
Instruction output.

6
docs/AMDGPU/gfx9_sdst64_0.rst → docs/AMDGPU/gfx9_sdst_2.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_sdst64_0:
.. _amdgpu_synid_gfx9_sdst_2:
sdst
===========================
====
Instruction output.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

4
docs/AMDGPU/gfx9_sdst128_0.rst → docs/AMDGPU/gfx9_sdst_3.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_sdst128_0:
.. _amdgpu_synid_gfx9_sdst_3:
sdst
===========================
====
Instruction output.

4
docs/AMDGPU/gfx9_sdst256_0.rst → docs/AMDGPU/gfx9_sdst_4.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_sdst256_0:
.. _amdgpu_synid_gfx9_sdst_4:
sdst
===========================
====
Instruction output.

6
docs/AMDGPU/gfx9_sdst32_1.rst → docs/AMDGPU/gfx9_sdst_5.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_sdst32_1:
.. _amdgpu_synid_gfx9_sdst_5:
sdst
===========================
====
Instruction output.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

6
docs/AMDGPU/gfx9_sdst64_1.rst → docs/AMDGPU/gfx9_sdst_6.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_sdst64_1:
.. _amdgpu_synid_gfx9_sdst_6:
sdst
===========================
====
Instruction output.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`

6
docs/AMDGPU/gfx9_sdst32_2.rst → docs/AMDGPU/gfx9_sdst_7.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_sdst32_2:
.. _amdgpu_synid_gfx9_sdst_7:
sdst
===========================
====
Instruction output.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`ttmp<amdgpu_synid_ttmp>`

6
docs/AMDGPU/gfx9_bimm32.rst → docs/AMDGPU/gfx9_simm32.rst
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@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_bimm32:
.. _amdgpu_synid_gfx9_simm32:
imm32
===========================
simm32
======
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.

6
docs/AMDGPU/gfx9_fimm16.rst → docs/AMDGPU/gfx9_simm32_1.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_fimm16:
.. _amdgpu_synid_gfx9_simm32_1:
imm32
===========================
simm32
======
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.

6
docs/AMDGPU/gfx9_fimm32.rst → docs/AMDGPU/gfx9_simm32_2.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_fimm32:
.. _amdgpu_synid_gfx9_simm32_2:
imm32
===========================
simm32
======
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.

6
docs/AMDGPU/gfx9_offset_buf.rst → docs/AMDGPU/gfx9_soffset.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_offset_buf:
.. _amdgpu_synid_gfx9_soffset:
soffset
===========================
=======
An unsigned byte offset.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`

6
docs/AMDGPU/gfx9_offset_smem_plain.rst → docs/AMDGPU/gfx9_soffset_1.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_offset_smem_plain:
.. _amdgpu_synid_gfx9_soffset_1:
soffset
===========================
=======
An offset added to the base address to get memory address.
@ -17,4 +17,4 @@ An offset added to the base address to get memory address.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`

6
docs/AMDGPU/gfx9_offset_smem_buf.rst → docs/AMDGPU/gfx9_soffset_2.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_offset_smem_buf:
.. _amdgpu_synid_gfx9_soffset_2:
soffset
===========================
=======
An unsigned 20-bit offset added to the base address to get memory address.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`

17
docs/AMDGPU/gfx9_src.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_src:
src
===
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_src32_0.rst
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@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src32_0:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_src32_1.rst
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@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src32_1:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_src32_2.rst
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@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src32_2:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_src32_3.rst
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@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src32_3:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_src32_4.rst
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@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src32_4:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`

17
docs/AMDGPU/gfx9_src32_5.rst
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@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src32_5:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`

17
docs/AMDGPU/gfx9_src32_6.rst
View File

@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src32_6:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`

17
docs/AMDGPU/gfx9_src32_7.rst
View File

@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src32_7:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`

17
docs/AMDGPU/gfx9_src64_0.rst
View File

@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_src64_0:
src
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

10
docs/AMDGPU/gfx9_ssrc64_2.rst → docs/AMDGPU/gfx9_src_1.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_ssrc64_2:
.. _amdgpu_synid_gfx9_src_1:
ssrc
===========================
src
===
Instruction input.
*Size:* 2 dwords.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`

17
docs/AMDGPU/gfx9_src_10.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_src_10:
src
===
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`

17
docs/AMDGPU/gfx9_src_2.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_src_2:
src
===
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_src_3.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_src_3:
src
===
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_src_4.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_src_4:
src
===
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`

6
docs/AMDGPU/gfx9_vsrc32_1.rst → docs/AMDGPU/gfx9_src_5.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_vsrc32_1:
.. _amdgpu_synid_gfx9_src_5:
vsrc
===========================
src
===
Instruction input.

17
docs/AMDGPU/gfx9_src_6.rst Normal file
View File

@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_src_6:
src
===
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`

10
docs/AMDGPU/gfx9_ssrc64_0.rst → docs/AMDGPU/gfx9_src_7.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_ssrc64_0:
.. _amdgpu_synid_gfx9_src_7:
ssrc
===========================
src
===
Instruction input.
*Size:* 2 dwords.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_src_8.rst Normal file
View File

@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_src_8:
src
===
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`

6
docs/AMDGPU/gfx9_src64_1.rst → docs/AMDGPU/gfx9_src_9.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_src64_1:
.. _amdgpu_synid_gfx9_src_9:
src
===========================
===
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`

4
docs/AMDGPU/gfx9_rsrc_mimg.rst → docs/AMDGPU/gfx9_srsrc.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_rsrc_mimg:
.. _amdgpu_synid_gfx9_srsrc:
srsrc
===========================
=====
Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.

4
docs/AMDGPU/gfx9_rsrc_buf.rst → docs/AMDGPU/gfx9_srsrc_1.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_rsrc_buf:
.. _amdgpu_synid_gfx9_srsrc_1:
srsrc
===========================
=====
Buffer resource constant which defines the address and characteristics of the buffer in memory.

4
docs/AMDGPU/gfx9_samp_mimg.rst → docs/AMDGPU/gfx9_ssamp.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_samp_mimg:
.. _amdgpu_synid_gfx9_ssamp:
ssamp
===========================
=====
Sampler constant used to specify filtering options applied to the image data after it is read.

17
docs/AMDGPU/gfx9_ssrc.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_ssrc:
ssrc
====
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_ssrc32_0.rst
View File

@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_ssrc32_0:
ssrc
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
docs/AMDGPU/gfx9_ssrc32_4.rst
View File

@ -1,17 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_ssrc32_4:
ssrc
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`

17
docs/AMDGPU/gfx9_ssrc_1.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_ssrc_1:
ssrc
====
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

6
docs/AMDGPU/gfx9_ssrc32_1.rst → docs/AMDGPU/gfx9_ssrc_2.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_ssrc32_1:
.. _amdgpu_synid_gfx9_ssrc_2:
ssrc
===========================
====
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

6
docs/AMDGPU/gfx9_ssrc64_1.rst → docs/AMDGPU/gfx9_ssrc_3.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_ssrc64_1:
.. _amdgpu_synid_gfx9_ssrc_3:
ssrc
===========================
====
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

17
docs/AMDGPU/gfx9_ssrc_4.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_ssrc_4:
ssrc
====
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`

6
docs/AMDGPU/gfx9_ssrc64_3.rst → docs/AMDGPU/gfx9_ssrc_5.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_ssrc64_3:
.. _amdgpu_synid_gfx9_ssrc_5:
ssrc
===========================
====
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`

6
docs/AMDGPU/gfx9_ssrc32_2.rst → docs/AMDGPU/gfx9_ssrc_6.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_ssrc32_2:
.. _amdgpu_synid_gfx9_ssrc_6:
ssrc
===========================
====
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

6
docs/AMDGPU/gfx9_ssrc32_3.rst → docs/AMDGPU/gfx9_ssrc_7.rst
View File

@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_ssrc32_3:
.. _amdgpu_synid_gfx9_ssrc_7:
ssrc
===========================
====
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`

17
docs/AMDGPU/gfx9_ssrc_8.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_ssrc_8:
ssrc
====
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`

4
docs/AMDGPU/gfx9_tgt.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_tgt:
.. _amdgpu_synid_gfx9_tgt:
tgt
===========================
===
An export target:

6
docs/AMDGPU/gfx9_type_dev.rst → docs/AMDGPU/gfx9_type_deviation.rst
View File

@ -5,9 +5,9 @@
* *
**************************************************
.. _amdgpu_synid9_type_dev:
.. _amdgpu_synid_gfx9_type_deviation:
Type deviation
===========================
Type Deviation
==============
*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.

4
docs/AMDGPU/gfx9_addr_ds.rst → docs/AMDGPU/gfx9_vaddr.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_addr_ds:
.. _amdgpu_synid_gfx9_vaddr:
vaddr
===========================
=====
An offset from the start of GDS/LDS memory.

4
docs/AMDGPU/gfx9_addr_flat.rst → docs/AMDGPU/gfx9_vaddr_1.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_addr_flat:
.. _amdgpu_synid_gfx9_vaddr_1:
vaddr
===========================
=====
A 64-bit flat address.

20
docs/AMDGPU/gfx9_vaddr_2.rst Normal file
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@ -0,0 +1,20 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_vaddr_2:
vaddr
=====
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
* Address = :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx9_saddr>` set to :ref:`off<amdgpu_synid_off>`.
* Address = :ref:`saddr<amdgpu_synid_gfx9_saddr>` + :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx9_saddr>` is not :ref:`off<amdgpu_synid_off>`.
*Size:* 1 or 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

6
docs/AMDGPU/gfx9_vaddr_flat_scratch.rst → docs/AMDGPU/gfx9_vaddr_3.rst
View File

@ -5,14 +5,14 @@
* *
**************************************************
.. _amdgpu_synid9_vaddr_flat_scratch:
.. _amdgpu_synid_gfx9_vaddr_3:
vaddr
===========================
=====
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
Either this operand or :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
Either this operand or :ref:`saddr<amdgpu_synid_gfx9_saddr_1>` must be set to :ref:`off<amdgpu_synid_off>`.
*Size:* 1 dword.

4
docs/AMDGPU/gfx9_addr_mimg.rst → docs/AMDGPU/gfx9_vaddr_4.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_addr_mimg:
.. _amdgpu_synid_gfx9_vaddr_4:
vaddr
===========================
=====
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.

4
docs/AMDGPU/gfx9_addr_buf.rst → docs/AMDGPU/gfx9_vaddr_5.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_addr_buf:
.. _amdgpu_synid_gfx9_vaddr_5:
vaddr
===========================
=====
This is an optional operand which may specify offset and/or index.

20
docs/AMDGPU/gfx9_vaddr_flat_global.rst
View File

@ -1,20 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_vaddr_flat_global:
vaddr
===========================
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
* Address = :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid9_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
* Address = :ref:`saddr<amdgpu_synid9_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid9_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
*Size:* 1 or 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

4
docs/AMDGPU/gfx9_vcc_64.rst → docs/AMDGPU/gfx9_vcc.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_vcc_64:
.. _amdgpu_synid_gfx9_vcc:
vcc
===========================
===
Vector condition code.

4
docs/AMDGPU/gfx9_vdata32_0.rst → docs/AMDGPU/gfx9_vdata.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_vdata32_0:
.. _amdgpu_synid_gfx9_vdata:
vdata
===========================
=====
Instruction input.

17
docs/AMDGPU/gfx9_vdata0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_vdata0:
vdata0
======
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
docs/AMDGPU/gfx9_vdata0_1.rst Normal file
View File

@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_vdata0_1:
vdata0
======
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
docs/AMDGPU/gfx9_vdata1.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_vdata1:
vdata1
======
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
docs/AMDGPU/gfx9_vdata1_1.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx9_vdata1_1:
vdata1
======
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

4
docs/AMDGPU/gfx9_vdata64_0.rst → docs/AMDGPU/gfx9_vdata_1.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_vdata64_0:
.. _amdgpu_synid_gfx9_vdata_1:
vdata
===========================
=====
Instruction input.

4
docs/AMDGPU/gfx9_data_buf_atomic128.rst → docs/AMDGPU/gfx9_vdata_10.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_buf_atomic128:
.. _amdgpu_synid_gfx9_vdata_10:
vdata
===========================
=====
Input data for an atomic instruction.

4
docs/AMDGPU/gfx9_vdata128_0.rst → docs/AMDGPU/gfx9_vdata_2.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_vdata128_0:
.. _amdgpu_synid_gfx9_vdata_2:
vdata
===========================
=====
Instruction input.

4
docs/AMDGPU/gfx9_vdata96_0.rst → docs/AMDGPU/gfx9_vdata_3.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_vdata96_0:
.. _amdgpu_synid_gfx9_vdata_3:
vdata
===========================
=====
Instruction input.

4
docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst → docs/AMDGPU/gfx9_vdata_4.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_mimg_atomic_reg:
.. _amdgpu_synid_gfx9_vdata_4:
vdata
===========================
=====
Input data for an atomic instruction.

5
docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst → docs/AMDGPU/gfx9_vdata_5.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_mimg_atomic_cmp:
.. _amdgpu_synid_gfx9_vdata_5:
vdata
===========================
=====
Input data for an atomic instruction.
@ -23,5 +23,4 @@ Optionally may serve as an output data:
Note: the surface data format is indicated in the image resource constant but not in the instruction.
*Operands:* :ref:`v<amdgpu_synid_v>`

5
docs/AMDGPU/gfx9_data_mimg_store_d16.rst → docs/AMDGPU/gfx9_vdata_6.rst
View File

@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_mimg_store_d16:
.. _amdgpu_synid_gfx9_vdata_6:
vdata
===========================
=====
Image data to store by an *image_store* instruction.
@ -17,5 +17,4 @@ Image data to store by an *image_store* instruction.
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
*Operands:* :ref:`v<amdgpu_synid_v>`

5
docs/AMDGPU/gfx9_data_mimg_store.rst → docs/AMDGPU/gfx9_vdata_7.rst
View File

@ -5,14 +5,13 @@
* *
**************************************************
.. _amdgpu_synid9_data_mimg_store:
.. _amdgpu_synid_gfx9_vdata_7:
vdata
===========================
=====
Image data to store by an *image_store* instruction.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

4
docs/AMDGPU/gfx9_data_buf_atomic32.rst → docs/AMDGPU/gfx9_vdata_8.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_buf_atomic32:
.. _amdgpu_synid_gfx9_vdata_8:
vdata
===========================
=====
Input data for an atomic instruction.

4
docs/AMDGPU/gfx9_data_buf_atomic64.rst → docs/AMDGPU/gfx9_vdata_9.rst
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@ -5,10 +5,10 @@
* *
**************************************************
.. _amdgpu_synid9_data_buf_atomic64:
.. _amdgpu_synid_gfx9_vdata_9:
vdata
===========================
=====
Input data for an atomic instruction.

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