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llvm-mirror/test/MC/Mips/mips-jump-delay-slots.s

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[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# Verify that every branch and jump instruction is followed by a delay slot.
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
#
# RUN: llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s
.set noat
# CHECK: b 1332
# CHECK: nop
b 1332
# CHECK: bc1f 1332
# CHECK: nop
bc1f 1332
# CHECK: bc1t 1332
# CHECK: nop
bc1t 1332
# CHECK: beq $9, $6, 1332
# CHECK: nop
beq $9,$6,1332
# CHECK: bgez $6, 1332
# CHECK: nop
bgez $6,1332
# CHECK: bgezal $6, 1332
# CHECK: nop
bgezal $6,1332
# CHECK: bgtz $6, 1332
# CHECK: nop
bgtz $6,1332
# CHECK: blez $6, 1332
# CHECK: nop
blez $6,1332
# CHECK: bltz $6, 1332
# CHECK: nop
bltz $6,1332
# CHECK: bne $9, $6, 1332
# CHECK: nop
bne $9,$6,1332
# CHECK: bltzal $6, 1332
# CHECK: nop
bltzal $6,1332
# CHECK: bal 1332
# CHECK: nop
bal 1332
# CHECK: bnez $11, 1332
# CHECK: nop
bnez $11,1332
# CHECK: beqz $11, 1332
# CHECK: nop
beqz $11,1332
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 16:08:28 +02:00
# CHECK: bc1fl 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 16:08:28 +02:00
bc1fl 1332
# CHECK: bc1fl 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 16:08:28 +02:00
bc1fl $fcc0, 1332
# CHECK: bc1fl $fcc3, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 16:08:28 +02:00
bc1fl $fcc3, 1332
# CHECK: bc1tl 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 16:08:28 +02:00
bc1tl 1332
# CHECK: bc1tl 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 16:08:28 +02:00
bc1tl $fcc0, 1332
# CHECK: bc1tl $fcc3, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 16:08:28 +02:00
bc1tl $fcc3, 1332
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
# CHECK: beql $9, $6, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
beql $9,$6,1332
[mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions. Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 llvm-svn: 234401
2015-04-08 14:15:05 +02:00
# CHECK: beql $9, $zero, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions. Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 llvm-svn: 234401
2015-04-08 14:15:05 +02:00
beqzl $9,1332
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
# CHECK: bnel $9, $6, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
bnel $9,$6,1332
[mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions. Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 llvm-svn: 234401
2015-04-08 14:15:05 +02:00
# CHECK: bnel $9, $zero, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions. Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 llvm-svn: 234401
2015-04-08 14:15:05 +02:00
bnezl $9,1332
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
# CHECK: bgezl $6, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
bgezl $6,1332
# CHECK: bgtzl $6, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
bgtzl $6,1332
# CHECK: blezl $6, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
blezl $6,1332
# CHECK: bltzl $6, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
bltzl $6,1332
# CHECK: bgezall $6, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
bgezall $6,1332
# CHECK: bltzall $6, 1332
[mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
2017-09-28 17:24:07 +02:00
# CHECK: nop
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 14:38:35 +02:00
bltzall $6,1332
# CHECK: j 1328
# CHECK: nop
j 1328
# CHECK: jal 1328
# CHECK: nop
jal 1328
# CHECK: jalr $6
# CHECK: nop
jalr $6
# CHECK: jalr $25
# CHECK: nop
jalr $31,$25
# CHECK: jalr $10, $11
# CHECK: nop
jalr $10,$11
# CHECK: jr $7
# CHECK: nop
jr $7
# CHECK: jr $7
# CHECK: nop
j $7
# CHECK: jalr $25
# CHECK: nop
jal $25
# CHECK: jalr $4, $25
# CHECK: nop
jal $4,$25
# CHECK: jalx lab
# CHECK: nop
jalx lab
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