2012-02-27 03:21:34 +01:00
|
|
|
//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
|
2007-06-06 09:42:06 +02:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 21:36:04 +01:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-06-06 09:42:06 +02:00
|
|
|
//
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 09:42:06 +02:00
|
|
|
// Declarations that describe the MIPS register file
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2011-09-22 19:57:32 +02:00
|
|
|
let Namespace = "Mips" in {
|
2013-06-01 01:45:26 +02:00
|
|
|
def sub_fpeven : SubRegIndex<32>;
|
|
|
|
def sub_fpodd : SubRegIndex<32, 32>;
|
|
|
|
def sub_32 : SubRegIndex<32>;
|
|
|
|
def sub_lo : SubRegIndex<32>;
|
|
|
|
def sub_hi : SubRegIndex<32, 32>;
|
|
|
|
def sub_dsp16_19 : SubRegIndex<4, 16>;
|
|
|
|
def sub_dsp20 : SubRegIndex<1, 20>;
|
|
|
|
def sub_dsp21 : SubRegIndex<1, 21>;
|
|
|
|
def sub_dsp22 : SubRegIndex<1, 22>;
|
|
|
|
def sub_dsp23 : SubRegIndex<1, 23>;
|
2011-09-22 19:57:32 +02:00
|
|
|
}
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2013-03-15 00:09:19 +01:00
|
|
|
class Unallocatable {
|
|
|
|
bit isAllocatable = 0;
|
|
|
|
}
|
|
|
|
|
2007-06-06 09:42:06 +02:00
|
|
|
// We have banks of 32 registers each.
|
2012-12-10 21:04:40 +01:00
|
|
|
class MipsReg<bits<16> Enc, string n> : Register<n> {
|
|
|
|
let HWEncoding = Enc;
|
2007-06-06 09:42:06 +02:00
|
|
|
let Namespace = "Mips";
|
|
|
|
}
|
|
|
|
|
2012-12-10 21:04:40 +01:00
|
|
|
class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
|
2009-11-19 07:06:13 +01:00
|
|
|
: RegisterWithSubRegs<n, subregs> {
|
2012-12-10 21:04:40 +01:00
|
|
|
let HWEncoding = Enc;
|
2009-11-19 07:06:13 +01:00
|
|
|
let Namespace = "Mips";
|
|
|
|
}
|
|
|
|
|
2007-06-06 09:42:06 +02:00
|
|
|
// Mips CPU Registers
|
2012-12-10 21:04:40 +01:00
|
|
|
class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2011-09-23 04:33:15 +02:00
|
|
|
// Mips 64-bit CPU Registers
|
2012-12-10 21:04:40 +01:00
|
|
|
class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
|
|
|
|
: MipsRegWithSubRegs<Enc, n, subregs> {
|
2011-09-23 04:33:15 +02:00
|
|
|
let SubRegIndices = [sub_32];
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
// Mips 32-bit FPU Registers
|
2012-12-10 21:04:40 +01:00
|
|
|
class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
|
|
|
// Mips 64-bit (aliased) FPU Registers
|
2012-12-10 21:04:40 +01:00
|
|
|
class AFPR<bits<16> Enc, string n, list<Register> subregs>
|
|
|
|
: MipsRegWithSubRegs<Enc, n, subregs> {
|
2010-05-26 19:27:12 +02:00
|
|
|
let SubRegIndices = [sub_fpeven, sub_fpodd];
|
2012-01-18 01:16:39 +01:00
|
|
|
let CoveredBySubRegs = 1;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
}
|
|
|
|
|
2012-12-10 21:04:40 +01:00
|
|
|
class AFPR64<bits<16> Enc, string n, list<Register> subregs>
|
|
|
|
: MipsRegWithSubRegs<Enc, n, subregs> {
|
2011-09-22 20:24:21 +02:00
|
|
|
let SubRegIndices = [sub_32];
|
2011-09-22 05:48:47 +02:00
|
|
|
}
|
|
|
|
|
2013-03-29 04:27:21 +01:00
|
|
|
// Accumulator Registers
|
2013-08-08 23:54:26 +02:00
|
|
|
class ACCReg<bits<16> Enc, string n, list<Register> subregs>
|
2013-03-29 04:27:21 +01:00
|
|
|
: MipsRegWithSubRegs<Enc, n, subregs> {
|
|
|
|
let SubRegIndices = [sub_lo, sub_hi];
|
|
|
|
let CoveredBySubRegs = 1;
|
|
|
|
}
|
|
|
|
|
2011-05-31 04:53:58 +02:00
|
|
|
// Mips Hardware Registers
|
2012-12-10 21:04:40 +01:00
|
|
|
class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
|
2011-05-31 04:53:58 +02:00
|
|
|
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
// Registers
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
|
|
|
let Namespace = "Mips" in {
|
|
|
|
// General Purpose Registers
|
2012-07-11 22:51:50 +02:00
|
|
|
def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
|
2012-11-02 22:26:03 +01:00
|
|
|
def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
|
|
|
|
def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
|
2011-05-26 21:25:47 +02:00
|
|
|
def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
|
|
|
|
def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
|
|
|
|
def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
|
|
|
|
def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
|
|
|
|
def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
|
|
|
|
def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
|
|
|
|
def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
|
|
|
|
def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
|
|
|
|
def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
|
|
|
|
def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
|
|
|
|
def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
|
|
|
|
def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
|
|
|
|
def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
|
|
|
|
def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
|
|
|
|
def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
|
|
|
|
def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
|
|
|
|
def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
|
|
|
|
def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
|
|
|
|
def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
|
|
|
|
def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
|
|
|
|
def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
|
|
|
|
def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
|
|
|
|
def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
|
2012-07-11 22:51:50 +02:00
|
|
|
def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
|
|
|
|
def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
|
|
|
|
def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
|
|
|
|
def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
|
2011-03-04 18:51:39 +01:00
|
|
|
|
2011-09-23 04:33:15 +02:00
|
|
|
// General Purpose 64-bit Registers
|
2012-07-11 22:51:50 +02:00
|
|
|
def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
|
2012-11-02 22:26:03 +01:00
|
|
|
def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;
|
2012-02-02 03:56:14 +01:00
|
|
|
def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
|
|
|
|
def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
|
|
|
|
def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
|
|
|
|
def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
|
|
|
|
def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
|
|
|
|
def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
|
|
|
|
def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
|
|
|
|
def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
|
2012-02-27 03:21:34 +01:00
|
|
|
def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
|
|
|
|
def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
|
|
|
|
def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
|
|
|
|
def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
|
|
|
|
def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
|
|
|
|
def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
|
|
|
|
def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
|
|
|
|
def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
|
|
|
|
def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
|
|
|
|
def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
|
|
|
|
def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
|
|
|
|
def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
|
|
|
|
def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
|
2012-02-02 03:56:14 +01:00
|
|
|
def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
|
|
|
|
def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
|
|
|
|
def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
|
|
|
|
def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
|
|
|
|
def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
|
2012-07-11 22:51:50 +02:00
|
|
|
def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
|
|
|
|
def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
|
|
|
|
def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
|
|
|
|
def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
|
2011-09-23 04:33:15 +02:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
/// Mips Single point precision FPU Registers
|
2013-07-17 21:09:27 +02:00
|
|
|
foreach I = 0-31 in
|
|
|
|
def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
|
2011-03-04 18:51:39 +01:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
/// Mips Double point precision FPU Registers (aliased
|
|
|
|
/// with the single precision to hold 64 bit values)
|
2013-07-17 21:09:27 +02:00
|
|
|
foreach I = 0-15 in
|
|
|
|
def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1),
|
|
|
|
[!cast<FPR>("F"#!shl(I, 1)),
|
|
|
|
!cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
2011-09-22 05:48:47 +02:00
|
|
|
/// Mips Double point precision FPU Registers in MFP64 mode.
|
2013-07-17 21:09:27 +02:00
|
|
|
foreach I = 0-31 in
|
|
|
|
def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I)]>,
|
|
|
|
DwarfRegNum<[!add(I, 32)]>;
|
2011-09-22 05:48:47 +02:00
|
|
|
|
2008-08-02 21:42:36 +02:00
|
|
|
// Hi/Lo registers
|
2013-04-18 02:52:44 +02:00
|
|
|
def HI : Register<"ac0">, DwarfRegNum<[64]>;
|
|
|
|
def HI1 : Register<"ac1">, DwarfRegNum<[176]>;
|
|
|
|
def HI2 : Register<"ac2">, DwarfRegNum<[178]>;
|
|
|
|
def HI3 : Register<"ac3">, DwarfRegNum<[180]>;
|
|
|
|
def LO : Register<"ac0">, DwarfRegNum<[65]>;
|
|
|
|
def LO1 : Register<"ac1">, DwarfRegNum<[177]>;
|
|
|
|
def LO2 : Register<"ac2">, DwarfRegNum<[179]>;
|
|
|
|
def LO3 : Register<"ac3">, DwarfRegNum<[181]>;
|
2008-08-02 21:42:36 +02:00
|
|
|
|
2011-09-23 20:11:56 +02:00
|
|
|
let SubRegIndices = [sub_32] in {
|
|
|
|
def HI64 : RegisterWithSubRegs<"hi", [HI]>;
|
|
|
|
def LO64 : RegisterWithSubRegs<"lo", [LO]>;
|
|
|
|
}
|
|
|
|
|
2013-07-01 22:31:44 +02:00
|
|
|
// FP control registers.
|
|
|
|
foreach I = 0-31 in
|
|
|
|
def FCR#I : MipsReg<#I, ""#I>;
|
2011-05-31 04:53:58 +02:00
|
|
|
|
2013-07-26 21:03:48 +02:00
|
|
|
// FP condition code registers.
|
|
|
|
foreach I = 0-7 in
|
|
|
|
def FCC#I : MipsReg<#I, "fcc"#I>;
|
2012-07-11 22:51:50 +02:00
|
|
|
|
2012-08-17 22:16:42 +02:00
|
|
|
// PC register
|
|
|
|
def PC : Register<"pc">;
|
|
|
|
|
2011-05-31 04:53:58 +02:00
|
|
|
// Hardware register $29
|
2012-12-10 21:04:40 +01:00
|
|
|
def HWR29 : MipsReg<29, "29">;
|
2012-09-22 01:48:37 +02:00
|
|
|
|
|
|
|
// Accum registers
|
2013-08-08 23:54:26 +02:00
|
|
|
def AC0 : ACCReg<0, "ac0", [LO, HI]>;
|
|
|
|
def AC1 : ACCReg<1, "ac1", [LO1, HI1]>;
|
|
|
|
def AC2 : ACCReg<2, "ac2", [LO2, HI2]>;
|
|
|
|
def AC3 : ACCReg<3, "ac3", [LO3, HI3]>;
|
2013-03-29 04:27:21 +01:00
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def AC0_64 : ACCReg<0, "ac0", [LO64, HI64]>;
|
2012-09-22 01:48:37 +02:00
|
|
|
|
2013-05-03 20:37:49 +02:00
|
|
|
// DSP-ASE control register fields.
|
|
|
|
def DSPPos : Register<"">;
|
|
|
|
def DSPSCount : Register<"">;
|
|
|
|
def DSPCarry : Register<"">;
|
|
|
|
def DSPEFI : Register<"">;
|
|
|
|
def DSPOutFlag16_19 : Register<"">;
|
|
|
|
def DSPOutFlag20 : Register<"">;
|
|
|
|
def DSPOutFlag21 : Register<"">;
|
|
|
|
def DSPOutFlag22 : Register<"">;
|
|
|
|
def DSPOutFlag23 : Register<"">;
|
2013-05-01 00:37:26 +02:00
|
|
|
def DSPCCond : Register<"">;
|
2013-05-03 20:37:49 +02:00
|
|
|
|
|
|
|
let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
|
|
|
|
sub_dsp23] in
|
|
|
|
def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,
|
|
|
|
DSPOutFlag21, DSPOutFlag22,
|
|
|
|
DSPOutFlag23]>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
}
|
|
|
|
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
// Register Classes
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
class GPR32Class<list<ValueType> regTypes> :
|
2012-09-22 01:48:37 +02:00
|
|
|
RegisterClass<"Mips", regTypes, 32, (add
|
2012-07-11 22:51:50 +02:00
|
|
|
// Reserved
|
|
|
|
ZERO, AT,
|
2007-06-06 09:42:06 +02:00
|
|
|
// Return Values and Arguments
|
2011-06-16 01:28:14 +02:00
|
|
|
V0, V1, A0, A1, A2, A3,
|
2007-06-06 09:42:06 +02:00
|
|
|
// Not preserved across procedure calls
|
2012-07-11 22:51:50 +02:00
|
|
|
T0, T1, T2, T3, T4, T5, T6, T7,
|
2007-06-06 09:42:06 +02:00
|
|
|
// Callee save
|
|
|
|
S0, S1, S2, S3, S4, S5, S6, S7,
|
2012-07-11 22:51:50 +02:00
|
|
|
// Not preserved across procedure calls
|
|
|
|
T8, T9,
|
2007-06-06 09:42:06 +02:00
|
|
|
// Reserved
|
2012-07-11 22:51:50 +02:00
|
|
|
K0, K1, GP, SP, FP, RA)>;
|
2008-06-07 23:32:41 +02:00
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR32 : GPR32Class<[i32]>;
|
|
|
|
def DSPRegs : GPR32Class<[v4i8, v2i16]>;
|
2012-09-22 01:48:37 +02:00
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
|
2012-07-11 22:51:50 +02:00
|
|
|
// Reserved
|
|
|
|
ZERO_64, AT_64,
|
2011-09-23 20:11:56 +02:00
|
|
|
// Return Values and Arguments
|
|
|
|
V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
|
|
|
|
// Not preserved across procedure calls
|
2012-07-11 22:51:50 +02:00
|
|
|
T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
|
2011-09-23 20:11:56 +02:00
|
|
|
// Callee save
|
|
|
|
S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
|
2012-07-11 22:51:50 +02:00
|
|
|
// Not preserved across procedure calls
|
|
|
|
T8_64, T9_64,
|
2011-09-23 20:11:56 +02:00
|
|
|
// Reserved
|
2012-07-11 22:51:50 +02:00
|
|
|
K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
|
2011-09-23 20:11:56 +02:00
|
|
|
|
2012-05-17 00:19:56 +02:00
|
|
|
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
|
|
|
|
// Return Values and Arguments
|
|
|
|
V0, V1, A0, A1, A2, A3,
|
|
|
|
// Callee save
|
|
|
|
S0, S1)>;
|
|
|
|
|
2013-08-04 03:13:25 +02:00
|
|
|
def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
|
|
|
|
// Return Values and Arguments
|
|
|
|
V0, V1, A0, A1, A2, A3,
|
|
|
|
// Callee save
|
|
|
|
S0, S1,
|
|
|
|
SP)>;
|
|
|
|
|
2013-03-15 00:09:19 +01:00
|
|
|
def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
|
2012-05-24 20:32:33 +02:00
|
|
|
|
2013-03-15 00:09:19 +01:00
|
|
|
def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
|
2012-05-17 00:19:56 +02:00
|
|
|
|
2009-03-21 01:05:07 +01:00
|
|
|
// 64bit fp:
|
|
|
|
// * FGR64 - 32 64-bit registers
|
2011-03-04 18:51:39 +01:00
|
|
|
// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
|
2009-03-21 01:05:07 +01:00
|
|
|
//
|
|
|
|
// 32bit fp:
|
|
|
|
// * FGR32 - 16 32-bit even registers
|
|
|
|
// * FGR32 - 32 32-bit registers (single float only mode)
|
2011-06-16 01:28:14 +02:00
|
|
|
def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
|
2008-06-07 23:32:41 +02:00
|
|
|
|
2011-06-16 01:28:14 +02:00
|
|
|
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
|
2008-06-07 23:32:41 +02:00
|
|
|
// Return Values and Arguments
|
2012-07-11 22:51:50 +02:00
|
|
|
D0, D1,
|
|
|
|
// Not preserved across procedure calls
|
|
|
|
D2, D3, D4, D5,
|
|
|
|
// Return Values and Arguments
|
|
|
|
D6, D7,
|
2008-06-07 23:32:41 +02:00
|
|
|
// Not preserved across procedure calls
|
2012-07-11 22:51:50 +02:00
|
|
|
D8, D9,
|
2008-06-07 23:32:41 +02:00
|
|
|
// Callee save
|
2012-05-04 05:30:34 +02:00
|
|
|
D10, D11, D12, D13, D14, D15)>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
2012-05-04 05:30:34 +02:00
|
|
|
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
|
2011-09-23 20:11:56 +02:00
|
|
|
|
2013-07-01 22:31:44 +02:00
|
|
|
// FP control registers.
|
|
|
|
def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
|
|
|
|
Unallocatable;
|
|
|
|
|
|
|
|
// FP condition code registers.
|
2013-07-26 21:03:48 +02:00
|
|
|
def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
|
|
|
|
Unallocatable;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
2009-05-27 19:23:44 +02:00
|
|
|
// Hi/Lo Registers
|
2013-05-01 01:22:09 +02:00
|
|
|
def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;
|
|
|
|
def HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>;
|
2013-04-18 02:52:44 +02:00
|
|
|
def LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>;
|
|
|
|
def HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>;
|
2013-05-01 01:22:09 +02:00
|
|
|
def LORegs64 : RegisterClass<"Mips", [i64], 64, (add LO64)>;
|
|
|
|
def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>;
|
2008-08-02 21:42:36 +02:00
|
|
|
|
2011-05-31 04:53:58 +02:00
|
|
|
// Hardware registers
|
2013-03-15 00:09:19 +01:00
|
|
|
def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
|
2011-12-08 00:26:03 +01:00
|
|
|
|
2012-09-26 21:25:21 +02:00
|
|
|
// Accumulator Registers
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
|
2013-03-29 04:27:21 +01:00
|
|
|
let Size = 64;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
|
2013-03-29 04:27:21 +01:00
|
|
|
let Size = 128;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
|
2013-03-29 04:27:21 +01:00
|
|
|
let Size = 64;
|
|
|
|
}
|
2013-01-12 02:03:14 +01:00
|
|
|
|
2013-05-01 00:37:26 +02:00
|
|
|
def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
|
|
|
|
|
|
|
|
// Register Operands.
|
2013-06-19 12:14:36 +02:00
|
|
|
|
|
|
|
class MipsAsmRegOperand : AsmOperandClass {
|
|
|
|
let RenderMethod = "addRegAsmOperands";
|
|
|
|
}
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR32AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "GPR32Asm";
|
|
|
|
let ParserMethod = "parseGPR32";
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR64AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "GPR64Asm";
|
|
|
|
let ParserMethod = "parseGPR64";
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC64DSPAsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "ACC64DSPAsm";
|
|
|
|
let ParserMethod = "parseACC64DSP";
|
2013-08-07 00:20:40 +02:00
|
|
|
}
|
|
|
|
|
2013-06-19 12:14:36 +02:00
|
|
|
def CCRAsmOperand : MipsAsmRegOperand {
|
2013-01-12 02:03:14 +01:00
|
|
|
let Name = "CCRAsm";
|
|
|
|
let ParserMethod = "parseCCRRegs";
|
|
|
|
}
|
|
|
|
|
2013-06-24 12:05:34 +02:00
|
|
|
def AFGR64AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "AFGR64Asm";
|
|
|
|
let ParserMethod = "parseAFGR64Regs";
|
|
|
|
}
|
|
|
|
|
|
|
|
def FGR64AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "FGR64Asm";
|
|
|
|
let ParserMethod = "parseFGR64Regs";
|
|
|
|
}
|
|
|
|
|
|
|
|
def FGR32AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "FGR32Asm";
|
|
|
|
let ParserMethod = "parseFGR32Regs";
|
|
|
|
}
|
|
|
|
|
2013-07-30 12:12:14 +02:00
|
|
|
def FCCRegsAsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "FCCRegsAsm";
|
|
|
|
let ParserMethod = "parseFCCRegs";
|
|
|
|
}
|
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR32Opnd : RegisterOperand<GPR32> {
|
|
|
|
let ParserMatchClass = GPR32AsmOperand;
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR64Opnd : RegisterOperand<GPR64> {
|
|
|
|
let ParserMatchClass = GPR64AsmOperand;
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2013-07-26 20:50:42 +02:00
|
|
|
def CCROpnd : RegisterOperand<CCR> {
|
2013-01-12 02:03:14 +01:00
|
|
|
let ParserMatchClass = CCRAsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-06-19 12:14:36 +02:00
|
|
|
def HWRegsAsmOperand : MipsAsmRegOperand {
|
2013-01-12 02:03:14 +01:00
|
|
|
let Name = "HWRegsAsm";
|
|
|
|
let ParserMethod = "parseHWRegs";
|
|
|
|
}
|
|
|
|
|
2013-07-26 20:50:42 +02:00
|
|
|
def HWRegsOpnd : RegisterOperand<HWRegs> {
|
2013-01-12 02:03:14 +01:00
|
|
|
let ParserMatchClass = HWRegsAsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def AFGR64Opnd : RegisterOperand<AFGR64> {
|
2013-06-24 12:05:34 +02:00
|
|
|
let ParserMatchClass = AFGR64AsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def FGR64Opnd : RegisterOperand<FGR64> {
|
2013-06-24 12:05:34 +02:00
|
|
|
let ParserMatchClass = FGR64AsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def FGR32Opnd : RegisterOperand<FGR32> {
|
2013-06-24 12:05:34 +02:00
|
|
|
let ParserMatchClass = FGR32AsmOperand;
|
2013-07-30 12:12:14 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def FCCRegsOpnd : RegisterOperand<FCC> {
|
|
|
|
let ParserMatchClass = FCCRegsAsmOperand;
|
2013-08-07 00:20:40 +02:00
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
|
|
|
|
let ParserMatchClass = ACC64DSPAsmOperand;
|
2013-08-07 00:20:40 +02:00
|
|
|
}
|