2017-02-22 19:47:41 +01:00
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# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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2016-08-26 19:46:13 +02:00
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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2016-10-14 12:19:40 +02:00
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target triple = "aarch64--"
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2016-08-26 19:46:13 +02:00
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define void @test_rem() {
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entry:
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ret void
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}
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...
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---
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name: test_rem
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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2016-08-29 21:07:16 +02:00
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- { id: 9, class: _ }
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- { id: 10, class: _ }
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2016-08-26 19:46:13 +02:00
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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2016-09-09 13:46:34 +02:00
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; CHECK: [[QUOT:%[0-9]+]](s64) = G_UDIV %0, %1
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; CHECK: [[PROD:%[0-9]+]](s64) = G_MUL [[QUOT]], %1
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; CHECK: [[RES:%[0-9]+]](s64) = G_SUB %0, [[PROD]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = G_UREM %0, %1
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2016-08-26 19:46:13 +02:00
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2016-09-09 13:46:34 +02:00
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; CHECK: [[QUOT:%[0-9]+]](s32) = G_SDIV %3, %4
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; CHECK: [[PROD:%[0-9]+]](s32) = G_MUL [[QUOT]], %4
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; CHECK: [[RES:%[0-9]+]](s32) = G_SUB %3, [[PROD]]
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%3(s32) = G_TRUNC %0
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%4(s32) = G_TRUNC %1
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%5(s32) = G_SREM %3, %4
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2016-08-26 19:46:13 +02:00
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2016-09-09 13:46:34 +02:00
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; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %6
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; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %7
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; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]]
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; CHECK: [[QUOT:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
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[AArch64][GlobalISel] Legalize narrow scalar ops again.
Since r279760, we've been marking as legal operations on narrow integer
types that have wider legal equivalents (for instance, G_ADD s8).
Compared to legalizing these operations, this reduced the amount of
extends/truncates required, but was always a weird legalization decision
made at selection time.
So far, we haven't been able to formalize it in a way that permits the
selector generated from SelectionDAG patterns to be sufficient.
Using a wide instruction (say, s64), when a narrower instruction exists
(s32) would introduce register class incompatibilities (when one narrow
generic instruction is selected to the wider variant, but another is
selected to the narrower variant).
It's also impractical to limit which narrow operations are matched for
which instruction, as restricting "narrow selection" to ranges of types
clashes with potentially incompatible instruction predicates.
Concerns were also raised regarding MIPS64's sign-extended register
assumptions, as well as wrapping behavior.
See discussions in https://reviews.llvm.org/D26878.
Instead, legalize the operations.
Should we ever revert to selecting these narrow operations, we should
try to represent this more accurately: for instance, by separating
a "concrete" type on operations, and an "underlying" type on vregs, we
could move the "this narrow-looking op is really legal" decision to the
legalizer, and let the selector use the "underlying" vreg type only,
which would be guaranteed to map to a register class.
In any case, we eventually should mitigate:
- the performance impact by selecting no-op extract/truncates to COPYs
(which we currently do), and the COPYs to register reuses (which we
don't do yet).
- the compile-time impact by optimizing away extract/truncate sequences
in the legalizer.
llvm-svn: 292827
2017-01-23 22:10:05 +01:00
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; CHECK: [[QUOT32_2:%.*]](s32) = G_ANYEXT [[QUOT]](s8)
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; CHECK: [[RHS32_2:%.*]](s32) = G_ANYEXT %7(s8)
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; CHECK: [[PROD32:%.*]](s32) = G_MUL [[QUOT32_2]], [[RHS32_2]]
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; CHECK: [[PROD:%.*]](s8) = G_TRUNC [[PROD32]](s32)
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; CHECK: [[LHS32_2:%.*]](s32) = G_ANYEXT %6(s8)
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; CHECK: [[PROD32_2:%.*]](s32) = G_ANYEXT [[PROD]](s8)
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; CHECK: [[RES:%[0-9]+]](s32) = G_SUB [[LHS32_2]], [[PROD32_2]]
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2016-09-09 13:46:34 +02:00
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%6(s8) = G_TRUNC %0
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%7(s8) = G_TRUNC %1
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%8(s8) = G_SREM %6, %7
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2016-08-26 19:46:13 +02:00
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2016-08-29 21:07:16 +02:00
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; CHECK: %d0 = COPY %0
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; CHECK: %d1 = COPY %1
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; CHECK: BL $fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
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2016-09-09 13:46:34 +02:00
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; CHECK: %9(s64) = COPY %d0
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%9(s64) = G_FREM %0, %1
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2016-08-29 21:07:16 +02:00
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; CHECK: %s0 = COPY %3
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; CHECK: %s1 = COPY %4
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; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
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2016-09-09 13:46:34 +02:00
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; CHECK: %10(s32) = COPY %s0
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%10(s32) = G_FREM %3, %4
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2016-08-29 21:07:16 +02:00
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2016-08-26 19:46:13 +02:00
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...
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