llvm-mirror/test/CodeGen/X86/tailcallstack64.ll

; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s

; Check that lowered arguments on the stack do not overwrite each other.
; Add %in1 %p1 to a different temporary register (%eax).
; CHECK: movl  32(%rsp), %eax
; Move param %in1 to temp register (%r10d).
; CHECK: movl  40(%rsp), %r10d
; Add %in1 %p1 to a different temporary register (%eax).
; CHECK: addl %edi, %eax
; Move param %in2 to stack.
; CHECK: movl  %r10d, 32(%rsp)
; Move result of addition to stack.
; CHECK: movl  %eax, 40(%rsp)
; Eventually, do a TAILCALL
; CHECK: TAILCALL

declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind

define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {
entry:
        %tmp = add i32 %in1, %p1
        %retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
        ret i32 %retval
}
Don't enable the post-RA scheduler on x86 except at -O3. In its current form, it is too expensive in compile time. llvm-svn: 90781 2009-12-07 20:04:31 +01:00			`; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true \| FileCheck %s`
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142 2009-08-05 03:29:28 +02:00
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478 2008-04-30 11:19:47 +02:00			`; Check that lowered arguments on the stack do not overwrite each other.`
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142 2009-08-05 03:29:28 +02:00			`; Add %in1 %p1 to a different temporary register (%eax).`
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. llvm-svn: 106493 2010-06-22 00:17:20 +02:00			`; CHECK: movl 32(%rsp), %eax`
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142 2009-08-05 03:29:28 +02:00			`; Move param %in1 to temp register (%r10d).`
			`; CHECK: movl 40(%rsp), %r10d`
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. llvm-svn: 106493 2010-06-22 00:17:20 +02:00			`; Add %in1 %p1 to a different temporary register (%eax).`
			`; CHECK: addl %edi, %eax`
Update test. llvm-svn: 87049 2009-11-13 02:01:58 +01:00			`; Move param %in2 to stack.`
			`; CHECK: movl %r10d, 32(%rsp)`
Revert r87049, which was the workaround for the regression triggered by the recent FixedStackPseudoSourceValue-related changes, now that the specific bug that affected it is fixed, in r88954. llvm-svn: 88997 2009-11-17 00:43:42 +01:00			`; Move result of addition to stack.`
			`; CHECK: movl %eax, 40(%rsp)`
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142 2009-08-05 03:29:28 +02:00			`; Eventually, do a TAILCALL`
			`; CHECK: TAILCALL`
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478 2008-04-30 11:19:47 +02:00
Turn on post-alloc scheduling for x86. llvm-svn: 84431 2009-10-18 21:57:27 +02:00			`declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind`
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478 2008-04-30 11:19:47 +02:00
Turn on post-alloc scheduling for x86. llvm-svn: 84431 2009-10-18 21:57:27 +02:00			`define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {`
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478 2008-04-30 11:19:47 +02:00			`entry:`
			`%tmp = add i32 %in1, %p1`
Fix Bug 4278: X86-64 with -tailcallopt calling convention out of sync with regular cc. The only difference between the tail call cc and the normal cc was that one parameter register - R9 - was reserved for calling functions through a function pointer. After time the tail call cc has gotten out of sync with the regular cc. We can use R11 which is also caller saved but not used as parameter register for potential function pointers and remove the special tail call cc on x86-64. llvm-svn: 73233 2009-06-12 18:26:57 +02:00			`%retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)`
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478 2008-04-30 11:19:47 +02:00			`ret i32 %retval`
			`}`