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llvm-mirror/test/CodeGen/X86/lzcnt.ll

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Test case for X86 LZCNT instruction selection. llvm-svn: 141652
2011-10-11 08:47:01 +02:00
; RUN: llc < %s -march=x86-64 -mattr=+lzcnt | FileCheck %s
Cleanup this test a bit, sorting things and grouping them more clearly. llvm-svn: 147243
2011-12-24 11:55:42 +01:00
declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone
declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i8 @t1(i8 %x) nounwind {
%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
ret i8 %tmp
Test case for X86 LZCNT instruction selection. llvm-svn: 141652
2011-10-11 08:47:01 +02:00
; CHECK: t1:
Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] llvm-svn: 147251
2011-12-24 13:12:34 +01:00
; CHECK: lzcntl
Test case for X86 LZCNT instruction selection. llvm-svn: 141652
2011-10-11 08:47:01 +02:00
}
define i16 @t2(i16 %x) nounwind {
Manually upgrade the test suite to specify the flag to cttz and ctlz. I followed three heuristics for deciding whether to set 'true' or 'false': - Everything target independent got 'true' as that is the expected common output of the GCC builtins. - If the target arch only has one way of implementing this operation, set the flag in the way that exercises the most of codegen. For most architectures this is also the likely path from a GCC builtin, with 'true' being set. It will (eventually) require lowering away that difference, and then lowering to the architecture's operation. - Otherwise, set the flag differently dependending on which target operation should be tested. Let me know if anyone has any issue with this pattern or would like specific tests of another form. This should allow the x86 codegen to just iteratively improve as I teach the backend how to differentiate between the two forms, and everything else should remain exactly the same. llvm-svn: 146370
2011-12-12 12:59:10 +01:00
%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 false )
Test case for X86 LZCNT instruction selection. llvm-svn: 141652
2011-10-11 08:47:01 +02:00
ret i16 %tmp
; CHECK: t2:
; CHECK: lzcntw
}
Cleanup this test a bit, sorting things and grouping them more clearly. llvm-svn: 147243
2011-12-24 11:55:42 +01:00
define i32 @t3(i32 %x) nounwind {
%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 false )
ret i32 %tmp
Test case for X86 LZCNT instruction selection. llvm-svn: 141652
2011-10-11 08:47:01 +02:00
; CHECK: t3:
Cleanup this test a bit, sorting things and grouping them more clearly. llvm-svn: 147243
2011-12-24 11:55:42 +01:00
; CHECK: lzcntl
Test case for X86 LZCNT instruction selection. llvm-svn: 141652
2011-10-11 08:47:01 +02:00
}
Cleanup this test a bit, sorting things and grouping them more clearly. llvm-svn: 147243
2011-12-24 11:55:42 +01:00
define i64 @t4(i64 %x) nounwind {
%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 false )
ret i64 %tmp
Test case for X86 LZCNT instruction selection. llvm-svn: 141652
2011-10-11 08:47:01 +02:00
; CHECK: t4:
Cleanup this test a bit, sorting things and grouping them more clearly. llvm-svn: 147243
2011-12-24 11:55:42 +01:00
; CHECK: lzcntq
Test case for X86 LZCNT instruction selection. llvm-svn: 141652
2011-10-11 08:47:01 +02:00
}
Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the X86ISelLowering C++ code. Because this is lowered via an xor wrapped around a bsr, we want the dagcombine which runs after isel lowering to have a chance to clean things up. In particular, it is very common to see code which looks like: (sizeof(x)*8 - 1) ^ __builtin_clz(x) Which is trying to compute the most significant bit of 'x'. That's actually the value computed directly by the 'bsr' instruction, but if we match it too late, we'll get completely redundant xor instructions. The more naive code for the above (subtracting rather than using an xor) still isn't handled correctly due to the dagcombine getting confused. Also, while here fix an issue spotted by inspection: we should have been expanding the zero-undef variants to the normal variants when there is an 'lzcnt' instruction. Do so, and test for this. We don't want to generate unnecessary 'bsr' instructions. These two changes fix some regressions in encoding and decoding benchmarks. However, there is still a *lot* to be improve on in this type of code. llvm-svn: 147244
2011-12-24 11:55:54 +01:00
define i8 @t5(i8 %x) nounwind {
%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
ret i8 %tmp
; CHECK: t5:
Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] llvm-svn: 147251
2011-12-24 13:12:34 +01:00
; CHECK: lzcntl
Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the X86ISelLowering C++ code. Because this is lowered via an xor wrapped around a bsr, we want the dagcombine which runs after isel lowering to have a chance to clean things up. In particular, it is very common to see code which looks like: (sizeof(x)*8 - 1) ^ __builtin_clz(x) Which is trying to compute the most significant bit of 'x'. That's actually the value computed directly by the 'bsr' instruction, but if we match it too late, we'll get completely redundant xor instructions. The more naive code for the above (subtracting rather than using an xor) still isn't handled correctly due to the dagcombine getting confused. Also, while here fix an issue spotted by inspection: we should have been expanding the zero-undef variants to the normal variants when there is an 'lzcnt' instruction. Do so, and test for this. We don't want to generate unnecessary 'bsr' instructions. These two changes fix some regressions in encoding and decoding benchmarks. However, there is still a *lot* to be improve on in this type of code. llvm-svn: 147244
2011-12-24 11:55:54 +01:00
}
define i16 @t6(i16 %x) nounwind {
%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 true )
ret i16 %tmp
; CHECK: t6:
; CHECK: lzcntw
}
define i32 @t7(i32 %x) nounwind {
%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
ret i32 %tmp
; CHECK: t7:
; CHECK: lzcntl
}
define i64 @t8(i64 %x) nounwind {
%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 true )
ret i64 %tmp
; CHECK: t8:
; CHECK: lzcntq
}
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