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Rename the new unsigned and signed keywords to nuw and nsw,

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which stand for no-unsigned-wrap and no-signed-wrap.

llvm-svn: 76810
This commit is contained in:
Dan Gohman 2009-07-22 22:44:56 +00:00
parent d1f9f45b05
commit 001d777207
9 changed files with 118 additions and 115 deletions
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43
docs/LangRef.html
View File

@ -2601,9 +2601,9 @@ Instruction</a> </div>
<h5>Syntax:</h5>
<pre>
&lt;result&gt; = add &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = signed add &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = unsigned add &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = unsigned signed add &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nuw add &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nsw add &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nuw nsw add &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@ -2623,9 +2623,10 @@ Instruction</a> </div>
<p>Because LLVM integers use a two's complement representation, this instruction
is appropriate for both signed and unsigned integers.</p>
<p>If the <tt>signed</tt> and/or <tt>unsigned</tt> keywords are present,
the result value of the <tt>add</tt> is undefined if signed and/or unsigned
overflow, respectively, occurs.</p>
<p><tt>nuw</tt> and <tt>nsw</tt> stand for &quot;No Unsigned Wrap&quot;
and &quot;No Signed Wrap&quot;, respectively. If the <tt>nuw</tt> and/or
<tt>nsw</tt> keywords are present, the result value of the <tt>add</tt>
is undefined if unsigned and/or signed overflow, respectively, occurs.</p>
<h5>Example:</h5>
<pre>
@ -2673,10 +2674,10 @@ Instruction</a> </div>
<h5>Syntax:</h5>
<pre>
&lt;result&gt; = sub &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = signed sub &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = unsigned sub &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = unsigned signed sub &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = sub &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nuw sub &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nsw sub &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nuw nsw sub &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@ -2702,9 +2703,10 @@ Instruction</a> </div>
<p>Because LLVM integers use a two's complement representation, this instruction
is appropriate for both signed and unsigned integers.</p>
<p>If the <tt>signed</tt> and/or <tt>unsigned</tt> keywords are present,
the result value of the <tt>sub</tt> is undefined if signed and/or unsigned
overflow, respectively, occurs.</p>
<p><tt>nuw</tt> and <tt>nsw</tt> stand for &quot;No Unsigned Wrap&quot;
and &quot;No Signed Wrap&quot;, respectively. If the <tt>nuw</tt> and/or
<tt>nsw</tt> keywords are present, the result value of the <tt>sub</tt>
is undefined if unsigned and/or signed overflow, respectively, occurs.</p>
<h5>Example:</h5>
<pre>
@ -2759,10 +2761,10 @@ Instruction</a> </div>
<h5>Syntax:</h5>
<pre>
&lt;result&gt; = mul &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = signed mul &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = unsigned mul &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = unsigned signed mul &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = mul &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nuw mul &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nsw mul &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
&lt;result&gt; = nuw nsw mul &lt;ty&gt; &lt;op1&gt;, &lt;op2&gt; <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@ -2787,9 +2789,10 @@ Instruction</a> </div>
be sign-extended or zero-extended as appropriate to the width of the full
product.</p>
<p>If the <tt>signed</tt> and/or <tt>unsigned</tt> keywords are present,
the result value of the <tt>mul</tt> is undefined if signed and/or unsigned
overflow, respectively, occurs.</p>
<p><tt>nuw</tt> and <tt>nsw</tt> stand for &quot;No Unsigned Wrap&quot;
and &quot;No Signed Wrap&quot;, respectively. If the <tt>nuw</tt> and/or
<tt>nsw</tt> keywords are present, the result value of the <tt>mul</tt>
is undefined if unsigned and/or signed overflow, respectively, occurs.</p>
<h5>Example:</h5>
<pre>

4
lib/AsmParser/LLLexer.cpp
View File

@ -501,8 +501,8 @@ lltok::Kind LLLexer::LexIdentifier() {
KEYWORD(deplibs);
KEYWORD(datalayout);
KEYWORD(volatile);
KEYWORD(signed);
KEYWORD(unsigned);
KEYWORD(nuw);
KEYWORD(nsw);
KEYWORD(exact);
KEYWORD(align);
KEYWORD(addrspace);

58
lib/AsmParser/LLParser.cpp
View File

@ -2045,26 +2045,9 @@ bool LLParser::ParseValID(ValID &ID) {
ID.Kind = ValID::t_Constant;
return false;
}
case lltok::kw_signed: {
case lltok::kw_nuw: {
Lex.Lex();
bool AlsoUnsigned = EatIfPresent(lltok::kw_unsigned);
if (Lex.getKind() != lltok::kw_add &&
Lex.getKind() != lltok::kw_sub &&
Lex.getKind() != lltok::kw_mul)
return TokError("expected 'add', 'sub', or 'mul'");
bool Result = LLParser::ParseValID(ID);
if (!Result) {
cast<OverflowingBinaryOperator>(ID.ConstantVal)
->setHasNoSignedOverflow(true);
if (AlsoUnsigned)
cast<OverflowingBinaryOperator>(ID.ConstantVal)
->setHasNoUnsignedOverflow(true);
}
return Result;
}
case lltok::kw_unsigned: {
Lex.Lex();
bool AlsoSigned = EatIfPresent(lltok::kw_signed);
bool AlsoSigned = EatIfPresent(lltok::kw_nsw);
if (Lex.getKind() != lltok::kw_add &&
Lex.getKind() != lltok::kw_sub &&
Lex.getKind() != lltok::kw_mul)
@ -2079,6 +2062,23 @@ bool LLParser::ParseValID(ValID &ID) {
}
return Result;
}
case lltok::kw_nsw: {
Lex.Lex();
bool AlsoUnsigned = EatIfPresent(lltok::kw_nuw);
if (Lex.getKind() != lltok::kw_add &&
Lex.getKind() != lltok::kw_sub &&
Lex.getKind() != lltok::kw_mul)
return TokError("expected 'add', 'sub', or 'mul'");
bool Result = LLParser::ParseValID(ID);
if (!Result) {
cast<OverflowingBinaryOperator>(ID.ConstantVal)
->setHasNoSignedOverflow(true);
if (AlsoUnsigned)
cast<OverflowingBinaryOperator>(ID.ConstantVal)
->setHasNoUnsignedOverflow(true);
}
return Result;
}
case lltok::kw_exact: {
Lex.Lex();
if (Lex.getKind() != lltok::kw_sdiv)
@ -2609,8 +2609,8 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
return ParseStore(Inst, PFS, true);
else
return TokError("expected 'load' or 'store'");
case lltok::kw_signed: {
bool AlsoUnsigned = EatIfPresent(lltok::kw_unsigned);
case lltok::kw_nuw: {
bool AlsoSigned = EatIfPresent(lltok::kw_nsw);
if (Lex.getKind() == lltok::kw_add ||
Lex.getKind() == lltok::kw_sub ||
Lex.getKind() == lltok::kw_mul) {
@ -2618,16 +2618,16 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
KeywordVal = Lex.getUIntVal();
bool Result = ParseArithmetic(Inst, PFS, KeywordVal, 0);
if (!Result) {
cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedOverflow(true);
if (AlsoUnsigned)
cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedOverflow(true);
cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedOverflow(true);
if (AlsoSigned)
cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedOverflow(true);
}
return Result;
}
return TokError("expected 'add', 'sub', or 'mul'");
}
case lltok::kw_unsigned: {
bool AlsoSigned = EatIfPresent(lltok::kw_signed);
case lltok::kw_nsw: {
bool AlsoUnsigned = EatIfPresent(lltok::kw_nuw);
if (Lex.getKind() == lltok::kw_add ||
Lex.getKind() == lltok::kw_sub ||
Lex.getKind() == lltok::kw_mul) {
@ -2635,9 +2635,9 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
KeywordVal = Lex.getUIntVal();
bool Result = ParseArithmetic(Inst, PFS, KeywordVal, 1);
if (!Result) {
cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedOverflow(true);
if (AlsoSigned)
cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedOverflow(true);
cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedOverflow(true);
if (AlsoUnsigned)
cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedOverflow(true);
}
return Result;
}

4
lib/AsmParser/LLToken.h
View File

@ -51,8 +51,8 @@ namespace lltok {
kw_deplibs,
kw_datalayout,
kw_volatile,
kw_signed,
kw_unsigned,
kw_nuw,
kw_nsw,
kw_exact,
kw_align,
kw_addrspace,

4
lib/VMCore/AsmWriter.cpp
View File

@ -856,9 +856,9 @@ static void WriteOptimizationInfo(raw_ostream &Out, const User *U) {
if (const OverflowingBinaryOperator *OBO =
dyn_cast<OverflowingBinaryOperator>(U)) {
if (OBO->hasNoUnsignedOverflow())
Out << "unsigned ";
Out << "nuw ";
if (OBO->hasNoSignedOverflow())
Out << "signed ";
Out << "nsw ";
} else if (const SDivOperator *Div = dyn_cast<SDivOperator>(U)) {
if (Div->isExact())
Out << "exact ";

12
test/Assembler/flags-reversed.ll
View File

@ -3,16 +3,16 @@
@addr = external global i64
define i64 @add_both_reversed_ce() {
; CHECK: ret i64 unsigned signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 signed unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nsw nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sub_both_reversed_ce() {
; CHECK: ret i64 unsigned signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 signed unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nsw nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @mul_both_reversed_ce() {
; CHECK: ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 signed unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nsw nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
}

12
test/Assembler/flags-signed.ll
View File

@ -3,16 +3,16 @@
@addr = external global i64
define i64 @add_signed_ce() {
; CHECK: ret i64 signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sub_signed_ce() {
; CHECK: ret i64 signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @mul_signed_ce() {
; CHECK: ret i64 signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
}

12
test/Assembler/flags-unsigned.ll
View File

@ -3,16 +3,16 @@
@addr = external global i64
define i64 @add_unsigned_ce() {
; CHECK: ret i64 unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sub_unsigned_ce() {
; CHECK: ret i64 unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @mul_unsigned_ce() {
; CHECK: ret i64 unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
}

84
test/Assembler/flags.ll
View File

@ -2,39 +2,39 @@
@addr = external global i64
define i64 @add_signed(i64 %x, i64 %y) {
; CHECK: %z = signed add i64 %x, %y
%z = signed add i64 %x, %y
ret i64 %z
}
define i64 @sub_signed(i64 %x, i64 %y) {
; CHECK: %z = signed sub i64 %x, %y
%z = signed sub i64 %x, %y
ret i64 %z
}
define i64 @mul_signed(i64 %x, i64 %y) {
; CHECK: %z = signed mul i64 %x, %y
%z = signed mul i64 %x, %y
ret i64 %z
}
define i64 @add_unsigned(i64 %x, i64 %y) {
; CHECK: %z = unsigned add i64 %x, %y
%z = unsigned add i64 %x, %y
; CHECK: %z = nuw add i64 %x, %y
%z = nuw add i64 %x, %y
ret i64 %z
}
define i64 @sub_unsigned(i64 %x, i64 %y) {
; CHECK: %z = unsigned sub i64 %x, %y
%z = unsigned sub i64 %x, %y
; CHECK: %z = nuw sub i64 %x, %y
%z = nuw sub i64 %x, %y
ret i64 %z
}
define i64 @mul_unsigned(i64 %x, i64 %y) {
; CHECK: %z = unsigned mul i64 %x, %y
%z = unsigned mul i64 %x, %y
; CHECK: %z = nuw mul i64 %x, %y
%z = nuw mul i64 %x, %y
ret i64 %z
}
define i64 @add_signed(i64 %x, i64 %y) {
; CHECK: %z = nsw add i64 %x, %y
%z = nsw add i64 %x, %y
ret i64 %z
}
define i64 @sub_signed(i64 %x, i64 %y) {
; CHECK: %z = nsw sub i64 %x, %y
%z = nsw sub i64 %x, %y
ret i64 %z
}
define i64 @mul_signed(i64 %x, i64 %y) {
; CHECK: %z = nsw mul i64 %x, %y
%z = nsw mul i64 %x, %y
ret i64 %z
}
@ -57,38 +57,38 @@ define i64 @mul_plain(i64 %x, i64 %y) {
}
define i64 @add_both(i64 %x, i64 %y) {
; CHECK: %z = unsigned signed add i64 %x, %y
%z = unsigned signed add i64 %x, %y
; CHECK: %z = nuw nsw add i64 %x, %y
%z = nuw nsw add i64 %x, %y
ret i64 %z
}
define i64 @sub_both(i64 %x, i64 %y) {
; CHECK: %z = unsigned signed sub i64 %x, %y
%z = unsigned signed sub i64 %x, %y
; CHECK: %z = nuw nsw sub i64 %x, %y
%z = nuw nsw sub i64 %x, %y
ret i64 %z
}
define i64 @mul_both(i64 %x, i64 %y) {
; CHECK: %z = unsigned signed mul i64 %x, %y
%z = unsigned signed mul i64 %x, %y
; CHECK: %z = nuw nsw mul i64 %x, %y
%z = nuw nsw mul i64 %x, %y
ret i64 %z
}
define i64 @add_both_reversed(i64 %x, i64 %y) {
; CHECK: %z = unsigned signed add i64 %x, %y
%z = signed unsigned add i64 %x, %y
; CHECK: %z = nuw nsw add i64 %x, %y
%z = nsw nuw add i64 %x, %y
ret i64 %z
}
define i64 @sub_both_reversed(i64 %x, i64 %y) {
; CHECK: %z = unsigned signed sub i64 %x, %y
%z = signed unsigned sub i64 %x, %y
; CHECK: %z = nuw nsw sub i64 %x, %y
%z = nsw nuw sub i64 %x, %y
ret i64 %z
}
define i64 @mul_both_reversed(i64 %x, i64 %y) {
; CHECK: %z = unsigned signed mul i64 %x, %y
%z = signed unsigned mul i64 %x, %y
; CHECK: %z = nuw nsw mul i64 %x, %y
%z = nsw nuw mul i64 %x, %y
ret i64 %z
}
@ -105,18 +105,18 @@ define i64 @sdiv_plain(i64 %x, i64 %y) {
}
define i64 @add_both_ce() {
; CHECK: ret i64 unsigned signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 signed unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nsw nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sub_both_ce() {
; CHECK: ret i64 unsigned signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 signed unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nsw nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @mul_both_ce() {
; CHECK: ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
; CHECK: ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sdiv_exact_ce() {