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Make fsel emission work with both the pattern and dag-dag selectors, by

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giving it a non-instruction opcode.  The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.

llvm-svn: 23091
This commit is contained in:
Chris Lattner 2005-08-26 20:25:03 +00:00
parent 17f0f9beae
commit 04b88ca768
4 changed files with 34 additions and 14 deletions
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2
lib/Target/PowerPC/PPC32ISelPattern.cpp
View File

@ -811,7 +811,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
default:
Node->dump(); std::cerr << '\n';
assert(0 && "Node not handled!\n");
case ISD::BUILTIN_OP_END+PPC::FSEL:
case PPCISD::FSEL:
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = SelectExpr(N.getOperand(2));

9
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -629,7 +629,8 @@ SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
// target-specific node if it hasn't already been changed.
SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END)
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
N->getOpcode() < PPCISD::FIRST_NUMBER)
return Op; // Already selected.
switch (N->getOpcode()) {
@ -747,6 +748,12 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
assert(N->getValueType(0) == MVT::i32);
CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0)));
break;
case PPCISD::FSEL:
CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
Select(N->getOperand(0)),
Select(N->getOperand(1)),
Select(N->getOperand(2)));
break;
case ISD::ADD: {
MVT::ValueType Ty = N->getValueType(0);
if (Ty == MVT::i32) {

12
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -125,13 +125,13 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETUGE:
case ISD::SETGE:
return DAG.getTargetNode(PPC::FSEL, ResVT, LHS, TV, FV);
return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETULE:
case ISD::SETLE:
return DAG.getTargetNode(PPC::FSEL, ResVT,
return DAG.getNode(PPCISD::FSEL, ResVT,
DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
}
@ -139,19 +139,19 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
default: assert(0 && "Invalid FSEL condition"); abort();
case ISD::SETULT:
case ISD::SETLT:
return DAG.getTargetNode(PPC::FSEL, ResVT,
return DAG.getNode(PPCISD::FSEL, ResVT,
DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
case ISD::SETUGE:
case ISD::SETGE:
return DAG.getTargetNode(PPC::FSEL, ResVT,
return DAG.getNode(PPCISD::FSEL, ResVT,
DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
return DAG.getTargetNode(PPC::FSEL, ResVT,
return DAG.getNode(PPCISD::FSEL, ResVT,
DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
case ISD::SETULE:
case ISD::SETLE:
return DAG.getTargetNode(PPC::FSEL, ResVT,
return DAG.getNode(PPCISD::FSEL, ResVT,
DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
}
}

15
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -1,4 +1,4 @@
//===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Impl. --------*- C++ -*-===//
//===-- PPC32ISelLowering.h - PPC32 DAG Lowering Interface ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -16,8 +16,21 @@
#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
#include "llvm/Target/TargetLowering.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "PowerPC.h"
namespace llvm {
namespace PPCISD {
enum NodeType {
// Start the numbering where the builting ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
/// FSEL - Traditional three-operand fsel node.
///
FSEL,
};
}
class PPC32TargetLowering : public TargetLowering {
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
int ReturnAddrIndex; // FrameIndex for return slot.