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[Hexagon] Remove unused validSubtarget TSFlags

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Patch by Colin LeMahieu.

llvm-svn: 301952
This commit is contained in:
Krzysztof Parzyszek 2017-05-02 18:05:36 +00:00
parent 04e7e9f315
commit 0bbdb59c25
8 changed files with 4 additions and 58 deletions
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16
lib/Target/Hexagon/HexagonInstrFormats.td
View File

@ -7,16 +7,6 @@
//
//===----------------------------------------------------------------------===//
// Maintain list of valid subtargets for each instruction.
class SubTarget<bits<6> value> {
bits<6> Value = value;
}
def HasAnySubT : SubTarget<0x3f>; // 111111
def HasV5SubT : SubTarget<0x3e>; // 111110
def HasV55SubT : SubTarget<0x3c>; // 111100
def HasV60SubT : SubTarget<0x38>; // 111000
// Addressing modes for load/store instructions
class AddrModeType<bits<3> value> {
bits<3> Value = value;
@ -131,12 +121,6 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
bits<2> opExtentAlign = 0;
let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending.
// If an instruction is valid on a subtarget, set the corresponding
// bit from validSubTargets.
// By default, instruction is valid on all subtargets.
SubTarget validSubTargets = HasAnySubT;
let TSFlags{40-35} = validSubTargets.Value;
// Addressing mode for load/store instructions.
AddrModeType addrMode = NoAddrMode;
let TSFlags{43-41} = addrMode.Value;

8
lib/Target/Hexagon/HexagonInstrFormatsV60.td
View File

@ -15,8 +15,6 @@
// Instruction Classes Definitions +
//----------------------------------------------------------------------------//
let validSubTargets = HasV60SubT in
{
class CVI_VA_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = CVI_VA>
@ -184,10 +182,7 @@ class CVI_HIST_Resource<dag outs, dag ins, string asmstr,
InstrItinClass itin = CVI_HIST>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_HIST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
}
let validSubTargets = HasV60SubT in
{
class CVI_VA_Resource1<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = CVI_VA>
@ -205,6 +200,3 @@ class CVI_HIST_Resource1<dag outs, dag ins, string asmstr,
InstrItinClass itin = CVI_HIST>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_HIST>,
Requires<[HasV60T, UseHVX]>;
}

5
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -4139,11 +4139,6 @@ unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
return IS.getUnits();
}
unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const {
const uint64_t F = get(Opcode).TSFlags;
return (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask;
}
// Calculate size of the basic block without debug instructions.
unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
return nonDbgMICount(BB->instr_begin(), BB->instr_end());

1
lib/Target/Hexagon/HexagonInstrInfo.h
View File

@ -424,7 +424,6 @@ public:
unsigned getSize(const MachineInstr &MI) const;
uint64_t getType(const MachineInstr &MI) const;
unsigned getUnits(const MachineInstr &MI) const;
unsigned getValidSubTargets(const unsigned Opcode) const;
/// getInstrTimingClassLatency - Compute the instruction latency of a given
/// instruction using Timing Class information, if available.

8
lib/Target/Hexagon/HexagonPseudo.td
View File

@ -321,7 +321,7 @@ def LDriw_mod : LDInst<(outs ModRegs:$dst),
// Vector load
let Predicates = [HasV60T, UseHVX] in
let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
let mayLoad = 1, hasSideEffects = 0 in
class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = CVI_VM_LD,
IType type = TypeCVI_VM_LD>
@ -329,7 +329,7 @@ let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
// Vector store
let Predicates = [HasV60T, UseHVX] in
let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
let mayStore = 1, hasSideEffects = 0 in
class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = CVI_VM_ST,
IType type = TypeCVI_VM_ST>
@ -415,7 +415,7 @@ let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
// Vector load/store pseudos
let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
let isPseudo = 1, isCodeGenOnly = 1 in
class STrivv_template<RegisterClass RC>
: V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>;
@ -429,7 +429,7 @@ def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>,
Requires<[HasV60T,UseHVXDbl]>;
let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
let isPseudo = 1, isCodeGenOnly = 1 in
class LDrivv_template<RegisterClass RC>
: V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>;

4
lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
View File

@ -128,10 +128,6 @@ namespace HexagonII {
ExtentAlignPos = 33,
ExtentAlignMask = 0x3,
// Valid subtargets
validSubTargetPos = 35,
validSubTargetMask = 0x3f,
// Addressing mode for load/store instructions.
AddrModePos = 41,
AddrModeMask = 0x7,

19
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
View File

@ -384,25 +384,6 @@ unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
}
int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII,
MCInst const &MCI) {
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
HexagonII::SubTarget Target = static_cast<HexagonII::SubTarget>(
(F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask);
switch (Target) {
default:
return Hexagon::ArchV4;
case HexagonII::HasV5SubT:
return Hexagon::ArchV5;
case HexagonII::HasV55SubT:
return Hexagon::ArchV55;
case HexagonII::HasV60SubT:
return Hexagon::ArchV60;
}
}
/// Return the slots this instruction can execute out of
unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
MCSubtargetInfo const &STI,

1
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
View File

@ -152,7 +152,6 @@ MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);
MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII,
MCInst const &MCI);
int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI);
// Return the Hexagon ISA class for the insn.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);