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[RISCV] Add -mattr=+c command lines to add-before-shl.ll to prepare for D105417. NFC
This commit is contained in:
Craig Topper
parent
b0ba22b69f
commit
0bcc5397bd
@ -1,8 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs --riscv-no-aliases < %s \
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; RUN: | FileCheck -check-prefixes=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs --riscv-no-aliases < %s \
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; RUN: | FileCheck -check-prefixes=RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
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; RUN: < %s | FileCheck -check-prefixes=RV32C %s
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; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
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; RUN: < %s | FileCheck -check-prefixes=RV64C %s
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; These test that constant adds are not moved after shifts by DAGCombine,
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; if the constant is cheaper to materialise before it has been shifted.
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@ -13,14 +17,28 @@ define signext i32 @add_small_const(i32 signext %a) nounwind {
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: srai a0, a0, 24
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; RV32I-NEXT: ret
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; RV32I-NEXT: jalr zero, 0(ra)
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;
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; RV64I-LABEL: add_small_const:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 1
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: srai a0, a0, 56
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; RV64I-NEXT: ret
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; RV64I-NEXT: jalr zero, 0(ra)
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;
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; RV32C-LABEL: add_small_const:
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; RV32C: # %bb.0:
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; RV32C-NEXT: c.addi a0, 1
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; RV32C-NEXT: c.slli a0, 24
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; RV32C-NEXT: c.srai a0, 24
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; RV32C-NEXT: c.jr ra
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;
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; RV64C-LABEL: add_small_const:
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; RV64C: # %bb.0:
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; RV64C-NEXT: c.addi a0, 1
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; RV64C-NEXT: c.slli a0, 56
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; RV64C-NEXT: c.srai a0, 56
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; RV64C-NEXT: c.jr ra
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%1 = add i32 %a, 1
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%2 = shl i32 %1, 24
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%3 = ashr i32 %2, 24
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@ -34,7 +52,7 @@ define signext i32 @add_large_const(i32 signext %a) nounwind {
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; RV32I-NEXT: lui a1, 65520
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srai a0, a0, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: jalr zero, 0(ra)
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;
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; RV64I-LABEL: add_large_const:
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; RV64I: # %bb.0:
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@ -43,7 +61,24 @@ define signext i32 @add_large_const(i32 signext %a) nounwind {
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srai a0, a0, 48
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; RV64I-NEXT: ret
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; RV64I-NEXT: jalr zero, 0(ra)
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;
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; RV32C-LABEL: add_large_const:
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; RV32C: # %bb.0:
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; RV32C-NEXT: c.slli a0, 16
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; RV32C-NEXT: lui a1, 65520
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; RV32C-NEXT: c.add a0, a1
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; RV32C-NEXT: c.srai a0, 16
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; RV32C-NEXT: c.jr ra
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;
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; RV64C-LABEL: add_large_const:
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; RV64C: # %bb.0:
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; RV64C-NEXT: c.lui a1, 1
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; RV64C-NEXT: c.addiw a1, -1
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; RV64C-NEXT: c.add a0, a1
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; RV64C-NEXT: c.slli a0, 48
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; RV64C-NEXT: c.srai a0, 48
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; RV64C-NEXT: c.jr ra
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%1 = add i32 %a, 4095
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%2 = shl i32 %1, 16
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%3 = ashr i32 %2, 16
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@ -57,7 +92,7 @@ define signext i32 @add_huge_const(i32 signext %a) nounwind {
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; RV32I-NEXT: lui a1, 524272
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srai a0, a0, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: jalr zero, 0(ra)
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;
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; RV64I-LABEL: add_huge_const:
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; RV64I: # %bb.0:
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@ -66,7 +101,24 @@ define signext i32 @add_huge_const(i32 signext %a) nounwind {
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srai a0, a0, 48
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; RV64I-NEXT: ret
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; RV64I-NEXT: jalr zero, 0(ra)
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;
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; RV32C-LABEL: add_huge_const:
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; RV32C: # %bb.0:
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; RV32C-NEXT: c.slli a0, 16
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; RV32C-NEXT: lui a1, 524272
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; RV32C-NEXT: c.add a0, a1
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; RV32C-NEXT: c.srai a0, 16
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; RV32C-NEXT: c.jr ra
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;
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; RV64C-LABEL: add_huge_const:
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; RV64C: # %bb.0:
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; RV64C-NEXT: c.lui a1, 8
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; RV64C-NEXT: c.addiw a1, -1
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; RV64C-NEXT: c.add a0, a1
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; RV64C-NEXT: c.slli a0, 48
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; RV64C-NEXT: c.srai a0, 48
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; RV64C-NEXT: c.jr ra
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%1 = add i32 %a, 32767
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%2 = shl i32 %1, 16
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%3 = ashr i32 %2, 16
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@ -79,14 +131,28 @@ define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
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; RV32I-NEXT: addi a0, a0, 256
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srai a0, a0, 8
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; RV32I-NEXT: ret
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; RV32I-NEXT: jalr zero, 0(ra)
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;
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; RV64I-LABEL: add_non_machine_type:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 256
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srai a0, a0, 40
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; RV64I-NEXT: ret
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; RV64I-NEXT: jalr zero, 0(ra)
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;
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; RV32C-LABEL: add_non_machine_type:
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; RV32C: # %bb.0:
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; RV32C-NEXT: addi a0, a0, 256
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; RV32C-NEXT: c.slli a0, 20
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; RV32C-NEXT: c.srai a0, 8
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; RV32C-NEXT: c.jr ra
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;
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; RV64C-LABEL: add_non_machine_type:
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; RV64C: # %bb.0:
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; RV64C-NEXT: addi a0, a0, 256
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; RV64C-NEXT: c.slli a0, 52
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; RV64C-NEXT: c.srai a0, 40
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; RV64C-NEXT: c.jr ra
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%1 = add i24 %a, 256
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%2 = shl i24 %1, 12
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ret i24 %2
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@ -115,7 +181,7 @@ define i128 @add_wide_operand(i128 %a) nounwind {
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; RV32I-NEXT: sw a3, 8(a0)
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; RV32I-NEXT: sw a4, 4(a0)
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; RV32I-NEXT: sw a1, 12(a0)
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; RV32I-NEXT: ret
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; RV32I-NEXT: jalr zero, 0(ra)
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;
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; RV64I-LABEL: add_wide_operand:
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; RV64I: # %bb.0:
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@ -126,7 +192,42 @@ define i128 @add_wide_operand(i128 %a) nounwind {
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: slli a2, a2, 51
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; RV64I-NEXT: add a1, a1, a2
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; RV64I-NEXT: ret
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; RV64I-NEXT: jalr zero, 0(ra)
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;
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; RV32C-LABEL: add_wide_operand:
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; RV32C: # %bb.0:
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; RV32C-NEXT: c.lw a2, 0(a1)
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; RV32C-NEXT: c.lw a3, 4(a1)
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; RV32C-NEXT: lw a6, 12(a1)
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; RV32C-NEXT: c.lw a1, 8(a1)
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; RV32C-NEXT: srli a5, a2, 29
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; RV32C-NEXT: slli a4, a3, 3
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; RV32C-NEXT: c.or a4, a5
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; RV32C-NEXT: c.srli a3, 29
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; RV32C-NEXT: slli a5, a1, 3
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; RV32C-NEXT: c.or a3, a5
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; RV32C-NEXT: c.srli a1, 29
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; RV32C-NEXT: slli a5, a6, 3
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; RV32C-NEXT: c.or a1, a5
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; RV32C-NEXT: c.slli a2, 3
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; RV32C-NEXT: lui a5, 128
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; RV32C-NEXT: c.add a1, a5
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; RV32C-NEXT: c.sw a2, 0(a0)
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; RV32C-NEXT: c.sw a3, 8(a0)
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; RV32C-NEXT: c.sw a4, 4(a0)
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; RV32C-NEXT: c.sw a1, 12(a0)
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; RV32C-NEXT: c.jr ra
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;
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; RV64C-LABEL: add_wide_operand:
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; RV64C: # %bb.0:
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; RV64C-NEXT: srli a2, a0, 61
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; RV64C-NEXT: c.slli a1, 3
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; RV64C-NEXT: c.or a1, a2
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; RV64C-NEXT: c.slli a0, 3
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; RV64C-NEXT: c.li a2, 1
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; RV64C-NEXT: c.slli a2, 51
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; RV64C-NEXT: c.add a1, a2
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; RV64C-NEXT: c.jr ra
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%1 = add i128 %a, 5192296858534827628530496329220096
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%2 = shl i128 %1, 3
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ret i128 %2
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