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https://github.com/RPCS3/llvm-mirror.git
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[Hexagon] Handle lowering of SETCC via setCondCodeAction
It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
This commit is contained in:
Krzysztof Parzyszek
parent
5207077229
commit
0c375edf16
@ -2100,7 +2100,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::MUL, T, Custom);
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setOperationAction(ISD::MULHS, T, Custom);
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setOperationAction(ISD::MULHU, T, Custom);
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setOperationAction(ISD::SETCC, T, Custom);
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setOperationAction(ISD::BUILD_VECTOR, T, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
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@ -2116,6 +2115,14 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SHL, T, Custom);
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setOperationAction(ISD::SRL, T, Custom);
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}
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setCondCodeAction(ISD::SETNE, T, Expand);
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setCondCodeAction(ISD::SETLE, T, Expand);
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setCondCodeAction(ISD::SETGE, T, Expand);
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setCondCodeAction(ISD::SETLT, T, Expand);
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setCondCodeAction(ISD::SETULE, T, Expand);
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setCondCodeAction(ISD::SETUGE, T, Expand);
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setCondCodeAction(ISD::SETULT, T, Expand);
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}
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for (MVT T : LegalV) {
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@ -2303,6 +2310,8 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case HexagonISD::P2D: return "HexagonISD::P2D";
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case HexagonISD::V2Q: return "HexagonISD::V2Q";
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case HexagonISD::Q2V: return "HexagonISD::Q2V";
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case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
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case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
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case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
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case HexagonISD::OP_END: break;
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}
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@ -73,6 +73,8 @@ namespace HexagonISD {
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// [*] The equivalence is defined as "Q <=> (V != 0)",
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// where the != operation compares bytes.
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// Note: V != 0 is implemented as V >u 0.
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QTRUE,
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QFALSE,
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VZERO,
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TYPECAST, // No-op that's used to convert between different legal
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// types in a register.
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@ -324,6 +324,18 @@ HexagonTargetLowering::buildHvxVectorPred(ArrayRef<SDValue> Values,
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unsigned HwLen = Subtarget.getVectorLength();
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assert(VecLen <= HwLen || VecLen == 8*HwLen);
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SmallVector<SDValue,128> Bytes;
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bool AllT = true, AllF = true;
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auto IsTrue = [] (SDValue V) {
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if (const auto *N = dyn_cast<ConstantSDNode>(V.getNode()))
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return !N->isNullValue();
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return false;
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};
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auto IsFalse = [] (SDValue V) {
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if (const auto *N = dyn_cast<ConstantSDNode>(V.getNode()))
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return N->isNullValue();
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return false;
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};
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if (VecLen <= HwLen) {
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// In the hardware, each bit of a vector predicate corresponds to a byte
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@ -332,8 +344,11 @@ HexagonTargetLowering::buildHvxVectorPred(ArrayRef<SDValue> Values,
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assert(HwLen % VecLen == 0);
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unsigned BitBytes = HwLen / VecLen;
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for (SDValue V : Values) {
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AllT &= IsTrue(V);
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AllF &= IsFalse(V);
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SDValue Ext = !V.isUndef() ? DAG.getZExtOrTrunc(V, dl, MVT::i8)
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: DAG.getConstant(0, dl, MVT::i8);
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: DAG.getUNDEF(MVT::i8);
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for (unsigned B = 0; B != BitBytes; ++B)
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Bytes.push_back(Ext);
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}
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@ -349,8 +364,11 @@ HexagonTargetLowering::buildHvxVectorPred(ArrayRef<SDValue> Values,
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break;
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}
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SDValue F = Values[I+B];
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AllT &= IsTrue(F);
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AllF &= IsFalse(F);
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SDValue Ext = (B < 8) ? DAG.getZExtOrTrunc(F, dl, MVT::i8)
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: DAG.getConstant(0, dl, MVT::i8);
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: DAG.getUNDEF(MVT::i8);
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Bytes.push_back(Ext);
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// Verify that the rest of values in the group are the same as the
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// first.
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@ -359,6 +377,11 @@ HexagonTargetLowering::buildHvxVectorPred(ArrayRef<SDValue> Values,
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}
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}
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if (AllT)
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return DAG.getNode(HexagonISD::QTRUE, dl, VecTy);
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if (AllF)
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return DAG.getNode(HexagonISD::QFALSE, dl, VecTy);
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MVT ByteTy = MVT::getVectorVT(MVT::i8, HwLen);
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SDValue ByteVec = buildHvxVectorReg(Bytes, dl, ByteTy, DAG);
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return DAG.getNode(HexagonISD::V2Q, dl, VecTy, ByteVec);
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@ -1013,6 +1036,7 @@ HexagonTargetLowering::LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const {
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SDValue
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HexagonTargetLowering::LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
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MVT ResTy = ty(Op);
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MVT VecTy = ty(Op.getOperand(0));
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assert(VecTy == ty(Op.getOperand(1)));
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unsigned HwLen = Subtarget.getVectorLength();
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@ -1024,78 +1048,14 @@ HexagonTargetLowering::LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
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if (VecTy.getSizeInBits() == 16*HwLen) {
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VectorPair P0 = opSplit(Op.getOperand(0), dl, DAG);
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VectorPair P1 = opSplit(Op.getOperand(1), dl, DAG);
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MVT HalfTy = typeSplit(VecTy).first;
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MVT HalfTy = typeSplit(ResTy).first;
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SDValue V0 = DAG.getSetCC(dl, HalfTy, P0.first, P1.first, CC);
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SDValue V1 = DAG.getSetCC(dl, HalfTy, P0.second, P1.second, CC);
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, ty(Op), V1, V0);
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, V1, V0);
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}
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bool Negate = false, Swap = false;
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// HVX has instructions for SETEQ, SETGT, SETUGT. The other comparisons
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// can be arranged as operand-swapped/negated versions of these. Since
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// the generated code will have the original CC expressed as
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// (negate (swap-op NewCmp)),
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// the condition code for the NewCmp should be calculated from the original
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// CC by applying these operations in the reverse order.
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//
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// This could also be done through setCondCodeAction, but for negation it
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// uses a xor with a vector of -1s, which it obtains from BUILD_VECTOR.
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// That is far too expensive for what can be done with a single instruction.
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switch (CC) {
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case ISD::SETNE: // !eq
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case ISD::SETLE: // !gt
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case ISD::SETGE: // !lt
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case ISD::SETULE: // !ugt
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case ISD::SETUGE: // !ult
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CC = ISD::getSetCCInverse(CC, true);
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Negate = true;
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break;
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default:
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break;
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}
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switch (CC) {
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case ISD::SETLT: // swap gt
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case ISD::SETULT: // swap ugt
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CC = ISD::getSetCCSwappedOperands(CC);
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Swap = true;
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break;
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default:
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break;
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}
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assert(CC == ISD::SETEQ || CC == ISD::SETGT || CC == ISD::SETUGT);
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MVT ElemTy = VecTy.getVectorElementType();
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unsigned ElemWidth = ElemTy.getSizeInBits();
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assert(isPowerOf2_32(ElemWidth));
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auto getIdx = [] (unsigned Code) {
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static const unsigned Idx[] = { ISD::SETEQ, ISD::SETGT, ISD::SETUGT };
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for (unsigned I = 0, E = array_lengthof(Idx); I != E; ++I)
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if (Code == Idx[I])
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return I;
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llvm_unreachable("Unhandled CondCode");
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};
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static unsigned OpcTable[3][3] = {
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// SETEQ SETGT, SETUGT
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/* Byte */ { Hexagon::V6_veqb, Hexagon::V6_vgtb, Hexagon::V6_vgtub },
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/* Half */ { Hexagon::V6_veqh, Hexagon::V6_vgth, Hexagon::V6_vgtuh },
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/* Word */ { Hexagon::V6_veqw, Hexagon::V6_vgtw, Hexagon::V6_vgtuw }
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};
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unsigned CmpOpc = OpcTable[Log2_32(ElemWidth)-3][getIdx(CC)];
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MVT ResTy = ty(Op);
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SDValue OpL = Swap ? Op.getOperand(1) : Op.getOperand(0);
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SDValue OpR = Swap ? Op.getOperand(0) : Op.getOperand(1);
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SDValue CmpV = getInstr(CmpOpc, dl, ResTy, {OpL, OpR}, DAG);
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return Negate ? getInstr(Hexagon::V6_pred_not, dl, ResTy, {CmpV}, DAG)
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: CmpV;
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return SDValue();
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}
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SDValue
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@ -2993,8 +2993,14 @@ def Combinev: OutPatFrag<(ops node:$Rs, node:$Rt),
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def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
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def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
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def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
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def vzero: PatFrag<(ops), (HexagonVZERO)>;
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def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
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def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>;
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def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>;
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def vzero: PatFrag<(ops), (HexagonVZERO)>;
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def qtrue: PatFrag<(ops), (HexagonQTRUE)>;
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def qfalse: PatFrag<(ops), (HexagonQFALSE)>;
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def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>;
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def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>;
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def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>;
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@ -3074,6 +3080,13 @@ let Predicates = [UseHVX] in {
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def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
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(V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt),
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(V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
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def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt),
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(V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
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def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt),
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(V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
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def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>;
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def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;
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def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>;
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@ -3122,6 +3135,32 @@ let Predicates = [UseHVX] in {
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def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
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def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
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def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
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def: Pat<(qnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
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def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
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def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
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def: Pat<(VecQ8 (seteq HVI8:$Vs, HVI8:$Vt)),
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(V6_veqb HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecQ8 (setgt HVI8:$Vs, HVI8:$Vt)),
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(V6_vgtb HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecQ8 (setugt HVI8:$Vs, HVI8:$Vt)),
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(V6_vgtub HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecQ16 (seteq HVI16:$Vs, HVI16:$Vt)),
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(V6_veqh HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecQ16 (setgt HVI16:$Vs, HVI16:$Vt)),
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(V6_vgth HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecQ16 (setugt HVI16:$Vs, HVI16:$Vt)),
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(V6_vgtuh HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecQ32 (seteq HVI32:$Vs, HVI32:$Vt)),
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(V6_veqw HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecQ32 (setgt HVI32:$Vs, HVI32:$Vt)),
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(V6_vgtw HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecQ32 (setugt HVI32:$Vs, HVI32:$Vt)),
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(V6_vgtuw HvxVR:$Vs, HvxVR:$Vt)>;
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def: Pat<(VecI8 (trunc HWI16:$Vss)),
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(V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
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def: Pat<(VecI16 (trunc HWI32:$Vss)),
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@ -13,8 +13,7 @@ define <128 x i8> @test_00(<128 x i8> %v0, <128 x i8> %v1) #0 {
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; CHECK-LABEL: test_01:
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; CHECK: q[[Q010:[0-3]]] = vcmp.eq(v0.b,v1.b)
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; CHECK: q[[Q011:[0-9]]] = not(q[[Q010]])
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; CHECK: v0 = vmux(q[[Q011]],v0,v1)
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; CHECK: v0 = vmux(q[[Q010]],v1,v0)
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define <128 x i8> @test_01(<128 x i8> %v0, <128 x i8> %v1) #0 {
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%t0 = icmp ne <128 x i8> %v0, %v1
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%t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
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@ -32,8 +31,7 @@ define <128 x i8> @test_02(<128 x i8> %v0, <128 x i8> %v1) #0 {
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; CHECK-LABEL: test_03:
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; CHECK: q[[Q030:[0-3]]] = vcmp.gt(v0.b,v1.b)
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; CHECK: q[[Q031:[0-9]]] = not(q[[Q030]])
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; CHECK: v0 = vmux(q[[Q031]],v0,v1)
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; CHECK: v0 = vmux(q[[Q030]],v1,v0)
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define <128 x i8> @test_03(<128 x i8> %v0, <128 x i8> %v1) #0 {
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%t0 = icmp sle <128 x i8> %v0, %v1
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%t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
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@ -51,8 +49,7 @@ define <128 x i8> @test_04(<128 x i8> %v0, <128 x i8> %v1) #0 {
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; CHECK-LABEL: test_05:
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; CHECK: q[[Q050:[0-3]]] = vcmp.gt(v1.b,v0.b)
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; CHECK: q[[Q051:[0-9]]] = not(q[[Q050]])
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; CHECK: v0 = vmux(q[[Q051]],v0,v1)
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; CHECK: v0 = vmux(q[[Q050]],v1,v0)
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define <128 x i8> @test_05(<128 x i8> %v0, <128 x i8> %v1) #0 {
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%t0 = icmp sge <128 x i8> %v0, %v1
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%t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
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@ -70,8 +67,7 @@ define <128 x i8> @test_06(<128 x i8> %v0, <128 x i8> %v1) #0 {
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; CHECK-LABEL: test_07:
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; CHECK: q[[Q070:[0-3]]] = vcmp.gt(v0.ub,v1.ub)
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; CHECK: q[[Q071:[0-9]]] = not(q[[Q070]])
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; CHECK: v0 = vmux(q[[Q071]],v0,v1)
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; CHECK: v0 = vmux(q[[Q070]],v1,v0)
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define <128 x i8> @test_07(<128 x i8> %v0, <128 x i8> %v1) #0 {
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%t0 = icmp ule <128 x i8> %v0, %v1
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%t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
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@ -89,8 +85,7 @@ define <128 x i8> @test_08(<128 x i8> %v0, <128 x i8> %v1) #0 {
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; CHECK-LABEL: test_09:
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; CHECK: q[[Q090:[0-3]]] = vcmp.gt(v1.ub,v0.ub)
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; CHECK: q[[Q091:[0-9]]] = not(q[[Q090]])
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; CHECK: v0 = vmux(q[[Q091]],v0,v1)
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; CHECK: v0 = vmux(q[[Q090]],v1,v0)
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define <128 x i8> @test_09(<128 x i8> %v0, <128 x i8> %v1) #0 {
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%t0 = icmp uge <128 x i8> %v0, %v1
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%t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
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@ -110,8 +105,7 @@ define <64 x i16> @test_10(<64 x i16> %v0, <64 x i16> %v1) #0 {
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; CHECK-LABEL: test_11:
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; CHECK: q[[Q110:[0-3]]] = vcmp.eq(v0.h,v1.h)
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; CHECK: q[[Q111:[0-9]]] = not(q[[Q110]])
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; CHECK: v0 = vmux(q[[Q111]],v0,v1)
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; CHECK: v0 = vmux(q[[Q110]],v1,v0)
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define <64 x i16> @test_11(<64 x i16> %v0, <64 x i16> %v1) #0 {
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%t0 = icmp ne <64 x i16> %v0, %v1
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%t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
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@ -129,8 +123,7 @@ define <64 x i16> @test_12(<64 x i16> %v0, <64 x i16> %v1) #0 {
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; CHECK-LABEL: test_13:
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; CHECK: q[[Q130:[0-3]]] = vcmp.gt(v0.h,v1.h)
|
||||
; CHECK: q[[Q131:[0-9]]] = not(q[[Q130]])
|
||||
; CHECK: v0 = vmux(q[[Q031]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q130]],v1,v0)
|
||||
define <64 x i16> @test_13(<64 x i16> %v0, <64 x i16> %v1) #0 {
|
||||
%t0 = icmp sle <64 x i16> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
|
||||
@ -148,8 +141,7 @@ define <64 x i16> @test_14(<64 x i16> %v0, <64 x i16> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_15:
|
||||
; CHECK: q[[Q150:[0-3]]] = vcmp.gt(v1.h,v0.h)
|
||||
; CHECK: q[[Q151:[0-9]]] = not(q[[Q150]])
|
||||
; CHECK: v0 = vmux(q[[Q151]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q150]],v1,v0)
|
||||
define <64 x i16> @test_15(<64 x i16> %v0, <64 x i16> %v1) #0 {
|
||||
%t0 = icmp sge <64 x i16> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
|
||||
@ -167,8 +159,7 @@ define <64 x i16> @test_16(<64 x i16> %v0, <64 x i16> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_17:
|
||||
; CHECK: q[[Q170:[0-3]]] = vcmp.gt(v0.uh,v1.uh)
|
||||
; CHECK: q[[Q171:[0-9]]] = not(q[[Q170]])
|
||||
; CHECK: v0 = vmux(q[[Q171]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q170]],v1,v0)
|
||||
define <64 x i16> @test_17(<64 x i16> %v0, <64 x i16> %v1) #0 {
|
||||
%t0 = icmp ule <64 x i16> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
|
||||
@ -186,8 +177,7 @@ define <64 x i16> @test_18(<64 x i16> %v0, <64 x i16> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_19:
|
||||
; CHECK: q[[Q190:[0-3]]] = vcmp.gt(v1.uh,v0.uh)
|
||||
; CHECK: q[[Q191:[0-9]]] = not(q[[Q190]])
|
||||
; CHECK: v0 = vmux(q[[Q191]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q190]],v1,v0)
|
||||
define <64 x i16> @test_19(<64 x i16> %v0, <64 x i16> %v1) #0 {
|
||||
%t0 = icmp uge <64 x i16> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
|
||||
@ -207,8 +197,7 @@ define <32 x i32> @test_20(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_21:
|
||||
; CHECK: q[[Q210:[0-3]]] = vcmp.eq(v0.w,v1.w)
|
||||
; CHECK: q[[Q211:[0-9]]] = not(q[[Q210]])
|
||||
; CHECK: v0 = vmux(q[[Q211]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q210]],v1,v0)
|
||||
define <32 x i32> @test_21(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
%t0 = icmp ne <32 x i32> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
|
||||
@ -226,8 +215,7 @@ define <32 x i32> @test_22(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_23:
|
||||
; CHECK: q[[Q230:[0-3]]] = vcmp.gt(v0.w,v1.w)
|
||||
; CHECK: q[[Q231:[0-9]]] = not(q[[Q230]])
|
||||
; CHECK: v0 = vmux(q[[Q031]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q230]],v1,v0)
|
||||
define <32 x i32> @test_23(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
%t0 = icmp sle <32 x i32> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
|
||||
@ -245,8 +233,7 @@ define <32 x i32> @test_24(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_25:
|
||||
; CHECK: q[[Q250:[0-3]]] = vcmp.gt(v1.w,v0.w)
|
||||
; CHECK: q[[Q251:[0-9]]] = not(q[[Q250]])
|
||||
; CHECK: v0 = vmux(q[[Q251]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q250]],v1,v0)
|
||||
define <32 x i32> @test_25(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
%t0 = icmp sge <32 x i32> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
|
||||
@ -264,8 +251,7 @@ define <32 x i32> @test_26(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_27:
|
||||
; CHECK: q[[Q270:[0-3]]] = vcmp.gt(v0.uw,v1.uw)
|
||||
; CHECK: q[[Q271:[0-9]]] = not(q[[Q270]])
|
||||
; CHECK: v0 = vmux(q[[Q271]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q270]],v1,v0)
|
||||
define <32 x i32> @test_27(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
%t0 = icmp ule <32 x i32> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
|
||||
@ -283,8 +269,7 @@ define <32 x i32> @test_28(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_29:
|
||||
; CHECK: q[[Q290:[0-3]]] = vcmp.gt(v1.uw,v0.uw)
|
||||
; CHECK: q[[Q291:[0-9]]] = not(q[[Q290]])
|
||||
; CHECK: v0 = vmux(q[[Q291]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q290]],v1,v0)
|
||||
define <32 x i32> @test_29(<32 x i32> %v0, <32 x i32> %v1) #0 {
|
||||
%t0 = icmp uge <32 x i32> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
|
||||
|
||||
@ -13,8 +13,7 @@ define <64 x i8> @test_00(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_01:
|
||||
; CHECK: q[[Q010:[0-3]]] = vcmp.eq(v0.b,v1.b)
|
||||
; CHECK: q[[Q011:[0-9]]] = not(q[[Q010]])
|
||||
; CHECK: v0 = vmux(q[[Q011]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q010]],v1,v0)
|
||||
define <64 x i8> @test_01(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
%t0 = icmp ne <64 x i8> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
|
||||
@ -32,8 +31,7 @@ define <64 x i8> @test_02(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_03:
|
||||
; CHECK: q[[Q030:[0-3]]] = vcmp.gt(v0.b,v1.b)
|
||||
; CHECK: q[[Q031:[0-9]]] = not(q[[Q030]])
|
||||
; CHECK: v0 = vmux(q[[Q031]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q030]],v1,v0)
|
||||
define <64 x i8> @test_03(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
%t0 = icmp sle <64 x i8> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
|
||||
@ -51,8 +49,7 @@ define <64 x i8> @test_04(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_05:
|
||||
; CHECK: q[[Q050:[0-3]]] = vcmp.gt(v1.b,v0.b)
|
||||
; CHECK: q[[Q051:[0-9]]] = not(q[[Q050]])
|
||||
; CHECK: v0 = vmux(q[[Q051]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q050]],v1,v0)
|
||||
define <64 x i8> @test_05(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
%t0 = icmp sge <64 x i8> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
|
||||
@ -70,8 +67,7 @@ define <64 x i8> @test_06(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_07:
|
||||
; CHECK: q[[Q070:[0-3]]] = vcmp.gt(v0.ub,v1.ub)
|
||||
; CHECK: q[[Q071:[0-9]]] = not(q[[Q070]])
|
||||
; CHECK: v0 = vmux(q[[Q071]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q070]],v1,v0)
|
||||
define <64 x i8> @test_07(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
%t0 = icmp ule <64 x i8> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
|
||||
@ -89,8 +85,7 @@ define <64 x i8> @test_08(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_09:
|
||||
; CHECK: q[[Q090:[0-3]]] = vcmp.gt(v1.ub,v0.ub)
|
||||
; CHECK: q[[Q091:[0-9]]] = not(q[[Q090]])
|
||||
; CHECK: v0 = vmux(q[[Q091]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q090]],v1,v0)
|
||||
define <64 x i8> @test_09(<64 x i8> %v0, <64 x i8> %v1) #0 {
|
||||
%t0 = icmp uge <64 x i8> %v0, %v1
|
||||
%t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
|
||||
@ -110,8 +105,7 @@ define <32 x i16> @test_10(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_11:
|
||||
; CHECK: q[[Q110:[0-3]]] = vcmp.eq(v0.h,v1.h)
|
||||
; CHECK: q[[Q111:[0-9]]] = not(q[[Q110]])
|
||||
; CHECK: v0 = vmux(q[[Q111]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q110]],v1,v0)
|
||||
define <32 x i16> @test_11(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
%t0 = icmp ne <32 x i16> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
|
||||
@ -129,8 +123,7 @@ define <32 x i16> @test_12(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_13:
|
||||
; CHECK: q[[Q130:[0-3]]] = vcmp.gt(v0.h,v1.h)
|
||||
; CHECK: q[[Q131:[0-9]]] = not(q[[Q130]])
|
||||
; CHECK: v0 = vmux(q[[Q031]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q130]],v1,v0)
|
||||
define <32 x i16> @test_13(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
%t0 = icmp sle <32 x i16> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
|
||||
@ -148,8 +141,7 @@ define <32 x i16> @test_14(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_15:
|
||||
; CHECK: q[[Q150:[0-3]]] = vcmp.gt(v1.h,v0.h)
|
||||
; CHECK: q[[Q151:[0-9]]] = not(q[[Q150]])
|
||||
; CHECK: v0 = vmux(q[[Q151]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q150]],v1,v0)
|
||||
define <32 x i16> @test_15(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
%t0 = icmp sge <32 x i16> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
|
||||
@ -167,8 +159,7 @@ define <32 x i16> @test_16(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_17:
|
||||
; CHECK: q[[Q170:[0-3]]] = vcmp.gt(v0.uh,v1.uh)
|
||||
; CHECK: q[[Q171:[0-9]]] = not(q[[Q170]])
|
||||
; CHECK: v0 = vmux(q[[Q171]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q170]],v1,v0)
|
||||
define <32 x i16> @test_17(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
%t0 = icmp ule <32 x i16> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
|
||||
@ -186,8 +177,7 @@ define <32 x i16> @test_18(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_19:
|
||||
; CHECK: q[[Q190:[0-3]]] = vcmp.gt(v1.uh,v0.uh)
|
||||
; CHECK: q[[Q191:[0-9]]] = not(q[[Q190]])
|
||||
; CHECK: v0 = vmux(q[[Q191]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q190]],v1,v0)
|
||||
define <32 x i16> @test_19(<32 x i16> %v0, <32 x i16> %v1) #0 {
|
||||
%t0 = icmp uge <32 x i16> %v0, %v1
|
||||
%t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
|
||||
@ -207,8 +197,7 @@ define <16 x i32> @test_20(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_21:
|
||||
; CHECK: q[[Q210:[0-3]]] = vcmp.eq(v0.w,v1.w)
|
||||
; CHECK: q[[Q211:[0-9]]] = not(q[[Q210]])
|
||||
; CHECK: v0 = vmux(q[[Q211]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q210]],v1,v0)
|
||||
define <16 x i32> @test_21(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
%t0 = icmp ne <16 x i32> %v0, %v1
|
||||
%t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
|
||||
@ -226,8 +215,7 @@ define <16 x i32> @test_22(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_23:
|
||||
; CHECK: q[[Q230:[0-3]]] = vcmp.gt(v0.w,v1.w)
|
||||
; CHECK: q[[Q231:[0-9]]] = not(q[[Q230]])
|
||||
; CHECK: v0 = vmux(q[[Q031]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q230]],v1,v0)
|
||||
define <16 x i32> @test_23(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
%t0 = icmp sle <16 x i32> %v0, %v1
|
||||
%t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
|
||||
@ -245,8 +233,7 @@ define <16 x i32> @test_24(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_25:
|
||||
; CHECK: q[[Q250:[0-3]]] = vcmp.gt(v1.w,v0.w)
|
||||
; CHECK: q[[Q251:[0-9]]] = not(q[[Q250]])
|
||||
; CHECK: v0 = vmux(q[[Q251]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q250]],v1,v0)
|
||||
define <16 x i32> @test_25(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
%t0 = icmp sge <16 x i32> %v0, %v1
|
||||
%t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
|
||||
@ -264,8 +251,7 @@ define <16 x i32> @test_26(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_27:
|
||||
; CHECK: q[[Q270:[0-3]]] = vcmp.gt(v0.uw,v1.uw)
|
||||
; CHECK: q[[Q271:[0-9]]] = not(q[[Q270]])
|
||||
; CHECK: v0 = vmux(q[[Q271]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q270]],v1,v0)
|
||||
define <16 x i32> @test_27(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
%t0 = icmp ule <16 x i32> %v0, %v1
|
||||
%t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
|
||||
@ -283,8 +269,7 @@ define <16 x i32> @test_28(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
|
||||
; CHECK-LABEL: test_29:
|
||||
; CHECK: q[[Q290:[0-3]]] = vcmp.gt(v1.uw,v0.uw)
|
||||
; CHECK: q[[Q291:[0-9]]] = not(q[[Q290]])
|
||||
; CHECK: v0 = vmux(q[[Q291]],v0,v1)
|
||||
; CHECK: v0 = vmux(q[[Q290]],v1,v0)
|
||||
define <16 x i32> @test_29(<16 x i32> %v0, <16 x i32> %v1) #0 {
|
||||
%t0 = icmp uge <16 x i32> %v0, %v1
|
||||
%t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user