RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 03:23:01 +02:00
Code Issues Projects Releases Wiki Activity

Modify how the prologue encoded the "move" information for the FDE. GCC

Browse Source 
generates a sequence similar to this:

__Z4funci:
LFB2:
        mflr r0
LCFI0:
        stmw r30,-8(r1)
LCFI1:
        stw r0,8(r1)
LCFI2:
        stwu r1,-80(r1)
LCFI3:
        mr r30,r1
LCFI4:

where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:

Leh_func_begin1:
        mflr r0
        stw r31, 20(r1)
        stw r0, 8(r1)
Llabel1:
        stwu r1, -80(r1)
Llabel2:
        mr r31, r1

Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.

llvm-svn: 86729
This commit is contained in:
Bill Wendling 2009-11-10 22:14:04 +00:00
parent e70bec27b0
commit 1176227990
2 changed files with 70 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -1356,12 +1356,6 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned MaxAlign = MFI->getMaxAlignment();
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
}
// Adjust stack pointer: r1 += NegFrameSize.
// If there is a preferred stack alignment, align R1 now
if (!IsPPC64) {
@ -1431,12 +1425,18 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
.addReg(PPC::X0);
}
}
std::vector<MachineMove> &Moves = MMI->getFrameMoves();
// Add the "machine moves" for the instructions we generated above, but in
// reverse order.
if (needsFrameMoves) {
std::vector<MachineMove> &Moves = MMI->getFrameMoves();
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
// Show update of SP.
if (NegFrameSize) {
// Show update of SP.
MachineLocation SPDst(MachineLocation::VirtualFP);
MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
@ -1451,31 +1451,15 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
}
// Add callee saved registers to move list.
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
unsigned Reg = CSI[I].getReg();
if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
MachineLocation CSSrc(Reg);
Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
if (MustSaveLR) {
MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
}
MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
(IsPPC64 ? PPC::X1 : PPC::R1));
MachineLocation FPSrc(MachineLocation::VirtualFP);
Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
}
unsigned ReadyLabelId = 0;
// If there is a frame pointer, copy R1 into R31
if (HasFP) {
if (!IsPPC64) {
@ -1487,6 +1471,33 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
.addReg(PPC::X1)
.addReg(PPC::X1);
}
if (needsFrameMoves) {
ReadyLabelId = MMI->NextLabelID();
// Mark effective beginning of when frame pointer is ready.
BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
(IsPPC64 ? PPC::X1 : PPC::R1));
MachineLocation FPSrc(MachineLocation::VirtualFP);
Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
}
}
if (needsFrameMoves) {
unsigned LabelId = HasFP ? ReadyLabelId : FrameLabelId;
// Add callee saved registers to move list.
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
unsigned Reg = CSI[I].getReg();
if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
MachineLocation CSSrc(Reg);
Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
}
}
}

28
test/CodeGen/PowerPC/ppc-prologue.ll Normal file
View File

@ -0,0 +1,28 @@
; RUN: llc < %s -march=ppc32 -disable-fp-elim | FileCheck %s
define i32 @_Z4funci(i32 %a) ssp {
; CHECK: mflr r0
; CHECK-NEXT: stw r31, 20(r1)
; CHECK-NEXT: stw r0, 8(r1)
; CHECK-NEXT: stwu r1, -80(r1)
; CHECK-NEXT: Llabel1:
; CHECK-NEXT: mr r31, r1
; CHECK-NEXT: Llabel2:
entry:
%a_addr = alloca i32 ; <i32*> [#uses=2]
%retval = alloca i32 ; <i32*> [#uses=2]
%0 = alloca i32 ; <i32*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i32 %a, i32* %a_addr
%1 = call i32 @_Z3barPi(i32* %a_addr) ; <i32> [#uses=1]
store i32 %1, i32* %0, align 4
%2 = load i32* %0, align 4 ; <i32> [#uses=1]
store i32 %2, i32* %retval, align 4
br label %return
return: ; preds = %entry
%retval1 = load i32* %retval ; <i32> [#uses=1]
ret i32 %retval1
}
declare i32 @_Z3barPi(i32*)