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1176227990
generates a sequence similar to this: __Z4funci: LFB2: mflr r0 LCFI0: stmw r30,-8(r1) LCFI1: stw r0,8(r1) LCFI2: stwu r1,-80(r1) LCFI3: mr r30,r1 LCFI4: where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other things are. We generated something more like this: Leh_func_begin1: mflr r0 stw r31, 20(r1) stw r0, 8(r1) Llabel1: stwu r1, -80(r1) Llabel2: mr r31, r1 Note that we are missing the "mr" instruction. This patch makes it more like the GCC output. llvm-svn: 86729
29 lines
1007 B
LLVM
29 lines
1007 B
LLVM
; RUN: llc < %s -march=ppc32 -disable-fp-elim | FileCheck %s
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define i32 @_Z4funci(i32 %a) ssp {
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; CHECK: mflr r0
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; CHECK-NEXT: stw r31, 20(r1)
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; CHECK-NEXT: stw r0, 8(r1)
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; CHECK-NEXT: stwu r1, -80(r1)
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; CHECK-NEXT: Llabel1:
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; CHECK-NEXT: mr r31, r1
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; CHECK-NEXT: Llabel2:
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entry:
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%a_addr = alloca i32 ; <i32*> [#uses=2]
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%retval = alloca i32 ; <i32*> [#uses=2]
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%0 = alloca i32 ; <i32*> [#uses=2]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store i32 %a, i32* %a_addr
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%1 = call i32 @_Z3barPi(i32* %a_addr) ; <i32> [#uses=1]
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store i32 %1, i32* %0, align 4
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%2 = load i32* %0, align 4 ; <i32> [#uses=1]
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store i32 %2, i32* %retval, align 4
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br label %return
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return: ; preds = %entry
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%retval1 = load i32* %retval ; <i32> [#uses=1]
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ret i32 %retval1
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}
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declare i32 @_Z3barPi(i32*)
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