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MI-Sched: handle latency of in-order operations with the new machine model.
The per-operand machine model allows the target to define "unbuffered" processor resources. This change is a quick, cheap way to model stalls caused by the latency of operations that use such resources. This only applies when the processor's micro-op buffer size is non-zero (Out-of-Order). We can't precisely model in-order stalls during out-of-order execution, but this is an easy and effective heuristic. It benefits cortex-a9 scheduling when using the new machine model, which is not yet on by default. MI-Sched for armv7 was evaluated on Swift (and only not enabled because of a performance bug related to predication). However, we never evaluated Cortex-A9 performance on MI-Sched in its current form. This change adds MI-Sched functionality to reach performance goals on A9. The only remaining change is to allow MI-Sched to run as a PostRA pass. I evaluated performance using a set of options to estimate the performance impact once MI sched is default on armv7: -mcpu=cortex-a9 -disable-post-ra -misched-bench -scheditins=false For a simple saxpy loop I see a 1.7x speedup. Here are the llvm-testsuite results: (min run time over 2 runs, filtering tiny changes) Speedups: | Benchmarks/BenchmarkGame/recursive | 52.39% | | Benchmarks/VersaBench/beamformer | 20.80% | | Benchmarks/Misc/pi | 19.97% | | Benchmarks/Misc/mandel-2 | 19.95% | | SPEC/CFP2000/188.ammp | 18.72% | | Benchmarks/McCat/08-main/main | 18.58% | | Benchmarks/Misc-C++/Large/sphereflake | 18.46% | | Benchmarks/Olden/power | 17.11% | | Benchmarks/Misc-C++/mandel-text | 16.47% | | Benchmarks/Misc/oourafft | 15.94% | | Benchmarks/Misc/flops-7 | 14.99% | | Benchmarks/FreeBench/distray | 14.26% | | SPEC/CFP2006/470.lbm | 14.00% | | mediabench/mpeg2/mpeg2dec/mpeg2decode | 12.28% | | Benchmarks/SmallPT/smallpt | 10.36% | | Benchmarks/Misc-C++/Large/ray | 8.97% | | Benchmarks/Misc/fp-convert | 8.75% | | Benchmarks/Olden/perimeter | 7.10% | | Benchmarks/Bullet/bullet | 7.03% | | Benchmarks/Misc/mandel | 6.75% | | Benchmarks/Olden/voronoi | 6.26% | | Benchmarks/Misc/flops-8 | 5.77% | | Benchmarks/Misc/matmul_f64_4x4 | 5.19% | | Benchmarks/MiBench/security-rijndael | 5.15% | | Benchmarks/Misc/flops-6 | 5.10% | | Benchmarks/Olden/tsp | 4.46% | | Benchmarks/MiBench/consumer-lame | 4.28% | | Benchmarks/Misc/flops-5 | 4.27% | | Benchmarks/mafft/pairlocalalign | 4.19% | | Benchmarks/Misc/himenobmtxpa | 4.07% | | Benchmarks/Misc/lowercase | 4.06% | | SPEC/CFP2006/433.milc | 3.99% | | Benchmarks/tramp3d-v4 | 3.79% | | Benchmarks/FreeBench/pifft | 3.66% | | Benchmarks/Ptrdist/ks | 3.21% | | Benchmarks/Adobe-C++/loop_unroll | 3.12% | | SPEC/CINT2000/175.vpr | 3.12% | | Benchmarks/nbench | 2.98% | | SPEC/CFP2000/183.equake | 2.91% | | Benchmarks/Misc/perlin | 2.85% | | Benchmarks/Misc/flops-1 | 2.82% | | Benchmarks/Misc-C++-EH/spirit | 2.80% | | Benchmarks/Misc/flops-2 | 2.77% | | Benchmarks/NPB-serial/is | 2.42% | | Benchmarks/ASC_Sequoia/CrystalMk | 2.33% | | Benchmarks/BenchmarkGame/n-body | 2.28% | | Benchmarks/SciMark2-C/scimark2 | 2.27% | | Benchmarks/Olden/bh | 2.03% | | skidmarks10/skidmarks | 1.81% | | Benchmarks/Misc/flops | 1.72% | Slowdowns: | Benchmarks/llubenchmark/llu | -14.14% | | Benchmarks/Polybench/stencils/seidel-2d | -5.67% | | Benchmarks/Adobe-C++/functionobjects | -5.25% | | Benchmarks/Misc-C++/oopack_v1p8 | -5.00% | | Benchmarks/Shootout/hash | -2.35% | | Benchmarks/Prolangs-C++/ocean | -2.01% | | Benchmarks/Polybench/medley/floyd-warshall | -1.98% | | Polybench/linear-algebra/kernels/3mm | -1.95% | | Benchmarks/McCat/09-vor/vor | -1.68% | llvm-svn: 196516
This commit is contained in:
Andrew Trick
parent
24a9064bbd
commit
192311ab9a
@ -292,6 +292,7 @@ namespace llvm {
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bool isScheduleHigh : 1; // True if preferable to schedule high.
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bool isScheduleLow : 1; // True if preferable to schedule low.
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bool isCloned : 1; // True if this node has been cloned.
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bool isUnbuffered : 1; // Reads an unbuffered resource.
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Sched::Preference SchedulingPref; // Scheduling preference.
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private:
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@ -316,9 +317,10 @@ namespace llvm {
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isTwoAddress(false), isCommutable(false), hasPhysRegUses(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false),
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isAvailable(false), isScheduled(false), isScheduleHigh(false),
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isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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isScheduleLow(false), isCloned(false), isUnbuffered(false),
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SchedulingPref(Sched::None), isDepthCurrent(false),
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isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
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BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// SUnit - Construct an SUnit for post-regalloc scheduling to represent
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/// a MachineInstr.
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@ -330,9 +332,10 @@ namespace llvm {
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isTwoAddress(false), isCommutable(false), hasPhysRegUses(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false),
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isAvailable(false), isScheduled(false), isScheduleHigh(false),
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isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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isScheduleLow(false), isCloned(false), isUnbuffered(false),
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SchedulingPref(Sched::None), isDepthCurrent(false),
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isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
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BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// SUnit - Construct a placeholder SUnit.
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SUnit()
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@ -343,9 +346,10 @@ namespace llvm {
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isTwoAddress(false), isCommutable(false), hasPhysRegUses(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false),
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isAvailable(false), isScheduled(false), isScheduleHigh(false),
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isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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isScheduleLow(false), isCloned(false), isUnbuffered(false),
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SchedulingPref(Sched::None), isDepthCurrent(false),
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isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
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BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// \brief Boundary nodes are placeholders for the boundary of the
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/// scheduling region.
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@ -1330,7 +1330,7 @@ public:
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/// Represent the type of SchedCandidate found within a single queue.
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/// pickNodeBidirectional depends on these listed by decreasing priority.
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enum CandReason {
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NoCand, PhysRegCopy, RegExcess, RegCritical, Cluster, Weak, RegMax,
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NoCand, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, RegMax,
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ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
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TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
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@ -1583,6 +1583,10 @@ public:
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MaxExecutedResCount);
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}
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/// Get the difference between the given SUnit's ready time and the current
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/// cycle.
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unsigned getLatencyStallCycles(SUnit *SU);
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bool checkHazard(SUnit *SU);
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unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs);
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@ -1869,6 +1873,23 @@ void GenericScheduler::registerRoots() {
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}
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}
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/// Compute the stall cycles based on this SUnit's ready time. Heuristics treat
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/// these "soft stalls" differently than the hard stall cycles based on CPU
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/// resources and computed by checkHazard(). A fully in-order model
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/// (MicroOpBufferSize==0) will not make use of this since instructions are not
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/// available for scheduling until they are ready. However, a weaker in-order
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/// model may use this for heuristics. For example, if a processor has in-order
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/// behavior when reading certain resources, this may come into play.
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unsigned GenericScheduler::SchedBoundary::getLatencyStallCycles(SUnit *SU) {
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if (!SU->isUnbuffered)
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return 0;
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unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
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if (ReadyCycle > CurrCycle)
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return ReadyCycle - CurrCycle;
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return 0;
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}
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/// Does this SU have a hazard within the current instruction group.
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///
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/// The scheduler supports two modes of hazard recognition. The first is the
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@ -1948,9 +1969,9 @@ getOtherResourceCount(unsigned &OtherCritIdx) {
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/// inside and outside the zone.
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void GenericScheduler::SchedBoundary::setPolicy(CandPolicy &Policy,
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SchedBoundary &OtherZone) {
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// Now that potential stalls have been considered, apply preemptive heuristics
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// based on the the total latency and resources inside and outside this
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// zone.
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// Apply preemptive heuristics based on the the total latency and resources
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// inside and outside this zone. Potential stalls should be considered before
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// following this policy.
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// Compute remaining latency. We need this both to determine whether the
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// overall schedule has become latency-limited and whether the instructions
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@ -2141,7 +2162,11 @@ void GenericScheduler::SchedBoundary::bumpNode(SUnit *SU) {
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break;
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default:
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// We don't currently model the OOO reorder buffer, so consider all
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// scheduled MOps to be "retired".
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// scheduled MOps to be "retired". We do loosely model in-order resource
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// latency. If this instruction uses an in-order resource, account for any
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// likely stall cycles.
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if (SU->isUnbuffered && ReadyCycle > NextCycle)
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NextCycle = ReadyCycle;
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break;
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}
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RetiredMOps += IncMOps;
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@ -2514,6 +2539,11 @@ void GenericScheduler::tryCandidate(SchedCandidate &Cand,
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&& tryLatency(TryCand, Cand, Zone))
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return;
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// Prioritize instructions that read unbuffered resources by stall cycles.
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if (tryLess(Zone.getLatencyStallCycles(TryCand.SU),
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Zone.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
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return;
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// Keep clustered nodes together to encourage downstream peephole
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// optimizations which may reduce resource requirements.
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//
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@ -2577,6 +2607,7 @@ const char *GenericScheduler::getReasonStr(
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case PhysRegCopy: return "PREG-COPY";
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case RegExcess: return "REG-EXCESS";
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case RegCritical: return "REG-CRIT ";
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case Stall: return "STALL ";
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case Cluster: return "CLUSTER ";
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case Weak: return "WEAK ";
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case RegMax: return "REG-MAX ";
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@ -687,6 +687,22 @@ void ScheduleDAGInstrs::initSUnits() {
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// Assign the Latency field of SU using target-provided information.
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SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
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// If this SUnit uses an unbuffered resource, mark it as such.
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// These resources are used for in-order execution pipelines within an
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// out-of-order core and are identified by BufferSize=1. BufferSize=0 is
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// used for dispatch/issue groups and is not considered here.
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if (SchedModel.hasInstrSchedModel()) {
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const MCSchedClassDesc *SC = getSchedClass(SU);
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for (TargetSchedModel::ProcResIter
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PI = SchedModel.getWriteProcResBegin(SC),
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PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
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if (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize == 1) {
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SU->isUnbuffered = true;
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break;
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}
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}
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}
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}
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}
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@ -1905,7 +1905,7 @@ def A9UnitALU : ProcResource<2>;
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def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; }
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def A9UnitAGU : ProcResource<1>;
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def A9UnitLS : ProcResource<1>;
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def A9UnitFP : ProcResource<1> { let BufferSize = 0; }
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def A9UnitFP : ProcResource<1> { let BufferSize = 1; }
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def A9UnitB : ProcResource<1>;
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//===----------------------------------------------------------------------===//
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135
test/CodeGen/ARM/saxpy10-a9.ll
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135
test/CodeGen/ARM/saxpy10-a9.ll
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@ -0,0 +1,135 @@
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; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -disable-post-ra -misched-bench -scheditins=false | FileCheck %s
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;
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; Test MI-Sched suppory latency based stalls on in in-order pipeline
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; using the new machine model.
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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; Don't be too strict with the top of the schedule, but most of it
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; should be nicely pipelined.
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;
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; CHECK: saxpy10:
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; CHECK: vldr
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; CHECK: vldr
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; CHECK: vldr
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; CHECK: vldr
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; CHECK: vldr
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; CHECK: vldr
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; CHECK-NEXT: vmul
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vmul
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vmul
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vmul
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vmul
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vmul
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vmul
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vmul
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vldr
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vadd
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; CHECK-NEXT: vmov
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; CHECK-NEXT: bx
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;
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; This accumulates a sum rather than storing each result.
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define float @saxpy10(float* nocapture readonly %data1, float* nocapture readonly %data2, float %a) {
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entry:
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%0 = load float* %data1, align 4
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%mul = fmul float %0, %a
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%1 = load float* %data2, align 4
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%add = fadd float %mul, %1
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%add2 = fadd float %add, 0.000000e+00
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%arrayidx.1 = getelementptr inbounds float* %data1, i32 1
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%2 = load float* %arrayidx.1, align 4
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%mul.1 = fmul float %2, %a
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%arrayidx1.1 = getelementptr inbounds float* %data2, i32 1
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%3 = load float* %arrayidx1.1, align 4
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%add.1 = fadd float %mul.1, %3
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%add2.1 = fadd float %add2, %add.1
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%arrayidx.2 = getelementptr inbounds float* %data1, i32 2
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%4 = load float* %arrayidx.2, align 4
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%mul.2 = fmul float %4, %a
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%arrayidx1.2 = getelementptr inbounds float* %data2, i32 2
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%5 = load float* %arrayidx1.2, align 4
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%add.2 = fadd float %mul.2, %5
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%add2.2 = fadd float %add2.1, %add.2
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%arrayidx.3 = getelementptr inbounds float* %data1, i32 3
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%6 = load float* %arrayidx.3, align 4
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%mul.3 = fmul float %6, %a
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%arrayidx1.3 = getelementptr inbounds float* %data2, i32 3
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%7 = load float* %arrayidx1.3, align 4
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%add.3 = fadd float %mul.3, %7
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%add2.3 = fadd float %add2.2, %add.3
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%arrayidx.4 = getelementptr inbounds float* %data1, i32 4
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%8 = load float* %arrayidx.4, align 4
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%mul.4 = fmul float %8, %a
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%arrayidx1.4 = getelementptr inbounds float* %data2, i32 4
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%9 = load float* %arrayidx1.4, align 4
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%add.4 = fadd float %mul.4, %9
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%add2.4 = fadd float %add2.3, %add.4
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%arrayidx.5 = getelementptr inbounds float* %data1, i32 5
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%10 = load float* %arrayidx.5, align 4
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%mul.5 = fmul float %10, %a
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%arrayidx1.5 = getelementptr inbounds float* %data2, i32 5
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%11 = load float* %arrayidx1.5, align 4
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%add.5 = fadd float %mul.5, %11
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%add2.5 = fadd float %add2.4, %add.5
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%arrayidx.6 = getelementptr inbounds float* %data1, i32 6
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%12 = load float* %arrayidx.6, align 4
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%mul.6 = fmul float %12, %a
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%arrayidx1.6 = getelementptr inbounds float* %data2, i32 6
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%13 = load float* %arrayidx1.6, align 4
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%add.6 = fadd float %mul.6, %13
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%add2.6 = fadd float %add2.5, %add.6
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%arrayidx.7 = getelementptr inbounds float* %data1, i32 7
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%14 = load float* %arrayidx.7, align 4
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%mul.7 = fmul float %14, %a
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%arrayidx1.7 = getelementptr inbounds float* %data2, i32 7
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%15 = load float* %arrayidx1.7, align 4
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%add.7 = fadd float %mul.7, %15
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%add2.7 = fadd float %add2.6, %add.7
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%arrayidx.8 = getelementptr inbounds float* %data1, i32 8
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%16 = load float* %arrayidx.8, align 4
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%mul.8 = fmul float %16, %a
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%arrayidx1.8 = getelementptr inbounds float* %data2, i32 8
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%17 = load float* %arrayidx1.8, align 4
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%add.8 = fadd float %mul.8, %17
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%add2.8 = fadd float %add2.7, %add.8
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%arrayidx.9 = getelementptr inbounds float* %data1, i32 9
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%18 = load float* %arrayidx.9, align 4
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%mul.9 = fmul float %18, %a
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%arrayidx1.9 = getelementptr inbounds float* %data2, i32 9
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%19 = load float* %arrayidx1.9, align 4
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%add.9 = fadd float %mul.9, %19
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%add2.9 = fadd float %add2.8, %add.9
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ret float %add2.9
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}
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