[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:

The new behavior matches GNU objdump. A pair of angle brackets makes tests slightly easier.

`.foo:` is not unique and thus cannot be used in a `CHECK-LABEL:` directive.
Without `-LABEL`, the CHECK line can match the `Disassembly of section`
line and causes the next `CHECK-NEXT:` to fail.

```
Disassembly of section .foo:

0000000000001634 .foo:
```

Bdragon: <> has metalinguistic connotation. it just "feels right"

Reviewed By: rupprecht

Differential Revision: https://reviews.llvm.org/D75713

test/CodeGen/AArch64/arm64-simplest-elf.ll

@@ -14,5 +14,5 @@ define void @foo() nounwind {
 ; CHECK-ELF: file format elf64-aarch64
 
 ; CHECK-ELF: Disassembly of section .text
-; CHECK-ELF-LABEL: foo:
+; CHECK-ELF-LABEL: <foo>:
 ; CHECK-ELF:    ret

test/CodeGen/AArch64/callbr-asm-obj-file.ll

@@ -6,11 +6,11 @@
 
 @l = common hidden local_unnamed_addr global i32 0, align 4
 
-; CHECK-LABEL: test1:
+; CHECK-LABEL: <test1>:
-; CHECK-LABEL: $d.1:
+; CHECK-LABEL: <$d.1>:
-; CHECK-LABEL: $x.2:
+; CHECK-LABEL: <$x.2>:
 ; CHECK-NEXT:    b #16 <$x.4+0x4>
-; CHECK-LABEL: $x.4:
+; CHECK-LABEL: <$x.4>:
 ; CHECK-NEXT:    b #4 <$x.4+0x4>
 ; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ldr x30, [sp], #16
@@ -40,10 +40,10 @@ declare dso_local i32 @g(...) local_unnamed_addr
 
 declare dso_local i32 @i(...) local_unnamed_addr
 
-; CHECK-LABEL: test2:
+; CHECK-LABEL: <test2>:
 ; CHECK:         bl #0 <test2+0x10>
-; CHECK-LABEL: $d.5:
+; CHECK-LABEL: <$d.5>:
-; CHECK-LABEL: $x.6:
+; CHECK-LABEL: <$x.6>:
 ; CHECK-NEXT:    b #16 <$x.8+0x4>
 define hidden i32 @test2() local_unnamed_addr {
   %1 = load i32, i32* @l, align 4
@@ -70,11 +70,11 @@ define hidden i32 @test2() local_unnamed_addr {
   ret i32 undef
 }
 
-; CHECK-LABEL: test3:
+; CHECK-LABEL: <test3>:
-; CHECK-LABEL: $d.9:
+; CHECK-LABEL: <$d.9>:
-; CHECK-LABEL: $x.10:
+; CHECK-LABEL: <$x.10>:
 ; CHECK-NEXT:    b #-20 <test3+0x18>
-; CHECK-LABEL: $x.12:
+; CHECK-LABEL: <$x.12>:
 ; CHECK-NEXT:    b #4 <$x.12+0x4>
 ; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ldr x30, [sp], #16

test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll

@@ -4,7 +4,7 @@
 ; demonstrate the bug. Going the asm->obj route does not show the issue.
 ; RUN: llc -mtriple=aarch64   < %s -filetype=obj | llvm-objdump -arch=aarch64 -d - | FileCheck %s
 
-; CHECK-LABEL: foo:
+; CHECK-LABEL: <foo>:
 ; CHECK:       a0 79 95 d2   mov x0, #43981
 ; CHECK:       c0 03 5f d6   ret
 define i32 @foo() nounwind {
@@ -12,11 +12,11 @@ entry:
   %0 = tail call i32 asm sideeffect "ldr $0,=0xabcd", "=r"() nounwind
   ret i32 %0
 }
-; CHECK-LABEL: bar:
+; CHECK-LABEL: <bar>:
 ; CHECK:        40 00 00 58                                      ldr    x0, #8
 ; CHECK:        c0 03 5f d6                                      ret
 ; Make sure the constant pool entry comes after the return
-; CHECK-LABEL:        $d.1:
+; CHECK-LABEL:        <$d.1>:
 define i32 @bar() nounwind {
 entry:
   %0 = tail call i32 asm sideeffect "ldr $0,=0x10001", "=r"() nounwind

test/CodeGen/AArch64/space.ll

@@ -10,7 +10,7 @@ entry:
 }
 ; CHECK: // SPACE
 ; CHECK-NEXT: ret
-; DUMP-LABEL: f:
+; DUMP-LABEL: <f>:
 ; DUMP-NEXT: ret
 
 declare dso_local i64 @llvm.aarch64.space(i32, i64) local_unnamed_addr #0

test/CodeGen/AMDGPU/nop-data.ll

@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - -mcpu=fiji | FileCheck %s
 
-; CHECK: kernel0:
+; CHECK: <kernel0>:
 ; CHECK-NEXT: s_endpgm
 define amdgpu_kernel void @kernel0() align 256 {
 entry:
@@ -79,7 +79,7 @@ entry:
 ; CHECK-NEXT: s_nop 0  // 0000000001FC: BF800000
 
 ; CHECK-EMPTY:
-; CHECK-NEXT: kernel1:
+; CHECK-NEXT: <kernel1>:
 ; CHECK-NEXT: s_endpgm
 define amdgpu_kernel void @kernel1(i32 addrspace(1)* addrspace(4)* %ptr.out) align 256 {
 entry:

test/CodeGen/AMDGPU/s_code_end.ll

@@ -4,7 +4,7 @@
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10NOEND,GFX10NOEND-ASM %s
 ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump -arch=amdgcn -mcpu=gfx1010 -disassemble - | FileCheck -check-prefixes=GCN,GCN-OBJ,GFX10NOEND,GFX10NOEND-OBJ %s
 
-; GCN:            a_kernel1:
+; GCN:            a_kernel1{{>?}}:
 ; GCN:                    s_endpgm
 ; GCN-ASM:        [[END_LABEL1:\.Lfunc_end.*]]:
 ; GCN-ASM-NEXT:           .size   a_kernel1, [[END_LABEL1]]-a_kernel1
@@ -15,7 +15,7 @@ define amdgpu_kernel void @a_kernel1() {
   ret void
 }
 
-; GCN:            a_kernel2:
+; GCN:            a_kernel2{{>?}}:
 ; GCN:                    s_endpgm
 ; GCN-ASM:        [[END_LABEL2:\.Lfunc_end.*]]:
 ; GCN-ASM-NEXT:           .size   a_kernel2, [[END_LABEL2]]-a_kernel2
@@ -30,7 +30,7 @@ define amdgpu_kernel void @a_kernel2() {
 ; GCN-ASM-NEXT:           .p2align        2
 ; GCN-ASM-NEXT:           .type   a_function,@function
 
-; GCN-NEXT:       a_function:
+; GCN-NEXT:       a_function{{>?}}:
 ; GCN:                    s_setpc_b64
 ; GCN-ASM-NEXT:   [[END_LABEL3:\.Lfunc_end.*]]:
 ; GCN-ASM-NEXT:           .size   a_function, [[END_LABEL3]]-a_function

test/CodeGen/ARM/Windows/trivial-gnu-object.ll

@@ -4,7 +4,7 @@
 define void @foo() {
 ; CHECK: file format coff-arm
 
-; CHECK-LABEL: foo:
+; CHECK-LABEL: <foo>:
 ; CHECK: bx lr
   ret void
 }

test/CodeGen/ARM/inlineasm-ldr-pseudo.ll

@@ -5,7 +5,7 @@
 ; demonstrate the bug. Going the asm->obj route does not show the issue.
 ; RUN: llc -mtriple=arm-none-linux   < %s -filetype=obj | llvm-objdump -d - | FileCheck %s
 ; RUN: llc -mtriple=arm-apple-darwin < %s -filetype=obj | llvm-objdump -d - | FileCheck %s
-; CHECK-LABEL: foo:
+; CHECK-LABEL: <{{_?}}foo>:
 ; CHECK: 0:       00 00 9f e5                                     ldr     r0, [pc]
 ; CHECK: 4:       0e f0 a0 e1                                     mov     pc, lr
 ; Make sure the constant pool entry comes after the return

test/CodeGen/ARM/struct_byval_arm_t1_t2.ll

@@ -53,11 +53,11 @@ declare void @use_M(%struct.M* byval)
 %struct.N = type  { [ 128 x i8 ] }  ; 128 bytes
 declare void @use_N(%struct.N* byval)
 
-;ARM-LABEL:    test_A_1:
+;ARM-LABEL:    <test_A_1>:
-;THUMB2-LABEL: test_A_1:
+;THUMB2-LABEL: <test_A_1>:
-;NO_NEON-LABEL:test_A_1:
+;NO_NEON-LABEL:<test_A_1>:
-;THUMB1-LABEL: test_A_1:
+;THUMB1-LABEL: <test_A_1>:
-;T1POST-LABEL: test_A_1:
+;T1POST-LABEL: <test_A_1>:
   define void @test_A_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 
@@ -74,11 +74,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_A(%struct.A* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_A_2:
+;ARM-LABEL:    <test_A_2>:
-;THUMB2-LABEL: test_A_2:
+;THUMB2-LABEL: <test_A_2>:
-;NO_NEON-LABEL:test_A_2:
+;NO_NEON-LABEL:<test_A_2>:
-;THUMB1-LABEL: test_A_2:
+;THUMB1-LABEL: <test_A_2>:
-;T1POST-LABEL: test_A_2:
+;T1POST-LABEL: <test_A_2>:
   define void @test_A_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 
@@ -95,11 +95,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_A(%struct.A* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_A_4:
+;ARM-LABEL:    <test_A_4>:
-;THUMB2-LABEL: test_A_4:
+;THUMB2-LABEL: <test_A_4>:
-;NO_NEON-LABEL:test_A_4:
+;NO_NEON-LABEL:<test_A_4>:
-;THUMB1-LABEL: test_A_4:
+;THUMB1-LABEL: <test_A_4>:
-;T1POST-LABEL: test_A_4:
+;T1POST-LABEL: <test_A_4>:
   define void @test_A_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 
@@ -116,11 +116,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_A(%struct.A* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_A_8:
+;ARM-LABEL:    <test_A_8>:
-;THUMB2-LABEL: test_A_8:
+;THUMB2-LABEL: <test_A_8>:
-;NO_NEON-LABEL:test_A_8:
+;NO_NEON-LABEL:<test_A_8>:
-;THUMB1-LABEL: test_A_8:
+;THUMB1-LABEL: <test_A_8>:
-;T1POST-LABEL: test_A_8:
+;T1POST-LABEL: <test_A_8>:
   define void @test_A_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 
@@ -138,11 +138,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_A(%struct.A* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_A_16:
+;ARM-LABEL:    <test_A_16>:
-;THUMB2-LABEL: test_A_16:
+;THUMB2-LABEL: <test_A_16>:
-;NO_NEON-LABEL:test_A_16:
+;NO_NEON-LABEL:<test_A_16>:
-;THUMB1-LABEL: test_A_16:
+;THUMB1-LABEL: <test_A_16>:
-;T1POST-LABEL: test_A_16:
+;T1POST-LABEL: <test_A_16>:
   define void @test_A_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -162,11 +162,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_A(%struct.A* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_B_1:
+;ARM-LABEL:    <test_B_1>:
-;THUMB2-LABEL: test_B_1:
+;THUMB2-LABEL: <test_B_1>:
-;NO_NEON-LABEL:test_B_1:
+;NO_NEON-LABEL:<test_B_1>:
-;THUMB1-LABEL: test_B_1:
+;THUMB1-LABEL: <test_B_1>:
-;T1POST-LABEL: test_B_1:
+;T1POST-LABEL: <test_B_1>:
   define void @test_B_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 
@@ -183,11 +183,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_B(%struct.B* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_B_2:
+;ARM-LABEL:    <test_B_2>:
-;THUMB2-LABEL: test_B_2:
+;THUMB2-LABEL: <test_B_2>:
-;NO_NEON-LABEL:test_B_2:
+;NO_NEON-LABEL:<test_B_2>:
-;THUMB1-LABEL: test_B_2:
+;THUMB1-LABEL: <test_B_2>:
-;T1POST-LABEL: test_B_2:
+;T1POST-LABEL: <test_B_2>:
   define void @test_B_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -208,11 +208,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_B(%struct.B* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_B_4:
+;ARM-LABEL:    <test_B_4>:
-;THUMB2-LABEL: test_B_4:
+;THUMB2-LABEL: <test_B_4>:
-;NO_NEON-LABEL:test_B_4:
+;NO_NEON-LABEL:<test_B_4>:
-;THUMB1-LABEL: test_B_4:
+;THUMB1-LABEL: <test_B_4>:
-;T1POST-LABEL: test_B_4:
+;T1POST-LABEL: <test_B_4>:
   define void @test_B_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -233,11 +233,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_B(%struct.B* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_B_8:
+;ARM-LABEL:    <test_B_8>:
-;THUMB2-LABEL: test_B_8:
+;THUMB2-LABEL: <test_B_8>:
-;NO_NEON-LABEL:test_B_8:
+;NO_NEON-LABEL:<test_B_8>:
-;THUMB1-LABEL: test_B_8:
+;THUMB1-LABEL: <test_B_8>:
-;T1POST-LABEL: test_B_8:
+;T1POST-LABEL: <test_B_8>:
   define void @test_B_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -259,11 +259,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_B(%struct.B* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_B_16:
+;ARM-LABEL:    <test_B_16>:
-;THUMB2-LABEL: test_B_16:
+;THUMB2-LABEL: <test_B_16>:
-;NO_NEON-LABEL:test_B_16:
+;NO_NEON-LABEL:<test_B_16>:
-;THUMB1-LABEL: test_B_16:
+;THUMB1-LABEL: <test_B_16>:
-;T1POST-LABEL: test_B_16:
+;T1POST-LABEL: <test_B_16>:
   define void @test_B_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -285,11 +285,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_B(%struct.B* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_C_1:
+;ARM-LABEL:    <test_C_1>:
-;THUMB2-LABEL: test_C_1:
+;THUMB2-LABEL: <test_C_1>:
-;NO_NEON-LABEL:test_C_1:
+;NO_NEON-LABEL:<test_C_1>:
-;THUMB1-LABEL: test_C_1:
+;THUMB1-LABEL: <test_C_1>:
-;T1POST-LABEL: test_C_1:
+;T1POST-LABEL: <test_C_1>:
   define void @test_C_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 
@@ -306,11 +306,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_C(%struct.C* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_C_2:
+;ARM-LABEL:    <test_C_2>:
-;THUMB2-LABEL: test_C_2:
+;THUMB2-LABEL: <test_C_2>:
-;NO_NEON-LABEL:test_C_2:
+;NO_NEON-LABEL:<test_C_2>:
-;THUMB1-LABEL: test_C_2:
+;THUMB1-LABEL: <test_C_2>:
-;T1POST-LABEL: test_C_2:
+;T1POST-LABEL: <test_C_2>:
   define void @test_C_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -331,11 +331,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_C(%struct.C* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_C_4:
+;ARM-LABEL:    <test_C_4>:
-;THUMB2-LABEL: test_C_4:
+;THUMB2-LABEL: <test_C_4>:
-;NO_NEON-LABEL:test_C_4:
+;NO_NEON-LABEL:<test_C_4>:
-;THUMB1-LABEL: test_C_4:
+;THUMB1-LABEL: <test_C_4>:
-;T1POST-LABEL: test_C_4:
+;T1POST-LABEL: <test_C_4>:
   define void @test_C_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -357,11 +357,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_C(%struct.C* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_C_8:
+;ARM-LABEL:    <test_C_8>:
-;THUMB2-LABEL: test_C_8:
+;THUMB2-LABEL: <test_C_8>:
-;NO_NEON-LABEL:test_C_8:
+;NO_NEON-LABEL:<test_C_8>:
-;THUMB1-LABEL: test_C_8:
+;THUMB1-LABEL: <test_C_8>:
-;T1POST-LABEL: test_C_8:
+;T1POST-LABEL: <test_C_8>:
   define void @test_C_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -384,11 +384,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_C(%struct.C* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_C_16:
+;ARM-LABEL:    <test_C_16>:
-;THUMB2-LABEL: test_C_16:
+;THUMB2-LABEL: <test_C_16>:
-;NO_NEON-LABEL:test_C_16:
+;NO_NEON-LABEL:<test_C_16>:
-;THUMB1-LABEL: test_C_16:
+;THUMB1-LABEL: <test_C_16>:
-;T1POST-LABEL: test_C_16:
+;T1POST-LABEL: <test_C_16>:
   define void @test_C_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
@@ -411,11 +411,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_C(%struct.C* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_D_1:
+;ARM-LABEL:    <test_D_1>:
-;THUMB2-LABEL: test_D_1:
+;THUMB2-LABEL: <test_D_1>:
-;NO_NEON-LABEL:test_D_1:
+;NO_NEON-LABEL:<test_D_1>:
-;THUMB1-LABEL: test_D_1:
+;THUMB1-LABEL: <test_D_1>:
-;T1POST-LABEL: test_D_1:
+;T1POST-LABEL: <test_D_1>:
   define void @test_D_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 ;ARM:         bne
@@ -436,11 +436,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_D(%struct.D* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_D_2:
+;ARM-LABEL:    <test_D_2>:
-;THUMB2-LABEL: test_D_2:
+;THUMB2-LABEL: <test_D_2>:
-;NO_NEON-LABEL:test_D_2:
+;NO_NEON-LABEL:<test_D_2>:
-;THUMB1-LABEL: test_D_2:
+;THUMB1-LABEL: <test_D_2>:
-;T1POST-LABEL: test_D_2:
+;T1POST-LABEL: <test_D_2>:
   define void @test_D_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 ;ARM:         bne
@@ -461,11 +461,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_D(%struct.D* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_D_4:
+;ARM-LABEL:    <test_D_4>:
-;THUMB2-LABEL: test_D_4:
+;THUMB2-LABEL: <test_D_4>:
-;NO_NEON-LABEL:test_D_4:
+;NO_NEON-LABEL:<test_D_4>:
-;THUMB1-LABEL: test_D_4:
+;THUMB1-LABEL: <test_D_4>:
-;T1POST-LABEL: test_D_4:
+;T1POST-LABEL: <test_D_4>:
   define void @test_D_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 ;ARM:         bne
@@ -486,11 +486,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_D(%struct.D* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_D_8:
+;ARM-LABEL:    <test_D_8>:
-;THUMB2-LABEL: test_D_8:
+;THUMB2-LABEL: <test_D_8>:
-;NO_NEON-LABEL:test_D_8:
+;NO_NEON-LABEL:<test_D_8>:
-;THUMB1-LABEL: test_D_8:
+;THUMB1-LABEL: <test_D_8>:
-;T1POST-LABEL: test_D_8:
+;T1POST-LABEL: <test_D_8>:
   define void @test_D_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -512,11 +512,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_D(%struct.D* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_D_16:
+;ARM-LABEL:    <test_D_16>:
-;THUMB2-LABEL: test_D_16:
+;THUMB2-LABEL: <test_D_16>:
-;NO_NEON-LABEL:test_D_16:
+;NO_NEON-LABEL:<test_D_16>:
-;THUMB1-LABEL: test_D_16:
+;THUMB1-LABEL: <test_D_16>:
-;T1POST-LABEL: test_D_16:
+;T1POST-LABEL: <test_D_16>:
   define void @test_D_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -538,11 +538,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_D(%struct.D* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_E_1:
+;ARM-LABEL:    <test_E_1>:
-;THUMB2-LABEL: test_E_1:
+;THUMB2-LABEL: <test_E_1>:
-;NO_NEON-LABEL:test_E_1:
+;NO_NEON-LABEL:<test_E_1>:
-;THUMB1-LABEL: test_E_1:
+;THUMB1-LABEL: <test_E_1>:
-;T1POST-LABEL: test_E_1:
+;T1POST-LABEL: <test_E_1>:
   define void @test_E_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 ;ARM:         bne
@@ -563,11 +563,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_E(%struct.E* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_E_2:
+;ARM-LABEL:    <test_E_2>:
-;THUMB2-LABEL: test_E_2:
+;THUMB2-LABEL: <test_E_2>:
-;NO_NEON-LABEL:test_E_2:
+;NO_NEON-LABEL:<test_E_2>:
-;THUMB1-LABEL: test_E_2:
+;THUMB1-LABEL: <test_E_2>:
-;T1POST-LABEL: test_E_2:
+;T1POST-LABEL: <test_E_2>:
   define void @test_E_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 ;ARM:         bne
@@ -592,11 +592,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_E(%struct.E* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_E_4:
+;ARM-LABEL:    <test_E_4>:
-;THUMB2-LABEL: test_E_4:
+;THUMB2-LABEL: <test_E_4>:
-;NO_NEON-LABEL:test_E_4:
+;NO_NEON-LABEL:<test_E_4>:
-;THUMB1-LABEL: test_E_4:
+;THUMB1-LABEL: <test_E_4>:
-;T1POST-LABEL: test_E_4:
+;T1POST-LABEL: <test_E_4>:
   define void @test_E_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 ;ARM:         bne
@@ -621,11 +621,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_E(%struct.E* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_E_8:
+;ARM-LABEL:    <test_E_8>:
-;THUMB2-LABEL: test_E_8:
+;THUMB2-LABEL: <test_E_8>:
-;NO_NEON-LABEL:test_E_8:
+;NO_NEON-LABEL:<test_E_8>:
-;THUMB1-LABEL: test_E_8:
+;THUMB1-LABEL: <test_E_8>:
-;T1POST-LABEL: test_E_8:
+;T1POST-LABEL: <test_E_8>:
   define void @test_E_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -651,11 +651,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_E(%struct.E* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_E_16:
+;ARM-LABEL:    <test_E_16>:
-;THUMB2-LABEL: test_E_16:
+;THUMB2-LABEL: <test_E_16>:
-;NO_NEON-LABEL:test_E_16:
+;NO_NEON-LABEL:<test_E_16>:
-;THUMB1-LABEL: test_E_16:
+;THUMB1-LABEL: <test_E_16>:
-;T1POST-LABEL: test_E_16:
+;T1POST-LABEL: <test_E_16>:
   define void @test_E_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -681,11 +681,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_E(%struct.E* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_F_1:
+;ARM-LABEL:    <test_F_1>:
-;THUMB2-LABEL: test_F_1:
+;THUMB2-LABEL: <test_F_1>:
-;NO_NEON-LABEL:test_F_1:
+;NO_NEON-LABEL:<test_F_1>:
-;THUMB1-LABEL: test_F_1:
+;THUMB1-LABEL: <test_F_1>:
-;T1POST-LABEL: test_F_1:
+;T1POST-LABEL: <test_F_1>:
   define void @test_F_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 ;ARM:         bne
@@ -706,11 +706,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_F(%struct.F* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_F_2:
+;ARM-LABEL:    <test_F_2>:
-;THUMB2-LABEL: test_F_2:
+;THUMB2-LABEL: <test_F_2>:
-;NO_NEON-LABEL:test_F_2:
+;NO_NEON-LABEL:<test_F_2>:
-;THUMB1-LABEL: test_F_2:
+;THUMB1-LABEL: <test_F_2>:
-;T1POST-LABEL: test_F_2:
+;T1POST-LABEL: <test_F_2>:
   define void @test_F_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 ;ARM:         bne
@@ -735,11 +735,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_F(%struct.F* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_F_4:
+;ARM-LABEL:    <test_F_4>:
-;THUMB2-LABEL: test_F_4:
+;THUMB2-LABEL: <test_F_4>:
-;NO_NEON-LABEL:test_F_4:
+;NO_NEON-LABEL:<test_F_4>:
-;THUMB1-LABEL: test_F_4:
+;THUMB1-LABEL: <test_F_4>:
-;T1POST-LABEL: test_F_4:
+;T1POST-LABEL: <test_F_4>:
   define void @test_F_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 ;ARM:         bne
@@ -765,11 +765,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_F(%struct.F* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_F_8:
+;ARM-LABEL:    <test_F_8>:
-;THUMB2-LABEL: test_F_8:
+;THUMB2-LABEL: <test_F_8>:
-;NO_NEON-LABEL:test_F_8:
+;NO_NEON-LABEL:<test_F_8>:
-;THUMB1-LABEL: test_F_8:
+;THUMB1-LABEL: <test_F_8>:
-;T1POST-LABEL: test_F_8:
+;T1POST-LABEL: <test_F_8>:
   define void @test_F_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -796,11 +796,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_F(%struct.F* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_F_16:
+;ARM-LABEL:    <test_F_16>:
-;THUMB2-LABEL: test_F_16:
+;THUMB2-LABEL: <test_F_16>:
-;NO_NEON-LABEL:test_F_16:
+;NO_NEON-LABEL:<test_F_16>:
-;THUMB1-LABEL: test_F_16:
+;THUMB1-LABEL: <test_F_16>:
-;T1POST-LABEL: test_F_16:
+;T1POST-LABEL: <test_F_16>:
   define void @test_F_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -827,11 +827,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_F(%struct.F* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_G_1:
+;ARM-LABEL:    <test_G_1>:
-;THUMB2-LABEL: test_G_1:
+;THUMB2-LABEL: <test_G_1>:
-;NO_NEON-LABEL:test_G_1:
+;NO_NEON-LABEL:<test_G_1>:
-;THUMB1-LABEL: test_G_1:
+;THUMB1-LABEL: <test_G_1>:
-;T1POST-LABEL: test_G_1:
+;T1POST-LABEL: <test_G_1>:
   define void @test_G_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 
@@ -848,11 +848,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_G(%struct.G* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_G_2:
+;ARM-LABEL:    <test_G_2>:
-;THUMB2-LABEL: test_G_2:
+;THUMB2-LABEL: <test_G_2>:
-;NO_NEON-LABEL:test_G_2:
+;NO_NEON-LABEL:<test_G_2>:
-;THUMB1-LABEL: test_G_2:
+;THUMB1-LABEL: <test_G_2>:
-;T1POST-LABEL: test_G_2:
+;T1POST-LABEL: <test_G_2>:
   define void @test_G_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 
@@ -869,11 +869,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_G(%struct.G* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_G_4:
+;ARM-LABEL:    <test_G_4>:
-;THUMB2-LABEL: test_G_4:
+;THUMB2-LABEL: <test_G_4>:
-;NO_NEON-LABEL:test_G_4:
+;NO_NEON-LABEL:<test_G_4>:
-;THUMB1-LABEL: test_G_4:
+;THUMB1-LABEL: <test_G_4>:
-;T1POST-LABEL: test_G_4:
+;T1POST-LABEL: <test_G_4>:
   define void @test_G_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 
@@ -890,11 +890,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_G(%struct.G* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_G_8:
+;ARM-LABEL:    <test_G_8>:
-;THUMB2-LABEL: test_G_8:
+;THUMB2-LABEL: <test_G_8>:
-;NO_NEON-LABEL:test_G_8:
+;NO_NEON-LABEL:<test_G_8>:
-;THUMB1-LABEL: test_G_8:
+;THUMB1-LABEL: <test_G_8>:
-;T1POST-LABEL: test_G_8:
+;T1POST-LABEL: <test_G_8>:
   define void @test_G_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 
@@ -912,11 +912,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_G(%struct.G* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_G_16:
+;ARM-LABEL:    <test_G_16>:
-;THUMB2-LABEL: test_G_16:
+;THUMB2-LABEL: <test_G_16>:
-;NO_NEON-LABEL:test_G_16:
+;NO_NEON-LABEL:<test_G_16>:
-;THUMB1-LABEL: test_G_16:
+;THUMB1-LABEL: <test_G_16>:
-;T1POST-LABEL: test_G_16:
+;T1POST-LABEL: <test_G_16>:
   define void @test_G_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 
@@ -934,11 +934,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_G(%struct.G* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_H_1:
+;ARM-LABEL:    <test_H_1>:
-;THUMB2-LABEL: test_H_1:
+;THUMB2-LABEL: <test_H_1>:
-;NO_NEON-LABEL:test_H_1:
+;NO_NEON-LABEL:<test_H_1>:
-;THUMB1-LABEL: test_H_1:
+;THUMB1-LABEL: <test_H_1>:
-;T1POST-LABEL: test_H_1:
+;T1POST-LABEL: <test_H_1>:
   define void @test_H_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 
@@ -955,11 +955,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_H(%struct.H* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_H_2:
+;ARM-LABEL:    <test_H_2>:
-;THUMB2-LABEL: test_H_2:
+;THUMB2-LABEL: <test_H_2>:
-;NO_NEON-LABEL:test_H_2:
+;NO_NEON-LABEL:<test_H_2>:
-;THUMB1-LABEL: test_H_2:
+;THUMB1-LABEL: <test_H_2>:
-;T1POST-LABEL: test_H_2:
+;T1POST-LABEL: <test_H_2>:
   define void @test_H_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 
@@ -976,11 +976,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_H(%struct.H* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_H_4:
+;ARM-LABEL:    <test_H_4>:
-;THUMB2-LABEL: test_H_4:
+;THUMB2-LABEL: <test_H_4>:
-;NO_NEON-LABEL:test_H_4:
+;NO_NEON-LABEL:<test_H_4>:
-;THUMB1-LABEL: test_H_4:
+;THUMB1-LABEL: <test_H_4>:
-;T1POST-LABEL: test_H_4:
+;T1POST-LABEL: <test_H_4>:
   define void @test_H_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 
@@ -997,11 +997,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_H(%struct.H* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_H_8:
+;ARM-LABEL:    <test_H_8>:
-;THUMB2-LABEL: test_H_8:
+;THUMB2-LABEL: <test_H_8>:
-;NO_NEON-LABEL:test_H_8:
+;NO_NEON-LABEL:<test_H_8>:
-;THUMB1-LABEL: test_H_8:
+;THUMB1-LABEL: <test_H_8>:
-;T1POST-LABEL: test_H_8:
+;T1POST-LABEL: <test_H_8>:
   define void @test_H_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 
@@ -1019,11 +1019,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_H(%struct.H* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_H_16:
+;ARM-LABEL:    <test_H_16>:
-;THUMB2-LABEL: test_H_16:
+;THUMB2-LABEL: <test_H_16>:
-;NO_NEON-LABEL:test_H_16:
+;NO_NEON-LABEL:<test_H_16>:
-;THUMB1-LABEL: test_H_16:
+;THUMB1-LABEL: <test_H_16>:
-;T1POST-LABEL: test_H_16:
+;T1POST-LABEL: <test_H_16>:
   define void @test_H_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 
@@ -1041,11 +1041,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_H(%struct.H* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_I_1:
+;ARM-LABEL:    <test_I_1>:
-;THUMB2-LABEL: test_I_1:
+;THUMB2-LABEL: <test_I_1>:
-;NO_NEON-LABEL:test_I_1:
+;NO_NEON-LABEL:<test_I_1>:
-;THUMB1-LABEL: test_I_1:
+;THUMB1-LABEL: <test_I_1>:
-;T1POST-LABEL: test_I_1:
+;T1POST-LABEL: <test_I_1>:
   define void @test_I_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 
@@ -1062,11 +1062,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_I(%struct.I* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_I_2:
+;ARM-LABEL:    <test_I_2>:
-;THUMB2-LABEL: test_I_2:
+;THUMB2-LABEL: <test_I_2>:
-;NO_NEON-LABEL:test_I_2:
+;NO_NEON-LABEL:<test_I_2>:
-;THUMB1-LABEL: test_I_2:
+;THUMB1-LABEL: <test_I_2>:
-;T1POST-LABEL: test_I_2:
+;T1POST-LABEL: <test_I_2>:
   define void @test_I_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 
@@ -1083,11 +1083,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_I(%struct.I* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_I_4:
+;ARM-LABEL:    <test_I_4>:
-;THUMB2-LABEL: test_I_4:
+;THUMB2-LABEL: <test_I_4>:
-;NO_NEON-LABEL:test_I_4:
+;NO_NEON-LABEL:<test_I_4>:
-;THUMB1-LABEL: test_I_4:
+;THUMB1-LABEL: <test_I_4>:
-;T1POST-LABEL: test_I_4:
+;T1POST-LABEL: <test_I_4>:
   define void @test_I_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 
@@ -1104,11 +1104,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_I(%struct.I* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_I_8:
+;ARM-LABEL:    <test_I_8>:
-;THUMB2-LABEL: test_I_8:
+;THUMB2-LABEL: <test_I_8>:
-;NO_NEON-LABEL:test_I_8:
+;NO_NEON-LABEL:<test_I_8>:
-;THUMB1-LABEL: test_I_8:
+;THUMB1-LABEL: <test_I_8>:
-;T1POST-LABEL: test_I_8:
+;T1POST-LABEL: <test_I_8>:
   define void @test_I_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 
@@ -1126,11 +1126,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_I(%struct.I* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_I_16:
+;ARM-LABEL:    <test_I_16>:
-;THUMB2-LABEL: test_I_16:
+;THUMB2-LABEL: <test_I_16>:
-;NO_NEON-LABEL:test_I_16:
+;NO_NEON-LABEL:<test_I_16>:
-;THUMB1-LABEL: test_I_16:
+;THUMB1-LABEL: <test_I_16>:
-;T1POST-LABEL: test_I_16:
+;T1POST-LABEL: <test_I_16>:
   define void @test_I_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 
@@ -1148,11 +1148,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_I(%struct.I* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_J_1:
+;ARM-LABEL:    <test_J_1>:
-;THUMB2-LABEL: test_J_1:
+;THUMB2-LABEL: <test_J_1>:
-;NO_NEON-LABEL:test_J_1:
+;NO_NEON-LABEL:<test_J_1>:
-;THUMB1-LABEL: test_J_1:
+;THUMB1-LABEL: <test_J_1>:
-;T1POST-LABEL: test_J_1:
+;T1POST-LABEL: <test_J_1>:
   define void @test_J_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 ;ARM:         bne
@@ -1173,11 +1173,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_J(%struct.J* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_J_2:
+;ARM-LABEL:    <test_J_2>:
-;THUMB2-LABEL: test_J_2:
+;THUMB2-LABEL: <test_J_2>:
-;NO_NEON-LABEL:test_J_2:
+;NO_NEON-LABEL:<test_J_2>:
-;THUMB1-LABEL: test_J_2:
+;THUMB1-LABEL: <test_J_2>:
-;T1POST-LABEL: test_J_2:
+;T1POST-LABEL: <test_J_2>:
   define void @test_J_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 ;ARM:         bne
@@ -1198,11 +1198,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_J(%struct.J* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_J_4:
+;ARM-LABEL:    <test_J_4>:
-;THUMB2-LABEL: test_J_4:
+;THUMB2-LABEL: <test_J_4>:
-;NO_NEON-LABEL:test_J_4:
+;NO_NEON-LABEL:<test_J_4>:
-;THUMB1-LABEL: test_J_4:
+;THUMB1-LABEL: <test_J_4>:
-;T1POST-LABEL: test_J_4:
+;T1POST-LABEL: <test_J_4>:
   define void @test_J_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 ;ARM:         bne
@@ -1223,11 +1223,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_J(%struct.J* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_J_8:
+;ARM-LABEL:    <test_J_8>:
-;THUMB2-LABEL: test_J_8:
+;THUMB2-LABEL: <test_J_8>:
-;NO_NEON-LABEL:test_J_8:
+;NO_NEON-LABEL:<test_J_8>:
-;THUMB1-LABEL: test_J_8:
+;THUMB1-LABEL: <test_J_8>:
-;T1POST-LABEL: test_J_8:
+;T1POST-LABEL: <test_J_8>:
   define void @test_J_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -1249,11 +1249,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_J(%struct.J* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_J_16:
+;ARM-LABEL:    <test_J_16>:
-;THUMB2-LABEL: test_J_16:
+;THUMB2-LABEL: <test_J_16>:
-;NO_NEON-LABEL:test_J_16:
+;NO_NEON-LABEL:<test_J_16>:
-;THUMB1-LABEL: test_J_16:
+;THUMB1-LABEL: <test_J_16>:
-;T1POST-LABEL: test_J_16:
+;T1POST-LABEL: <test_J_16>:
   define void @test_J_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -1275,11 +1275,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_J(%struct.J* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_K_1:
+;ARM-LABEL:    <test_K_1>:
-;THUMB2-LABEL: test_K_1:
+;THUMB2-LABEL: <test_K_1>:
-;NO_NEON-LABEL:test_K_1:
+;NO_NEON-LABEL:<test_K_1>:
-;THUMB1-LABEL: test_K_1:
+;THUMB1-LABEL: <test_K_1>:
-;T1POST-LABEL: test_K_1:
+;T1POST-LABEL: <test_K_1>:
   define void @test_K_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 ;ARM:         bne
@@ -1300,11 +1300,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_K(%struct.K* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_K_2:
+;ARM-LABEL:    <test_K_2>:
-;THUMB2-LABEL: test_K_2:
+;THUMB2-LABEL: <test_K_2>:
-;NO_NEON-LABEL:test_K_2:
+;NO_NEON-LABEL:<test_K_2>:
-;THUMB1-LABEL: test_K_2:
+;THUMB1-LABEL: <test_K_2>:
-;T1POST-LABEL: test_K_2:
+;T1POST-LABEL: <test_K_2>:
   define void @test_K_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 ;ARM:         bne
@@ -1325,11 +1325,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_K(%struct.K* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_K_4:
+;ARM-LABEL:    <test_K_4>:
-;THUMB2-LABEL: test_K_4:
+;THUMB2-LABEL: <test_K_4>:
-;NO_NEON-LABEL:test_K_4:
+;NO_NEON-LABEL:<test_K_4>:
-;THUMB1-LABEL: test_K_4:
+;THUMB1-LABEL: <test_K_4>:
-;T1POST-LABEL: test_K_4:
+;T1POST-LABEL: <test_K_4>:
   define void @test_K_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 ;ARM:         bne
@@ -1350,11 +1350,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_K(%struct.K* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_K_8:
+;ARM-LABEL:    <test_K_8>:
-;THUMB2-LABEL: test_K_8:
+;THUMB2-LABEL: <test_K_8>:
-;NO_NEON-LABEL:test_K_8:
+;NO_NEON-LABEL:<test_K_8>:
-;THUMB1-LABEL: test_K_8:
+;THUMB1-LABEL: <test_K_8>:
-;T1POST-LABEL: test_K_8:
+;T1POST-LABEL: <test_K_8>:
   define void @test_K_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -1376,11 +1376,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_K(%struct.K* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_K_16:
+;ARM-LABEL:    <test_K_16>:
-;THUMB2-LABEL: test_K_16:
+;THUMB2-LABEL: <test_K_16>:
-;NO_NEON-LABEL:test_K_16:
+;NO_NEON-LABEL:<test_K_16>:
-;THUMB1-LABEL: test_K_16:
+;THUMB1-LABEL: <test_K_16>:
-;T1POST-LABEL: test_K_16:
+;T1POST-LABEL: <test_K_16>:
   define void @test_K_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -1402,11 +1402,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_K(%struct.K* byval align 16 %a)
     ret void
   }
-;ARM-LABEL:    test_L_1:
+;ARM-LABEL:    <test_L_1>:
-;THUMB2-LABEL: test_L_1:
+;THUMB2-LABEL: <test_L_1>:
-;NO_NEON-LABEL:test_L_1:
+;NO_NEON-LABEL:<test_L_1>:
-;THUMB1-LABEL: test_L_1:
+;THUMB1-LABEL: <test_L_1>:
-;T1POST-LABEL: test_L_1:
+;T1POST-LABEL: <test_L_1>:
   define void @test_L_1() {
 ;ARM:         ldrb    r{{[0-9]+}}, [{{.*}}], #1
 ;ARM:         bne
@@ -1427,11 +1427,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_L(%struct.L* byval align 1 %a)
     ret void
   }
-;ARM-LABEL:    test_L_2:
+;ARM-LABEL:    <test_L_2>:
-;THUMB2-LABEL: test_L_2:
+;THUMB2-LABEL: <test_L_2>:
-;NO_NEON-LABEL:test_L_2:
+;NO_NEON-LABEL:<test_L_2>:
-;THUMB1-LABEL: test_L_2:
+;THUMB1-LABEL: <test_L_2>:
-;T1POST-LABEL: test_L_2:
+;T1POST-LABEL: <test_L_2>:
   define void @test_L_2() {
 ;ARM:         ldrh    r{{[0-9]+}}, [{{.*}}], #2
 ;ARM:         bne
@@ -1452,11 +1452,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_L(%struct.L* byval align 2 %a)
     ret void
   }
-;ARM-LABEL:    test_L_4:
+;ARM-LABEL:    <test_L_4>:
-;THUMB2-LABEL: test_L_4:
+;THUMB2-LABEL: <test_L_4>:
-;NO_NEON-LABEL:test_L_4:
+;NO_NEON-LABEL:<test_L_4>:
-;THUMB1-LABEL: test_L_4:
+;THUMB1-LABEL: <test_L_4>:
-;T1POST-LABEL: test_L_4:
+;T1POST-LABEL: <test_L_4>:
   define void @test_L_4() {
 ;ARM:         ldr     r{{[0-9]+}}, [{{.*}}], #4
 ;ARM:         bne
@@ -1477,11 +1477,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_L(%struct.L* byval align 4 %a)
     ret void
   }
-;ARM-LABEL:    test_L_8:
+;ARM-LABEL:    <test_L_8>:
-;THUMB2-LABEL: test_L_8:
+;THUMB2-LABEL: <test_L_8>:
-;NO_NEON-LABEL:test_L_8:
+;NO_NEON-LABEL:<test_L_8>:
-;THUMB1-LABEL: test_L_8:
+;THUMB1-LABEL: <test_L_8>:
-;T1POST-LABEL: test_L_8:
+;T1POST-LABEL: <test_L_8>:
   define void @test_L_8() {
 ;ARM:         vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -1503,11 +1503,11 @@ declare void @use_N(%struct.N* byval)
     call void @use_L(%struct.L* byval align 8 %a)
     ret void
   }
-;ARM-LABEL:    test_L_16:
+;ARM-LABEL:    <test_L_16>:
-;THUMB2-LABEL: test_L_16:
+;THUMB2-LABEL: <test_L_16>:
-;NO_NEON-LABEL:test_L_16:
+;NO_NEON-LABEL:<test_L_16>:
-;THUMB1-LABEL: test_L_16:
+;THUMB1-LABEL: <test_L_16>:
-;T1POST-LABEL: test_L_16:
+;T1POST-LABEL: <test_L_16>:
   define void @test_L_16() {
 ;ARM:         vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
 ;ARM:         bne
@@ -1529,7 +1529,7 @@ declare void @use_N(%struct.N* byval)
     call void @use_L(%struct.L* byval align 16 %a)
     ret void
   }
-;V8MBASE-LABEL: test_M:
+;V8MBASE-LABEL: <test_M>:
   define void @test_M() {
 
 ;V8MBASE:      ldrb    r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
@@ -1540,7 +1540,7 @@ declare void @use_N(%struct.N* byval)
     call void @use_M(%struct.M* byval align 1 %a)
     ret void
   }
-;V8MBASE-LABEL: test_N:
+;V8MBASE-LABEL: <test_N>:
   define void @test_N() {
 
 ;V8MBASE:      movw    r{{[0-9]+}}, #{{[0-9]+}}

test/CodeGen/ARM/thumb1-varalloc.ll

@@ -9,7 +9,7 @@
 ; rdar://8819685
 define i8* @_foo() {
 entry:
-; CHECK-LABEL: foo:
+; CHECK-LABEL: __foo{{>?}}:
 
 	%size = alloca i32, align 4
 	%0 = load i8*, i8** @__bar, align 4
@@ -46,7 +46,7 @@ declare i32 @_called_func(i8*, i32*) nounwind
 
 ; Simple variable ending up *at* sp.
 define void @test_simple_var() {
-; CHECK-LABEL: test_simple_var:
+; CHECK-LABEL: test_simple_var{{>?}}:
 
   %addr32 = alloca i32
   %addr8 = bitcast i32* %addr32 to i8*
@@ -60,7 +60,7 @@ define void @test_simple_var() {
 
 ; Simple variable ending up at aligned offset from sp.
 define void @test_local_var_addr_aligned() {
-; CHECK-LABEL: test_local_var_addr_aligned:
+; CHECK-LABEL: test_local_var_addr_aligned{{>?}}:
 
   %addr1.32 = alloca i32
   %addr1 = bitcast i32* %addr1.32 to i8*
@@ -81,7 +81,7 @@ define void @test_local_var_addr_aligned() {
 
 ; Simple variable ending up at aligned offset from sp.
 define void @test_local_var_big_offset() {
-; CHECK-LABEL: test_local_var_big_offset:
+; CHECK-LABEL: test_local_var_big_offset{{>?}}:
   %addr1.32 = alloca i32, i32 257
   %addr1 = bitcast i32* %addr1.32 to i8*
   %addr2.32 = alloca i32, i32 257

test/CodeGen/ARM/wrong-t2stmia-size-opt.ll

@@ -20,5 +20,5 @@ define i32* @wrong-t2stmia-size-reduction(i32* %addr, i32 %val0, i32 %val1) mins
 
 ; Check that stm writes three registers.  The bug caused one of registers (LR,
 ; which invalid for Thumb1 form of STMIA instruction) to be dropped.
-; CHECK-LABEL: wrong-t2stmia-size-reduction:
+; CHECK-LABEL: <wrong-t2stmia-size-reduction>:
 ; CHECK: stm{{[^,]*}}, {{{.*,.*,.*}}}

test/CodeGen/BPF/objdump_cond_op.ll

@@ -44,7 +44,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
   %12 = shl nsw i32 %10, 2
   br label %13
 
-; CHECK-LABEL: LBB0_2:
+; CHECK-LABEL: <LBB0_2>:
 ; CHECK: r3 = 0 ll
 ; CHECK: r0 = *(u32 *)(r3 + 0)
 ; CHECK: r2 <<= 32
@@ -56,14 +56,14 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
   %14 = phi i32 [ %12, %11 ], [ %7, %4 ]
   store i32 %14, i32* @gbl, align 4
   br label %15
-; CHECK-LABEL: LBB0_4:
+; CHECK-LABEL: <LBB0_4>:
 ; CHECK: r1 = 0 ll
 ; CHECK: *(u32 *)(r1 + 0) = r0
 
 ; <label>:15:                                     ; preds = %8, %13
   %16 = phi i32 [ %14, %13 ], [ %10, %8 ]
   ret i32 %16
-; CHECK-LABEL: LBB0_5:
+; CHECK-LABEL: <LBB0_5>:
 ; CHECK: exit
 }
 attributes #0 = { norecurse nounwind }

test/CodeGen/BPF/objdump_cond_op_2.ll

@@ -8,7 +8,7 @@
 ; }
 
 define i32 @test(i32, i32) local_unnamed_addr #0 {
-; CHECK-LABEL: test:
+; CHECK-LABEL: <test>:
   %3 = icmp slt i32 %0, %1
   br i1 %3, label %4, label %13
 
@@ -16,7 +16,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
   br label %5
 ; CHECK: if r4 s>= r3 goto +11 <LBB0_3>
 ; CHECK: r0 = 0
-; CHECK-LABEL: LBB0_2:
+; CHECK-LABEL: <LBB0_2>:
 
 ; <label>:5:                                      ; preds = %4, %5
   %6 = phi i32 [ %9, %5 ], [ 0, %4 ]
@@ -33,7 +33,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
 ; <label>:13:                                     ; preds = %5, %2
   %14 = phi i32 [ 0, %2 ], [ %9, %5 ]
   ret i32 %14
-; CHECK-LABEL: LBB0_3:
+; CHECK-LABEL: <LBB0_3>:
 ; CHECK: exit
 }
 attributes #0 = { norecurse nounwind readnone }

test/CodeGen/BPF/objdump_two_funcs.ll

@@ -16,7 +16,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define dso_local i32 @func1(i32 %a) local_unnamed_addr #0 section "s1" !dbg !7 {
 entry:
-; CHECK: func1:
+; CHECK: <func1>:
   call void @llvm.dbg.value(metadata i32 %a, metadata !12, metadata !DIExpression()), !dbg !13
   %mul = mul nsw i32 %a, %a, !dbg !14
   ret i32 %mul, !dbg !15
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define dso_local i32 @func2(i32 %a) local_unnamed_addr #0 section "s2" !dbg !16 {
 entry:
-; CHECK: func2:
+; CHECK: <func2>:
   call void @llvm.dbg.value(metadata i32 %a, metadata !18, metadata !DIExpression()), !dbg !19
   %mul = mul nsw i32 %a, %a, !dbg !20
   %mul1 = mul nsw i32 %mul, %a, !dbg !21

test/CodeGen/Hexagon/S3_2op.ll

@@ -1,6 +1,6 @@
 ; RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s
 
-; CHECK-LABEL: f0:
+; CHECK-LABEL: <f0>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = abs(r{{[1-9]}}:{{[0-9]}})
 define double @f0(double %a0) #0 {
 b0:
@@ -15,7 +15,7 @@ b0:
 
 declare i64 @llvm.hexagon.A2.absp(i64) #1
 
-; CHECK-LABEL: f1:
+; CHECK-LABEL: <f1>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = neg(r{{[1-9]}}:{{[0-9]}})
 define double @f1(double %a0) #0 {
 b0:
@@ -30,7 +30,7 @@ b0:
 
 declare i64 @llvm.hexagon.A2.negp(i64) #1
 
-; CHECK-LABEL: f2:
+; CHECK-LABEL: <f2>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = not(r{{[1-9]}}:{{[0-9]}})
 define double @f2(double %a0) #0 {
 b0:
@@ -45,7 +45,7 @@ b0:
 
 declare i64 @llvm.hexagon.A2.notp(i64) #1
 
-; CHECK-LABEL: f3:
+; CHECK-LABEL: <f3>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = interleave(r{{[1-9]}}:{{[0-9]}})
 define double @f3(double %a0) #0 {
 b0:
@@ -60,7 +60,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.interleave(i64) #1
 
-; CHECK-LABEL: f4:
+; CHECK-LABEL: <f4>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = deinterleave(r{{[1-9]}}:{{[0-9]}})
 define double @f4(double %a0) #0 {
 b0:
@@ -75,7 +75,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.deinterleave(i64) #1
 
-; CHECK-LABEL: f5:
+; CHECK-LABEL: <f5>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vconj(r{{[1-9]}}:{{[0-9]}}):sat
 define double @f5(double %a0) #0 {
 b0:
@@ -90,7 +90,7 @@ b0:
 
 declare i64 @llvm.hexagon.A2.vconj(i64) #1
 
-; CHECK-LABEL: f6:
+; CHECK-LABEL: <f6>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vsathb(r{{[1-9]}}:{{[0-9]}})
 define double @f6(double %a0) #0 {
 b0:
@@ -105,7 +105,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.vsathb.nopack(i64) #1
 
-; CHECK-LABEL: f7:
+; CHECK-LABEL: <f7>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vsathub(r{{[1-9]}}:{{[0-9]}})
 define double @f7(double %a0) #0 {
 b0:
@@ -120,7 +120,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.vsathub.nopack(i64) #1
 
-; CHECK-LABEL: f8:
+; CHECK-LABEL: <f8>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vsatwh(r{{[1-9]}}:{{[0-9]}})
 define double @f8(double %a0) #0 {
 b0:
@@ -135,7 +135,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.vsatwh.nopack(i64) #1
 
-; CHECK-LABEL: f9:
+; CHECK-LABEL: <f9>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vsatwuh(r{{[1-9]}}:{{[0-9]}})
 define double @f9(double %a0) #0 {
 b0:
@@ -150,7 +150,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.vsatwuh.nopack(i64) #1
 
-; CHECK-LABEL: f10:
+; CHECK-LABEL: <f10>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = asr(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f10(double %a0) #0 {
 b0:
@@ -165,7 +165,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #1
 
-; CHECK-LABEL: f11:
+; CHECK-LABEL: <f11>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = lsr(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f11(double %a0) #0 {
 b0:
@@ -180,7 +180,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32) #1
 
-; CHECK-LABEL: f12:
+; CHECK-LABEL: <f12>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = asl(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f12(double %a0) #0 {
 b0:
@@ -195,7 +195,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32) #1
 
-; CHECK-LABEL: f13:
+; CHECK-LABEL: <f13>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsh(r{{[1-9]}}:{{[0-9]}})
 define double @f13(double %a0) #0 {
 b0:
@@ -210,7 +210,7 @@ b0:
 
 declare i64 @llvm.hexagon.A2.vabsh(i64) #1
 
-; CHECK-LABEL: f14:
+; CHECK-LABEL: <f14>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsh(r{{[1-9]}}:{{[0-9]}}):sat
 define double @f14(double %a0) #0 {
 b0:
@@ -225,7 +225,7 @@ b0:
 
 declare i64 @llvm.hexagon.A2.vabshsat(i64) #1
 
-; CHECK-LABEL: f15:
+; CHECK-LABEL: <f15>:
 ; CHECK: r{{[0-9]}}:{{[0-9]}} = vasrh(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f15(double %a0) #0 {
 b0:
@@ -240,7 +240,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) #1
 
-; CHECK-LABEL: f16:
+; CHECK-LABEL: <f16>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vlsrh(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f16(double %a0) #0 {
 b0:
@@ -255,7 +255,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) #1
 
-; CHECK-LABEL: f17:
+; CHECK-LABEL: <f17>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vaslh(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f17(double %a0) #0 {
 b0:
@@ -270,7 +270,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) #1
 
-; CHECK-LABEL: f18:
+; CHECK-LABEL: <f18>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsw(r{{[1-9]}}:{{[0-9]}})
 define double @f18(double %a0) #0 {
 b0:
@@ -285,7 +285,7 @@ b0:
 
 declare i64 @llvm.hexagon.A2.vabsw(i64) #1
 
-; CHECK-LABEL: f19:
+; CHECK-LABEL: <f19>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsw(r{{[1-9]}}:{{[0-9]}}):sat
 define double @f19(double %a0) #0 {
 b0:
@@ -300,7 +300,7 @@ b0:
 
 declare i64 @llvm.hexagon.A2.vabswsat(i64) #1
 
-; CHECK-LABEL: f20:
+; CHECK-LABEL: <f20>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vasrw(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f20(double %a0) #0 {
 b0:
@@ -315,7 +315,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) #1
 
-; CHECK-LABEL: f21:
+; CHECK-LABEL: <f21>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vlsrw(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f21(double %a0) #0 {
 b0:
@@ -330,7 +330,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) #1
 
-; CHECK-LABEL: f22:
+; CHECK-LABEL: <f22>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = vaslw(r{{[1-9]}}:{{[0-9]}},#1)
 define double @f22(double %a0) #0 {
 b0:
@@ -345,7 +345,7 @@ b0:
 
 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1
 
-; CHECK-LABEL: f23:
+; CHECK-LABEL: <f23>:
 ; CHECK: r{{[1-9]}}:{{[0-9]}} = brev(r{{[1-9]}}:{{[0-9]}})
 define double @f23(double %a0) #0 {
 b0:

test/CodeGen/Hexagon/vrcmpys.ll

@@ -3,7 +3,7 @@
 @g0 = common global double 0.000000e+00, align 8
 @g1 = common global double 0.000000e+00, align 8
 
-; CHECK-LABEL: f0:
+; CHECK-LABEL: <f0>:
 ; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo
 define double @f0(i32 %a0, i32 %a1) {
 b0:
@@ -19,7 +19,7 @@ b0:
 ; Function Attrs: nounwind readnone
 declare i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64, i64, i32) #0
 
-; CHECK-LABEL: f1:
+; CHECK-LABEL: <f1>:
 ; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi
 define double @f1(i32 %a0, i32 %a1) {
 b0:
@@ -32,7 +32,7 @@ b0:
   ret double %v5
 }
 
-; CHECK-LABEL: f2:
+; CHECK-LABEL: <f2>:
 ; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo
 define double @f2(i32 %a0, i32 %a1) {
 b0:
@@ -46,7 +46,7 @@ b0:
 ; Function Attrs: nounwind readnone
 declare i64 @llvm.hexagon.M2.vrcmpys.s1(i64, i32) #0
 
-; CHECK-LABEL: f3:
+; CHECK-LABEL: <f3>:
 ; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi
 define double @f3(i32 %a0, i32 %a1) {
 b0:
@@ -57,7 +57,7 @@ b0:
   ret double %v3
 }
 
-; CHECK-LABEL: f4:
+; CHECK-LABEL: <f4>:
 ; CHECK: e9a4c2e0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:lo }
 ; CHECK: e9a4c2c0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:hi }
 define void @f4() {

test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll

@@ -40,7 +40,7 @@ define i32 @f1() {
 ; beqc and bnec have the restriction that $rs < $rt.
 
 define i32 @f2(i32 %a, i32 %b) {
-; ENCODING-LABEL: f2:
+; ENCODING-LABEL: <f2>:
 ; ENCODING-NOT:   beqc $5, $4
 ; ENCODING-NOT:   bnec $5, $4
 
@@ -87,7 +87,7 @@ define i64 @f4() {
 ; beqc and bnec have the restriction that $rs < $rt.
 
 define i64 @f5(i64 %a, i64 %b) {
-; ENCODING-LABEL: f5:
+; ENCODING-LABEL: <f5>:
 ; ENCODING-NOT:   beqc $5, $4
 ; ENCODING-NOT:   bnec $5, $4
 

test/CodeGen/Mips/dsp-spill-reload.ll

@@ -13,7 +13,7 @@
 ; FIXME: We should be able to get rid of those instructions with the variable
 ;        value registers.
 
-; ALL-LABEL: spill_reload:
+; ALL-LABEL: spill_reload{{>?}}:
 
 define <4 x i8>  @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) {
 entry:

test/CodeGen/Mips/micromips-b-range.ll

@@ -1,7 +1,7 @@
 ; RUN: llc -march=mips -relocation-model=pic -mattr=+micromips \
 ; RUN:     -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
 
-; CHECK-LABEL: foo:
+; CHECK-LABEL: <foo>:
 ; CHECK-NEXT:     0:	41 a2 00 00 	lui	$2, 0
 ; CHECK-NEXT:     4:	30 42 00 00 	addiu	$2, $2, 0
 ; CHECK-NEXT:     8:	03 22 11 50 	addu	$2, $2, $25

test/CodeGen/Mips/micromips-sw.ll

@@ -7,10 +7,10 @@
 ; RUN:   | FileCheck --check-prefix=MM6 %s
 
 define void @fun(i32 %val) {
-; MM2-LABEL: fun:
+; MM2-LABEL: <fun>:
 ; MM2:         cb e5 sw $ra, 20($sp)
 
-; MM6-LABEL: fun:
+; MM6-LABEL: <fun>:
 ; MM6:         fb fd 00 14 sw $ra, 20($sp)
 entry:
   call i32* @fun1()

test/CodeGen/Mips/unaligned-memops-mapping.mir

@@ -111,13 +111,13 @@ body:             |
 
 ...
 
-# CHECK-LABEL: g:
+# CHECK-LABEL: <g>:
 # CHECK:  0: 60 24 00 00   lwl $1, 0($4)
 # CHECK:  4: 60 24 10 03   lwr $1, 3($4)
 # CHECK:  8: 60 25 80 00   swl $1, 0($5)
 # CHECK:  c: 60 25 90 03   swr $1, 3($5)
 
-# CHECK-LABEL: g2:
+# CHECK-LABEL: <g2>:
 # CHECK: 14: 60 24 64 00   lwle  $1, 0($4)
 # CHECK: 18: 60 24 66 03   lwre  $1, 3($4)
 # CHECK: 1c: 60 25 a0 00   swle  $1, 0($5)

test/CodeGen/PowerPC/aix-indirect-call.ll

@@ -114,7 +114,7 @@ define void @callThroughPtrWithArgs(void (i32, i16, i64)* nocapture) {
 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .callThroughPtrWithArgs:
-; CHECKOBJ-LABEL: .callThroughPtrWithArgs:
+; CHECKOBJ-LABEL: <.callThroughPtrWithArgs>:
 
 ; ASMOBJ32:      stwu 1, -64(1)
 ; ASMOBJ32-DAG:  lwz [[REG:[0-9]+]], 0(3)

test/CodeGen/PowerPC/aix-return55.ll

@@ -19,21 +19,21 @@ entry:
 ; CHECK: blr
 }
 
-;CHECKOBJ:      00000000 .text:
+;CHECKOBJ:      00000000 <.text>:
 ;CHECKOBJ-NEXT:       0: 38 60 00 37                    li 3, 55
 ;CHECKOBJ-NEXT:       4: 4e 80 00 20                    blr{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000008 .rodata.str1.1:
+;CHECKOBJ-NEXT: 00000008 <.rodata.str1.1>:
 ;CHECKOBJ-NEXT:       8: 68 65 6c 6c                   xori 5, 3, 27756
 ;CHECKOBJ-NEXT:       c: 6f 77 6f 72 xoris 23, 27, 28530
 ;CHECKOBJ-NEXT:      10: 0a 00 00 00 tdlti 0, 0{{[[:space:]] *}}
 ;CHECKOBJ-NEXT: Disassembly of section .data:{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000018 a:
+;CHECKOBJ-NEXT: 00000018 <a>:
 ;CHECKOBJ-NEXT:      18: 00 01 23 45                   <unknown>
 ;CHECKOBJ-NEXT:      1c: 67 8a bc de                   oris 10, 28, 48350{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000020 d:
+;CHECKOBJ-NEXT: 00000020 <d>:
 ;CHECKOBJ-NEXT:      20: 40 14 00 00                   bdnzf   20, .+0
 ;CHECKOBJ-NEXT:      24: 00 00 00 00                   <unknown>{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000028 foo:
+;CHECKOBJ-NEXT: 00000028 <foo>:
 ;CHECKOBJ-NEXT:      28: 00 00 00 00                   <unknown>
 ;CHECKOBJ-NEXT:      2c: 00 00 00 34                   <unknown>
 ;CHECKOBJ-NEXT:      30: 00 00 00 00                   <unknown>

test/CodeGen/PowerPC/aix-user-defined-memcpy.ll

@@ -96,12 +96,12 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture r
 ; 32-REL-NOT:  Type: R_RBR (0x1A)
 
 ; 32-DIS:      Disassembly of section .text:
-; 32-DIS:      00000000 .text:
+; 32-DIS:      00000000 <.text>:
 ; 32-DIS-NEXT:        0: 38 60 00 03                   li 3, 3
 ; 32-DIS-NEXT:        4: 4e 80 00 20                   blr
 ; 32-DIS-NEXT:        8: 60 00 00 00                   nop
 ; 32-DIS-NEXT:        c: 60 00 00 00                   nop
-; 32-DIS:      00000010 .call_memcpy:
+; 32-DIS:      00000010 <.call_memcpy>:
 ; 32-DIS-NEXT:       10: 7c 08 02 a6                   mflr 0
 ; 32-DIS-NEXT:       14: 90 01 00 08                   stw 0, 8(1)
 ; 32-DIS-NEXT:       18: 94 21 ff c0                   stwu 1, -64(1)

test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

@@ -47,11 +47,11 @@ entry:
 ;CHECK-NEXT:         .space  1
 
 
-;CHECKOBJ:      00000000 .text:
+;CHECKOBJ:      00000000 <.text>:
 ;CHECKOBJ-NEXT:        0: 38 60 00 00                    li 3, 0
 ;CHECKOBJ-NEXT:        4: 4e 80 00 20                    blr
 ;CHECKOBJ-NEXT:          ...{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000010 .rodata:
+;CHECKOBJ-NEXT: 00000010 <.rodata>:
 ;CHECKOBJ-NEXT:        10: 40 00 00 00
 ;CHECKOBJ-NEXT:        14: 00 00 00 32
 ;CHECKOBJ-NEXT:          ...{{[[:space:]] *}}

test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

@@ -66,15 +66,15 @@ entry:
 ; CHECK-NEXT: .byte   104
 ; CHECK-NEXT: .byte   0
 
-; CHECKOBJ:     00000010 .rodata.str2.2:
+; CHECKOBJ:     00000010 <.rodata.str2.2>:
 ; CHECKOBJ-NEXT:       10: 01 08 01 10
 ; CHECKOBJ-NEXT:       14: 00 d5 00 00    {{.*}}{{[[:space:]] *}}
-; CHECKOBJ-NEXT: 00000018 .rodata.str4.4:
+; CHECKOBJ-NEXT: 00000018 <.rodata.str4.4>:
 ; CHECKOBJ-NEXT:       18: 00 00 01 d0
 ; CHECKOBJ-NEXT:       1c: 00 00 01 d8
 ; CHECKOBJ-NEXT:       20: 00 00 01 9d
 ; CHECKOBJ-NEXT:       24: 00 00 00 00    {{.*}}{{[[:space:]] *}}
-; CHECKOBJ-NEXT: 00000028 .rodata.str1.1:
+; CHECKOBJ-NEXT: 00000028 <.rodata.str1.1>:
 ; CHECKOBJ-NEXT:       28: 68 65 6c 6c
 ; CHECKOBJ-NEXT:       2c: 6f 20 77 6f
 ; CHECKOBJ-NEXT:       30: 72 6c 64 21

test/CodeGen/PowerPC/aix-xcoff-reloc.ll

@@ -410,7 +410,7 @@ declare i32 @bar(i32)
 
 ; DIS:      {{.*}}aix-xcoff-reloc.ll.tmp.o:   file format aixcoff-rs6000
 ; DIS:      Disassembly of section .text:
-; DIS:      00000000 .text:
+; DIS:      00000000 <.text>:
 ; DIS-NEXT:        0: 7c 08 02 a6                   mflr 0
 ; DIS-NEXT:        4: 90 01 00 08                   stw 0, 8(1)
 ; DIS-NEXT:        8: 94 21 ff c0                   stwu 1, -64(1)
@@ -429,20 +429,20 @@ declare i32 @bar(i32)
 ; DIS-NEXT:       3c: 4e 80 00 20                   blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      00000040 globalA:
+; DIS:      00000040 <globalA>:
 ; DIS-NEXT:       40: 00 00 00 01                   <unknown>
-; DIS:      00000044 globalB:
+; DIS:      00000044 <globalB>:
 ; DIS-NEXT:       44: 00 00 00 02                   <unknown>
-; DIS:      00000048 arr:
+; DIS:      00000048 <arr>:
 ; DIS-NEXT:       48: 00 00 00 03                   <unknown>
 ; DIS-NEXT:                 ...
-; DIS:      00000070 p:
+; DIS:      00000070 <p>:
 ; DIS-NEXT:       70: 00 00 00 58                   <unknown>
-; DIS:      00000074 foo:
+; DIS:      00000074 <foo>:
 ; DIS-NEXT:       74: 00 00 00 00                   <unknown>
 ; DIS-NEXT:       78: 00 00 00 80                   <unknown>
 ; DIS-NEXT:       7c: 00 00 00 00                   <unknown>
-; DIS:      00000080 globalA:
+; DIS:      00000080 <globalA>:
 ; DIS-NEXT:       80: 00 00 00 40                   <unknown>
-; DIS:      00000084 globalB:
+; DIS:      00000084 <globalB>:
 ; DIS-NEXT:       84: 00 00 00 44                   <unknown>

test/CodeGen/PowerPC/aix-xcoff-rodata.ll

@@ -285,33 +285,33 @@
 ; SYMS:      ]
 
 ; DIS: Disassembly of section .text:
-; DIS: 00000000 const_ivar:
+; DIS: 00000000 <const_ivar>:
 ; DIS-NEXT:        0: 00 00 00 23
 ; DIS-NEXT:        4: 00 00 00 00
 
-; DIS: 00000008 const_llvar:
+; DIS: 00000008 <const_llvar>:
 ; DIS-NEXT:        8: 00 00 00 00
 ; DIS-NEXT:        c: 00 00 00 24
 
-; DIS: 00000010 const_svar:
+; DIS: 00000010 <const_svar>:
 ; DIS-NEXT:       10: 00 25 00 00
 
-; DIS: 00000014 const_fvar:
+; DIS: 00000014 <const_fvar>:
 ; DIS-NEXT:       14: 44 48 00 00
 
-; DIS: 00000018 const_dvar:
+; DIS: 00000018 <const_dvar>:
 ; DIS-NEXT:       18: 40 8c 20 00
 ; DIS-NEXT:       1c: 00 00 00 00
 
-; DIS: 00000020 const_over_aligned:
+; DIS: 00000020 <const_over_aligned>:
 ; DIS-NEXT:       20: 40 8c 20 00
 ; DIS-NEXT:       24: 00 00 00 00
 
-; DIS: 00000028 const_chrarray:
+; DIS: 00000028 <const_chrarray>:
 ; DIS-NEXT:       28: 61 62 63 64
 ; DIS-NEXT:       2c: 00 00 00 00
 
-; DIS: 00000030 const_dblarr:
+; DIS: 00000030 <const_dblarr>:
 ; DIS-NEXT:       30: 3f f0 00 00
 ; DIS-NEXT:       34: 00 00 00 00
 ; DIS-NEXT:       38: 40 00 00 00

test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll

@@ -12,11 +12,11 @@ entry:
 }
 
 ; CHECK:     Disassembly of section .text:{{[[:space:]] *}}
-; CHECK-NEXT:     00000000 .text:
+; CHECK-NEXT:     00000000 <.text>:
 ; CHECK-NEXT:        0: 38 60 00 00                   li 3, 0
 ; CHECK-NEXT:        4: 4e 80 00 20                   blr
 ; CHECK-NEXT:        8: 60 00 00 00                   nop
 ; CHECK-NEXT:        c: 60 00 00 00                   nop
-; CHECK:     00000010 .foo1:
+; CHECK:     00000010 <.foo1>:
 ; CHECK-NEXT:       10: 38 60 00 01                   li 3, 1
 ; CHECK-NEXT:       14: 4e 80 00 20                   blr

test/CodeGen/RISCV/compress-float.ll

@@ -32,7 +32,7 @@
 ; instructions which also require one of the floating point extensions.
 
 define float @float_load(float *%a) #0 {
-; RV32IFDC-LABEL: float_load:
+; RV32IFDC-LABEL: <float_load>:
 ; RV32IFDC:         c.flw fa0, 0(a0)
 ; RV32IFDC-NEXT:    c.jr ra
   %1 = load volatile float, float* %a
@@ -40,7 +40,7 @@ define float @float_load(float *%a) #0 {
 }
 
 define double @double_load(double *%a) #0 {
-; RV32IFDC-LABEL: double_load:
+; RV32IFDC-LABEL: <double_load>:
 ; RV32IFDC:         c.fld fa0, 0(a0)
 ; RV32IFDC-NEXT:    c.jr ra
   %1 = load volatile double, double* %a

test/CodeGen/RISCV/compress-inline-asm.ll

@@ -5,7 +5,7 @@
 @ext = external global i32
 
 define i32 @compress_test(i32 %a) {
-; CHECK-LABEL: compress_test:
+; CHECK-LABEL: <compress_test>:
 ; CHECK:    c.add a0, a1
 ; CHECK-NEXT:    c.jr ra
   %1 = load i32, i32* @ext

test/CodeGen/RISCV/compress.ll

@@ -30,7 +30,7 @@
 ; different test file.
 
 define i32 @simple_arith(i32 %a, i32 %b) #0 {
-; RV32IC-LABEL: simple_arith:
+; RV32IC-LABEL: <simple_arith>:
 ; RV32IC:         addi a2, a0, 1
 ; RV32IC-NEXT:    c.andi a2, 11
 ; RV32IC-NEXT:    c.slli a2, 7
@@ -48,7 +48,7 @@ define i32 @simple_arith(i32 %a, i32 %b) #0 {
 }
 
 define i32 @select(i32 %a, i32 *%b) #0 {
-; RV32IC-LABEL: select:
+; RV32IC-LABEL: <select>:
 ; RV32IC:         c.lw a2, 0(a1)
 ; RV32IC-NEXT:    c.beqz a2, 4
 ; RV32IC-NEXT:    c.mv a0, a2
@@ -124,14 +124,14 @@ define i32 @select(i32 %a, i32 *%b) #0 {
 }
 
 define i32 @pos_tiny() #0 {
-; RV32IC-LABEL: pos_tiny:
+; RV32IC-LABEL: <pos_tiny>:
 ; RV32IC:         c.li a0, 18
 ; RV32IC-NEXT:    c.jr ra
   ret i32 18
 }
 
 define i32 @pos_i32() #0 {
-; RV32IC-LABEL: pos_i32:
+; RV32IC-LABEL: <pos_i32>:
 ; RV32IC:         lui a0, 423811
 ; RV32IC-NEXT:    addi a0, a0, -1297
 ; RV32IC-NEXT:    c.jr ra
@@ -139,7 +139,7 @@ define i32 @pos_i32() #0 {
 }
 
 define i32 @pos_i32_half_compressible() #0 {
-; RV32IC-LABEL: pos_i32_half_compressible:
+; RV32IC-LABEL: <pos_i32_half_compressible>:
 ; RV32IC:         lui a0, 423810
 ; RV32IC-NEXT:    c.addi  a0, 28
 ; RV32IC-NEXT:    c.jr    ra
@@ -147,14 +147,14 @@ define i32 @pos_i32_half_compressible() #0 {
 }
 
 define i32 @neg_tiny() #0 {
-; RV32IC-LABEL: neg_tiny:
+; RV32IC-LABEL: <neg_tiny>:
 ; RV32IC:       c.li a0, -19
 ; RV32IC-NEXT:  c.jr ra
   ret i32 -19
 }
 
 define i32 @neg_i32() #0 {
-; RV32IC-LABEL: neg_i32:
+; RV32IC-LABEL: <neg_i32>:
 ; RV32IC:       lui a0, 912092
 ; RV32IC-NEXT:  addi a0, a0, -273
 ; RV32IC-NEXT:  c.jr ra
@@ -162,14 +162,14 @@ define i32 @neg_i32() #0 {
 }
 
 define i32 @pos_i32_hi20_only() #0 {
-; RV32IC-LABEL: pos_i32_hi20_only:
+; RV32IC-LABEL: <pos_i32_hi20_only>:
 ; RV32IC:       c.lui a0, 16
 ; RV32IC-NEXT:  c.jr ra
   ret i32 65536
 }
 
 define i32 @neg_i32_hi20_only() #0 {
-; RV32IC-LABEL: neg_i32_hi20_only:
+; RV32IC-LABEL: <neg_i32_hi20_only>:
 ; RV32IC:       c.lui a0, 1048560
 ; RV32IC-NEXT:  c.jr ra
   ret i32 -65536

test/CodeGen/RISCV/option-norelax.ll

@@ -7,7 +7,7 @@
 declare i32 @foo(i32)
 
 define i32 @bar(i32 %a) nounwind {
-; CHECK-LABEL: bar:
+; CHECK-LABEL: <bar>:
 ; CHECK: R_RISCV_CALL
 ; CHECK: R_RISCV_RELAX
   tail call void asm sideeffect ".option norelax", ""()

test/CodeGen/RISCV/option-norvc.ll

@@ -6,7 +6,7 @@
 ; emitting an ELF directly.
 
 define i32 @add(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: add:
+; CHECK-LABEL: <add>:
 ; CHECK:    c.add a0, a1
 ; CHECK-NEXT:    c.jr ra
   tail call void asm sideeffect ".option norvc", ""()

test/CodeGen/RISCV/option-relax.ll

@@ -7,7 +7,7 @@
 declare i32 @foo(i32)
 
 define i32 @bar(i32 %a) nounwind {
-; CHECK-LABEL: bar:
+; CHECK-LABEL: <bar>:
 ; CHECK: R_RISCV_CALL
 ; CHECK-NOT: R_RISCV_RELAX
   tail call void asm sideeffect ".option relax", ""()

test/CodeGen/RISCV/option-rvc.ll

@@ -6,7 +6,7 @@
 ; emitting an ELF directly.
 
 define i32 @add(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: add:
+; CHECK-LABEL: <add>:
 ; CHECK:    add a0, a1, a0
 ; CHECK-NEXT:    jalr zero, 0(ra)
   tail call void asm sideeffect ".option rvc", ""()

test/CodeGen/Thumb/large-stack.ll

@@ -7,7 +7,7 @@
 
 ; Largest stack for which a single tADDspi/tSUBspi is enough
 define void @test1() {
-; CHECK-LABEL: test1:
+; CHECK-LABEL: test1{{>?}}:
 ; CHECK: sub sp, #508
 ; CHECK: add sp, #508
     %tmp = alloca [ 508 x i8 ] , align 4
@@ -16,7 +16,7 @@ define void @test1() {
 
 ; Largest stack for which three tADDspi/tSUBspis are enough
 define void @test100() {
-; CHECK-LABEL: test100:
+; CHECK-LABEL: test100{{>?}}:
 ; CHECK: sub sp, #508
 ; CHECK: sub sp, #508
 ; CHECK: sub sp, #508
@@ -29,7 +29,7 @@ define void @test100() {
 
 ; Largest stack for which three tADDspi/tSUBspis are enough
 define void @test100_nofpelim() "frame-pointer"="all" {
-; CHECK-LABEL: test100_nofpelim:
+; CHECK-LABEL: test100_nofpelim{{>?}}:
 ; CHECK: sub sp, #508
 ; CHECK: sub sp, #508
 ; CHECK: sub sp, #508
@@ -42,7 +42,7 @@ define void @test100_nofpelim() "frame-pointer"="all" {
 
 ; Smallest stack for which we use a constant pool
 define void @test2() {
-; CHECK-LABEL: test2:
+; CHECK-LABEL: test2{{>?}}:
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]
 ; CHECK: ldr [[TEMP:r[0-7]]],
@@ -53,7 +53,7 @@ define void @test2() {
 
 ; Smallest stack for which we use a constant pool
 define void @test2_nofpelim() "frame-pointer"="all" {
-; CHECK-LABEL: test2_nofpelim:
+; CHECK-LABEL: test2_nofpelim{{>?}}:
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]
 ; CHECK: subs r4, r7, #7
@@ -64,7 +64,7 @@ define void @test2_nofpelim() "frame-pointer"="all" {
 }
 
 define i32 @test3() {
-; CHECK-LABEL: test3:
+; CHECK-LABEL: test3{{>?}}:
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]
 ; CHECK: ldr [[TEMP2:r[0-7]]],
@@ -80,7 +80,7 @@ define i32 @test3() {
 }
 
 define i32 @test3_nofpelim() "frame-pointer"="all" {
-; CHECK-LABEL: test3_nofpelim:
+; CHECK-LABEL: test3_nofpelim{{>?}}:
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]
 ; CHECK: ldr [[TEMP2:r[0-7]]],

test/CodeGen/X86/2014-08-29-CompactUnwind.ll

@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 @.str1 = private unnamed_addr constant [3 x i8] c"  \00", align 1
 @.str2 = private unnamed_addr constant [6 x i8] c"%s%p:\00", align 1
 
-; CHECK: ___asan_report_error:
+; CHECK: <___asan_report_error>:
 
 ; subq instruction starts at 0x0a, so the second byte of the compact encoding
 ; (UNWIND_X86_64_FRAMELESS_STACK_SIZE in mach-o/compact_unwind_encoding.h)

test/CodeGen/X86/callbr-asm-obj-file.ll

@@ -2,7 +2,7 @@
 ; RUN:  | llvm-objdump -triple x86_64-linux-gnu -d - \
 ; RUN:  | FileCheck %s
 
-; CHECK: 0000000000000000 test1:
+; CHECK: 0000000000000000 <test1>:
 ; CHECK-NEXT:   0: 74 00 je 0 <test1+0x2>
 ; CHECK-NEXT:   2: c3    retq
 

test/CodeGen/X86/patchable-prologue.ll

@@ -4,7 +4,7 @@
 declare void @callee(i64*)
 
 define void @f0() "patchable-function"="prologue-short-redirect" {
-; CHECK-LABEL: _f0:
+; CHECK-LABEL: _f0{{>?}}:
 ; CHECK-NEXT:  66 90 	nop
 
 ; CHECK-ALIGN: 	.p2align	4, 0x90
@@ -45,7 +45,7 @@ define void @f3() "patchable-function"="prologue-short-redirect" optsize {
 ; This testcase happens to produce a KILL instruction at the beginning of the
 ; first basic block. In this case the 2nd instruction should be turned into a
 ; patchable one.
-; CHECK-LABEL: f4:
+; CHECK-LABEL: f4{{>?}}:
 ; CHECK-NEXT: 8b 0c 37  movl  (%rdi,%rsi), %ecx
 define i32 @f4(i8* %arg1, i64 %arg2, i32 %arg3) "patchable-function"="prologue-short-redirect" {
 bb:

test/DebugInfo/RISCV/dwarf-riscv-relocs.ll

@@ -18,7 +18,7 @@
 ; Check that we can print the source, even with relocations.
 ; OBJDUMP-SOURCE: Disassembly of section .text:
 ; OBJDUMP-SOURCE-EMPTY:
-; OBJDUMP-SOURCE-NEXT: 00000000 main:
+; OBJDUMP-SOURCE-NEXT: 00000000 <main>:
 ; OBJDUMP-SOURCE: ; {
 ; OBJDUMP-SOURCE: ; return 0;
 

test/LTO/Resolution/X86/asm-output.ll

@@ -7,7 +7,7 @@
 ; RUN: llvm-lto2 run -filetype=obj -r %t1.bc,main,px -o %t2 %t1.bc
 ; RUN: llvm-objdump -d %t2.0 | FileCheck --check-prefix=ASM %s
 ;
-; ASM: main:
+; ASM: main
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"

test/LTO/Resolution/X86/not-prevailing-alias.ll

@@ -14,7 +14,7 @@
 
 ; Check that 'barAlias' and 'varAlias' were not inlined.
 ; RUN: llvm-objdump -d %t2.o.1 | FileCheck %s
-; CHECK:      zed:
+; CHECK:      <zed>:
 ; CHECK-NEXT:  {{.*}}  pushq
 ; CHECK-NEXT:  {{.*}}  callq   0
 ; CHECK-NEXT:   movq  (%rip), %rax

test/LTO/Resolution/X86/not-prevailing-variables.ll

@@ -8,10 +8,10 @@
 
 ; Check 'var2' was not inlined.
 ; RUN: llvm-objdump -d %t2.o.1 | FileCheck %s
-; CHECK:      testVar1:
+; CHECK:      <testVar1>:
 ; CHECK-NEXT:   movl $10, %eax
 ; CHECK-NEXT:   retq
-; CHECK:      testVar2:
+; CHECK:      <testVar2>:
 ; CHECK-NEXT:   movl  (%rip), %eax
 ; CHECK-NEXT:   retq
 

test/LTO/Resolution/X86/not-prevailing.ll

@@ -4,7 +4,7 @@
 ; RUN:   -r %t2.o,bar,x -save-temps
 
 ; Check that 'foo' and 'bar' were not inlined.
-; CHECK:      zed:
+; CHECK:      <zed>:
 ; CHECK-NEXT:  {{.*}}  pushq   %rbx
 ; CHECK-NEXT:  {{.*}}  callq   0 <zed+0x6>
 ; CHECK-NEXT:  {{.*}}  movl    %eax, %ebx

test/LTO/X86/codemodel-1.ll

@@ -14,7 +14,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16
 
 define i32* @_start() nounwind readonly {
 entry:
-; CHECK-SMALL-LABEL:  _start:
+; CHECK-SMALL-LABEL:  <_start>:
 ; CHECK-SMALL: leaq    (%rip), %rax
     ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0)
 }

test/LTO/X86/codemodel-2.ll

@@ -14,7 +14,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16
 
 define i32* @_start() nounwind readonly {
 entry:
-; CHECK-LARGE-LABEL: _start:
+; CHECK-LARGE-LABEL: <_start>:
 ; CHECK-LARGE: movabsq $0, %rax
     ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0)
 }

test/LTO/X86/llvm-lto-output.ll

@@ -9,7 +9,7 @@
 ; RUN: FileCheck --check-prefix=ASM %s < %t2
 ; RUN: llvm-lto -exported-symbol=main -filetype=obj -o %t2 %t1
 ; RUN: llvm-objdump -d %t2 | FileCheck --check-prefix=ASM %s
-; ASM: main:
+; ASM: main{{>?}}:
 ;
 
 target triple = "x86_64-unknown-linux-gnu"

test/MC/AArch64/label-arithmetic-elf.s

@@ -3,7 +3,7 @@
 start:
   .space 8
 end:
-  // CHECK-LABEL: end:
+  // CHECK-LABEL: <end>:
 
   adds w0, w1, #(end - start)
   adds x0, x1, #(end - start)
@@ -72,7 +72,7 @@ notprivate:
 
   .type foo, @function
 foo:
-  // CHECK-LABEL: foo:
+  // CHECK-LABEL: <foo>:
 
   add w0, w1, #(foo - .Lprivate2)
   cmp w0, #(foo - .Lprivate2)
@@ -83,7 +83,7 @@ foo:
 
   .type goo, @function
 goo:
-  // CHECK-LABEL: goo:
+  // CHECK-LABEL: <goo>:
 
   add w0, w1, #(goo - foo)
   cmp w0, #(goo - foo)

test/MC/AMDGPU/labels-branch-gfx9.s

@@ -6,14 +6,14 @@ loop_start:
 s_call_b64 s[10:11], loop_end
 // GFX9: s_call_b64 s[10:11], loop_end   ; encoding: [A,A,0x8a,0xba]
 // GFX9-NEXT: ;   fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
-// BIN: loop_start:
+// BIN: <loop_start>:
 // BIN-NEXT: s_call_b64 s[10:11], loop_end // 000000000000: BA8A0001
 
 s_call_b64 s[10:11], loop_start
 // GFX9: s_call_b64 s[10:11], loop_start ; encoding: [A,A,0x8a,0xba]
 // GFX9-NEXT: ;   fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
 // BIN: s_call_b64 s[10:11], loop_start  // 000000000004: BA8AFFFE
-// BIN: loop_end:
+// BIN: <loop_end>:
 
 loop_end:
   s_nop 0

test/MC/AMDGPU/labels-branch.s

@@ -5,20 +5,20 @@ loop_start:
 s_branch loop_start
 // VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf]
 // VI-NEXT: ;   fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
-// BIN: loop_start:
+// BIN: <loop_start>:
 // BIN-NEXT: s_branch loop_start // 000000000000: BF82FFFF
 
 s_branch loop_end
 // VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf]
 // VI-NEXT: ;   fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
 // BIN: s_branch loop_end // 000000000004: BF820000
-// BIN: loop_end:
+// BIN: <loop_end>:
 loop_end:
 
 s_branch gds
 // VI: s_branch gds ; encoding: [A,A,0x82,0xbf]
 // VI-NEXT: ;   fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br
 // BIN: s_branch gds // 000000000008: BF820000
-// BIN: gds:
+// BIN: <gds>:
 gds:
   s_nop 0

test/MC/ARM/arm-macho-calls.s

@@ -1,7 +1,7 @@
 @ RUN: llvm-mc -triple armv7-apple-ios -filetype=obj -o %t %s
 @ RUN: llvm-objdump -d -r %t | FileCheck %s
 
-@ CHECK: _func:
+@ CHECK: <_func>:
 @ CHECK:    bl #0 <_func+0x8>
 @ CHECK:  ARM_RELOC_BR24 __text
 @ CHECK:    bl #-12 <_func>

test/MC/ARM/coff-relocations.s

@@ -14,28 +14,28 @@
 branch24t_0:
 	b target
 
-@ CHECK-ENCODING-LABEL: branch24t_0:
+@ CHECK-ENCODING-LABEL: <branch24t_0>:
 @ CHECK-ENCODING-NEXT: b.w #0
 
 	.thumb_func
 branch24t_1:
 	bl target
 
-@ CHECK-ENCODING-LABEL: branch24t_1:
+@ CHECK-ENCODING-LABEL: <branch24t_1>:
 @ CHECK-ENCODING-NEXR: bl #0
 
 	.thumb_func
 branch20t:
 	bcc target
 
-@ CHECK-ENCODING-LABEL: branch20t:
+@ CHECK-ENCODING-LABEL: <branch20t>:
 @ CHECK-ENCODING-NEXT: blo.w #0
 
 	.thumb_func
 blx23t:
 	blx target
 
-@ CHECK-ENCODING-LABEL: blx23t:
+@ CHECK-ENCODING-LABEL: <blx23t>:
 @ CHECK-ENCODING-NEXT: blx #0
 
 	.thumb_func
@@ -44,7 +44,7 @@ mov32t:
 	movt r0, :upper16:target
 	blx r0
 
-@ CHECK-ENCODING-LABEL: mov32t:
+@ CHECK-ENCODING-LABEL: <mov32t>:
 @ CHECK-ENCODING-NEXT: movw r0, #0
 @ CHECK-ENCODING-NEXT: movt r0, #0
 @ CHECK-ENCODING-NEXT: blx r0
@@ -57,7 +57,7 @@ addr32:
 .Laddr32:
 	.long target
 
-@ CHECK-ENCODING-LABEL: addr32:
+@ CHECK-ENCODING-LABEL: <addr32>:
 @ CHECK-ENCODING-NEXT: ldr r0, [pc, #4]
 @ CHECK-ENCODING-NEXT: bx r0
 @ CHECK-ENCODING-NEXT: trap
@@ -72,7 +72,7 @@ addr32nb:
 .Laddr32nb:
 	.long target(imgrel)
 
-@ CHECK-ENCODING-LABEL: addr32nb:
+@ CHECK-ENCODING-LABEL: <addr32nb>:
 @ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
 @ CHECK-ENCODING-NEXT: bx r0
 @ CHECK-ENCODING-NEXT: trap
@@ -87,7 +87,7 @@ secrel:
 .Lsecrel:
 	.long target(secrel32)
 
-@ CHECK-ENCODING-LABEL: secrel:
+@ CHECK-ENCODING-LABEL: <secrel>:
 @ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
 @ CHECK-ENCODING-NEXT: bx r0
 @ CHECK-ENCODING-NEXT: trap

test/MC/ARM/elf-movt.s

@@ -31,7 +31,7 @@ bar:
 
 @OBJ:      Disassembly of section .text:
 @OBJ-EMPTY:
-@OBJ-NEXT: barf:
+@OBJ-NEXT: <barf>:
 @OBJ-NEXT: 0:             f0 0f 0f e3     movw    r0, #65520
 @OBJ-NEXT: 00000000:         R_ARM_MOVW_PREL_NC   GOT
 @OBJ-NEXT: 4:             f4 0f 4f e3     movt    r0, #65524
@@ -45,7 +45,7 @@ bar:
 
 @THUMB:      Disassembly of section .text:
 @THUMB-EMPTY:
-@THUMB-NEXT: barf:
+@THUMB-NEXT: <barf>:
 @THUMB-NEXT: 0:             4f f6 f0 70     movw    r0, #65520
 @THUMB-NEXT: 00000000:         R_ARM_THM_MOVW_PREL_NC GOT
 @THUMB-NEXT: 4:             cf f6 f4 70     movt    r0, #65524

test/MC/ARM/sub-expr-imm.s

@@ -15,7 +15,7 @@ AES_Te:
   .word 1,2,3,4,5,6
   .word 1,2,3,4,5,6
   .word 1,2,3,4,5,6
-@ CHECK: AES_encrypt:
+@ CHECK: <AES_encrypt>:
 AES_encrypt:
 @ CHECK: sub	r10, r3, #264
   sub r10,r3,#(AES_encrypt-AES_Te)

test/MC/AVR/relocations-abs.s

@@ -1,6 +1,6 @@
 ; RUN: llvm-mc -filetype=obj -triple=avr %s | llvm-objdump -dr - | FileCheck %s
 
-; CHECK: bar:
+; CHECK: <bar>:
 ; CHECK-NEXT: 00 00 nop
 ; CHECK-NEXT: R_AVR_16 .text+0x2
 bar:

test/MC/BPF/insn-unit.s

@@ -134,7 +134,7 @@ Llabel0 :
   r8 ^= r9    // BPF_XOR  | BPF_X
   r9 = r10    // BPF_MOV  | BPF_X
   r10 s>>= r0 // BPF_ARSH | BPF_X
-// CHECK:Llabel0:
+// CHECK: <Llabel0>:
 // CHECK: 87 02 00 00 00 00 00 00	r2 = -r2
 // CHECK: 4f 54 00 00 00 00 00 00 	r4 |= r5
 // CHECK: 5f 65 00 00 00 00 00 00 	r5 &= r6

test/MC/COFF/cv-inline-linetable-unlikely.s

@@ -21,7 +21,7 @@
 # calls to __asan_report*, for which it is very important to have an accurate
 # stack trace.
 
-# ASM:      0000000000000000 g:
+# ASM:      0000000000000000 <g>:
 # ASM-NEXT:        0: 48 83 ec 28                   subq    $40, %rsp
 # ASM-NEXT:        4: c7 05 fc ff ff ff 00 00 00 00 movl    $0, -4(%rip)
 #  Begin inline loc (matches cv_loc below)

test/MC/COFF/cv-inline-linetable.s

@@ -47,7 +47,7 @@ Lfunc_begin0:
 Lfunc_end0:
 
 # Check the disassembly so we have accurate instruction offsets in hex.
-# ASM-LABEL: ?baz@@YAXXZ:
+# ASM-LABEL: <?baz@@YAXXZ>:
 # ASM-NEXT:       0: {{.*}} pushl   %eax
 # ASM-NEXT:       1: {{.*}} addl    $6, 0
 # ASM-NEXT:       8: {{.*}} addl    $4, 0

test/MC/COFF/cv-loc-unreachable-2.s

@@ -6,7 +6,7 @@
 # section afterwards. We had negative label difference assertions when .cv_loc
 # bound tightly to the next instruction.
 
-# ASM:      00000000 _callit:
+# ASM:      00000000 <_callit>:
 #   begin inline {
 # ASM-NEXT:        0: e8 00 00 00 00                calll   0 <_callit+0x5>
 # ASM-NEXT:        5: 85 c0                         testl   %eax, %eax

test/MC/COFF/cv-loc-unreachable.s

@@ -17,7 +17,7 @@
 # }
 
 
-# ASM:      00000000 _callit:
+# ASM:      00000000 <_callit>:
 #   begin inline {
 # ASM-NEXT:        0: e8 00 00 00 00                calll   0 <_callit+0x5>
 # ASM-NEXT:        5: 85 c0                         testl   %eax, %eax

test/MC/ELF/relax-arith.s

@@ -6,7 +6,7 @@
 bar:
 // CHECK:      Disassembly of section imul:
 // CHECK-EMPTY:
-// CHECK-NEXT: imul:
+// CHECK-NEXT: <imul>:
 // CHECK-NEXT:   0: 66 69 db 00 00                       imulw $0, %bx, %bx
 // CHECK-NEXT:   5: 66 69 1c 25 00 00 00 00 00 00        imulw $0, 0, %bx
 // CHECK-NEXT:   f: 69 db 00 00 00 00                    imull $0, %ebx, %ebx
@@ -23,7 +23,7 @@ bar:
 
 // CHECK:      Disassembly of section and:
 // CHECK-EMPTY:
-// CHECK-NEXT: and:
+// CHECK-NEXT: <and>:
 // CHECK-NEXT:   0: 66 81 e3 00 00                       andw $0, %bx
 // CHECK-NEXT:   5: 66 81 24 25 00 00 00 00 00 00        andw $0, 0
 // CHECK-NEXT:   f: 81 e3 00 00 00 00                    andl $0, %ebx
@@ -38,9 +38,7 @@ bar:
         and  $foo, %rbx
         andq $foo, bar
 
-// CHECK:      Disassembly of section or:
+// CHECK:      <or>:
-// CHECK-EMPTY:
-// CHECK-NEXT: or:
 // CHECK-NEXT:   0: 66 81 cb 00 00                       orw $0, %bx
 // CHECK-NEXT:   5: 66 81 0c 25 00 00 00 00 00 00        orw $0, 0
 // CHECK-NEXT:   f: 81 cb 00 00 00 00                    orl $0, %ebx
@@ -57,7 +55,7 @@ bar:
 
 // CHECK:      Disassembly of section xor:
 // CHECK-EMPTY:
-// CHECK-NEXT: xor:
+// CHECK-NEXT: <xor>:
 // CHECK-NEXT:   0: 66 81 f3 00 00                       xorw $0, %bx
 // CHECK-NEXT:   5: 66 81 34 25 00 00 00 00 00 00        xorw $0, 0
 // CHECK-NEXT:   f: 81 f3 00 00 00 00                    xorl $0, %ebx
@@ -74,7 +72,7 @@ bar:
 
 // CHECK:      Disassembly of section add:
 // CHECK-EMPTY:
-// CHECK-NEXT: add:
+// CHECK-NEXT: <add>:
 // CHECK-NEXT:   0: 66 81 c3 00 00                       addw $0, %bx
 // CHECK-NEXT:   5: 66 81 04 25 00 00 00 00 00 00        addw $0, 0
 // CHECK-NEXT:   f: 81 c3 00 00 00 00                    addl $0, %ebx
@@ -91,7 +89,7 @@ bar:
 
 // CHECK:      Disassembly of section sub:
 // CHECK-EMPTY:
-// CHECK-NEXT: sub:
+// CHECK-NEXT: <sub>:
 // CHECK-NEXT:   0: 66 81 eb 00 00                       subw $0, %bx
 // CHECK-NEXT:   5: 66 81 2c 25 00 00 00 00 00 00        subw $0, 0
 // CHECK-NEXT:   f: 81 eb 00 00 00 00                    subl $0, %ebx
@@ -108,7 +106,7 @@ bar:
 
 // CHECK:      Disassembly of section cmp:
 // CHECK-EMPTY:
-// CHECK-NEXT: cmp:
+// CHECK-NEXT: <cmp>:
 // CHECK-NEXT:   0: 66 81 fb 00 00                       cmpw $0, %bx
 // CHECK-NEXT:   5: 66 81 3c 25 00 00 00 00 00 00        cmpw $0, 0
 // CHECK-NEXT:   f: 81 fb 00 00 00 00                    cmpl $0, %ebx
@@ -125,7 +123,7 @@ bar:
 
 // CHECK:      Disassembly of section push:
 // CHECK-EMPTY:
-// CHECK-NEXT: push:
+// CHECK-NEXT: <push>:
 // CHECK-NEXT:   0: 66 68 00 00                          pushw $0
 // CHECK-NEXT:   4: 68 00 00 00 00                       pushq $0
         .section push,"x"
@@ -134,7 +132,7 @@ bar:
 
 // CHECK:      Disassembly of section adc:
 // CHECK-EMPTY:
-// CHECK-NEXT: adc:
+// CHECK-NEXT: <adc>:
 // CHECK-NEXT:   0: 66 81 d3 00 00                       adcw $0, %bx
 // CHECK-NEXT:   5: 66 81 14 25 00 00 00 00 00 00        adcw $0, 0
 // CHECK-NEXT:   f: 81 d3 00 00 00 00                    adcl $0, %ebx
@@ -151,7 +149,7 @@ bar:
 
 // CHECK:      Disassembly of section sbb:
 // CHECK-EMPTY:
-// CHECK-NEXT: sbb:
+// CHECK-NEXT: <sbb>:
 // CHECK-NEXT:   0: 66 81 db 00 00                       sbbw $0, %bx
 // CHECK-NEXT:   5: 66 81 1c 25 00 00 00 00 00 00        sbbw $0, 0
 // CHECK-NEXT:   f: 81 db 00 00 00 00                    sbbl $0, %ebx

test/MC/ELF/relax-arith2.s

@@ -6,7 +6,7 @@
 bar:
 // CHECK:      Disassembly of section imul:
 // CHECK-EMPTY:
-// CHECK-NEXT: imul:
+// CHECK-NEXT: <imul>:
 // CHECK-NEXT:   0: 66 6b db 80                   imulw $-128, %bx, %bx
 // CHECK-NEXT:   4: 66 6b 1c 25 00 00 00 00 7f    imulw $127, 0, %bx
 // CHECK-NEXT:   d: 6b db 00                      imull $0, %ebx, %ebx
@@ -22,9 +22,7 @@ bar:
         imul $42, bar,  %rbx
 
 
-// CHECK:      Disassembly of section and:
+// CHECK:      <and>:
-// CHECK-EMPTY:
-// CHECK-NEXT: and:
 // CHECK-NEXT:   0: 66 83 e3 7f                   andw $127, %bx
 // CHECK-NEXT:   4: 66 83 24 25 00 00 00 00 00    andw $0, 0
 // CHECK-NEXT:   d: 83 e3 01                      andl $1, %ebx
@@ -39,9 +37,7 @@ bar:
         and  $42, %rbx
         andq $-128, bar
 
-// CHECK:      Disassembly of section or:
+// CHECK:      <or>:
-// CHECK-EMPTY:
-// CHECK-NEXT: or:
 // CHECK-NEXT:   0: 66 83 cb 00                   orw $0, %bx
 // CHECK-NEXT:   4: 66 83 0c 25 00 00 00 00 01    orw $1, 0
 // CHECK-NEXT:   d: 83 cb ff                      orl $-1, %ebx
@@ -56,9 +52,7 @@ bar:
         or  $-128, %rbx
         orq $127, bar
 
-// CHECK:      Disassembly of section xor:
+// CHECK:      <xor>:
-// CHECK-EMPTY:
-// CHECK-NEXT: xor:
 // CHECK-NEXT:   0: 66 83 f3 01                   xorw $1, %bx
 // CHECK-NEXT:   4: 66 83 34 25 00 00 00 00 ff    xorw $-1, 0
 // CHECK-NEXT:   d: 83 f3 2a                      xorl $42, %ebx
@@ -73,9 +67,7 @@ bar:
         xor  $127, %rbx
         xorq $0, bar
 
-// CHECK:      Disassembly of section add:
+// CHECK:      <add>:
-// CHECK-EMPTY:
-// CHECK-NEXT: add:
 // CHECK-NEXT:   0: 66 83 c3 ff                   addw $-1, %bx
 // CHECK-NEXT:   4: 66 83 04 25 00 00 00 00 2a    addw $42, 0
 // CHECK-NEXT:   d: 83 c3 80                      addl $-128, %ebx
@@ -92,7 +84,7 @@ bar:
 
 // CHECK:      Disassembly of section sub:
 // CHECK-EMPTY:
-// CHECK-NEXT: sub:
+// CHECK-NEXT: <sub>:
 // CHECK-NEXT:   0: 66 83 eb 2a                   subw $42, %bx
 // CHECK-NEXT:   4: 66 83 2c 25 00 00 00 00 80    subw $-128, 0
 // CHECK-NEXT:   d: 83 eb 7f                      subl $127, %ebx
@@ -109,7 +101,7 @@ bar:
 
 // CHECK:      Disassembly of section cmp:
 // CHECK-EMPTY:
-// CHECK-NEXT: cmp:
+// CHECK-NEXT: <cmp>:
 // CHECK-NEXT:   0: 66 83 fb 80                   cmpw $-128, %bx
 // CHECK-NEXT:   4: 66 83 3c 25 00 00 00 00 7f    cmpw $127, 0
 // CHECK-NEXT:   d: 83 fb 00                      cmpl $0, %ebx
@@ -126,7 +118,7 @@ bar:
 
 // CHECK:      Disassembly of section push:
 // CHECK-EMPTY:
-// CHECK-NEXT: push:
+// CHECK-NEXT: <push>:
 // CHECK-NEXT:   0: 66 6a 80                      pushw $-128
 // CHECK-NEXT:   3: 66 6a 7f                      pushw $127
 // CHECK-NEXT:   6: 6a 80                         pushq $-128

test/MC/ELF/relax-arith3.s

@@ -6,7 +6,7 @@
 bar:
 // CHECK:      Disassembly of section imul:
 // CHECK-EMPTY:
-// CHECK-NEXT: imul:
+// CHECK-NEXT: <imul>:
 // CHECK-NEXT:   0: 66 69 1d 00 00 00 00 00 00        imulw $0, (%rip), %bx
 // CHECK-NEXT:   9: 69 1d 00 00 00 00 00 00 00 00     imull $0, (%rip), %ebx
 // CHECK-NEXT:  13: 48 69 1d 00 00 00 00 00 00 00 00  imulq $0, (%rip), %rbx
@@ -16,9 +16,7 @@ bar:
         imul $foo, bar(%rip),  %rbx
 
 
-// CHECK:      Disassembly of section and:
+// CHECK:      <and>:
-// CHECK-EMPTY:
-// CHECK-NEXT: and:
 // CHECK-NEXT:   0: 66 81 25 00 00 00 00 00 00        andw $0, (%rip)
 // CHECK-NEXT:   9: 81 25 00 00 00 00 00 00 00 00     andl $0, (%rip)
 // CHECK-NEXT:  13: 48 81 25 00 00 00 00 00 00 00 00  andq $0, (%rip)
@@ -27,9 +25,7 @@ bar:
         andl $foo, bar(%rip)
         andq $foo, bar(%rip)
 
-// CHECK:      Disassembly of section or:
+// CHECK:      <or>:
-// CHECK-EMPTY:
-// CHECK-NEXT: or:
 // CHECK-NEXT:   0: 66 81 0d 00 00 00 00 00 00        orw $0, (%rip)
 // CHECK-NEXT:   9: 81 0d 00 00 00 00 00 00 00 00     orl $0, (%rip)
 // CHECK-NEXT:  13: 48 81 0d 00 00 00 00 00 00 00 00  orq $0, (%rip)
@@ -38,9 +34,7 @@ bar:
         orl $foo, bar(%rip)
         orq $foo, bar(%rip)
 
-// CHECK:      Disassembly of section xor:
+// CHECK:      <xor>:
-// CHECK-EMPTY:
-// CHECK-NEXT: xor:
 // CHECK-NEXT:   0: 66 81 35 00 00 00 00 00 00        xorw $0, (%rip)
 // CHECK-NEXT:   9: 81 35 00 00 00 00 00 00 00 00     xorl $0, (%rip)
 // CHECK-NEXT:  13: 48 81 35 00 00 00 00 00 00 00 00  xorq $0, (%rip)
@@ -49,9 +43,7 @@ bar:
         xorl $foo, bar(%rip)
         xorq $foo, bar(%rip)
 
-// CHECK:      Disassembly of section add:
+// CHECK:      <add>:
-// CHECK-EMPTY:
-// CHECK-NEXT: add:
 // CHECK-NEXT:   0: 66 81 05 00 00 00 00 00 00        addw $0, (%rip)
 // CHECK-NEXT:   9: 81 05 00 00 00 00 00 00 00 00     addl $0, (%rip)
 // CHECK-NEXT:  13: 48 81 05 00 00 00 00 00 00 00 00  addq $0, (%rip)
@@ -60,9 +52,7 @@ bar:
         addl $foo, bar(%rip)
         addq $foo, bar(%rip)
 
-// CHECK:      Disassembly of section sub:
+// CHECK:      <sub>:
-// CHECK-EMPTY:
-// CHECK-NEXT: sub:
 // CHECK-NEXT:   0: 66 81 2d 00 00 00 00 00 00        subw $0, (%rip)
 // CHECK-NEXT:   9: 81 2d 00 00 00 00 00 00 00 00     subl $0, (%rip)
 // CHECK-NEXT:  13: 48 81 2d 00 00 00 00 00 00 00 00  subq $0, (%rip)
@@ -71,9 +61,7 @@ bar:
         subl $foo, bar(%rip)
         subq $foo, bar(%rip)
 
-// CHECK:      Disassembly of section cmp:
+// CHECK:      <cmp>:
-// CHECK-EMPTY:
-// CHECK-NEXT: cmp:
 // CHECK-NEXT:   0: 66 81 3d 00 00 00 00 00 00        cmpw $0, (%rip)
 // CHECK-NEXT:   9: 81 3d 00 00 00 00 00 00 00 00     cmpl $0, (%rip)
 // CHECK-NEXT:  13: 48 81 3d 00 00 00 00 00 00 00 00  cmpq $0, (%rip)

test/MC/ELF/relax-arith4.s

@@ -6,7 +6,7 @@
 
 // CHECK:      Disassembly of section push8:
 // CHECK-EMPTY:
-// CHECK-NEXT: push8:
+// CHECK-NEXT: <push8>:
 // CHECK-NEXT:   0: 66 6a 80                      pushw $-128
 // CHECK-NEXT:   3: 66 6a 7f                      pushw $127
 // CHECK-NEXT:   6: 6a 80                         pushl $-128
@@ -19,7 +19,7 @@
 
 // CHECK:      Disassembly of section push32:
 // CHECK-EMPTY:
-// CHECK-NEXT: push32:
+// CHECK-NEXT: <push32>:
 // CHECK-NEXT:   0: 66 68 00 00                   pushw $0
 // CHECK-NEXT:   4: 68 00 00 00 00                pushl $0
         .section push32,"x"

test/MC/Hexagon/missing_label.s

@@ -4,5 +4,5 @@
 .I1:
 nop
 
-# CHECK: .I1:
+# CHECK: <.I1>:
 # CHECK:        nop

test/MC/Mips/cpsetup.s

@@ -2,7 +2,7 @@
 # RUN:   llvm-objdump -d -r -z - | FileCheck -check-prefixes=ALL,O32 %s
 
 # RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 %s | \
-# RUN:   FileCheck -check-prefixes=ALL,ASM,ASM-O32 %s
+# RUN:   FileCheck -check-prefixes=ASM,ASM-O32 %s
 
 # FIXME: Now we check .cpsetup expansion for `-mno-shared` case only.
 #        We also need to implement/check the `-mshared` case.
@@ -11,14 +11,14 @@
 # RUN:   FileCheck -check-prefixes=ALL,NXX,N32 %s
 
 # RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 %s | \
-# RUN:   FileCheck -check-prefixes=ALL,ASM,ASM-N32 %s
+# RUN:   FileCheck -check-prefixes=ASM,ASM-N32 %s
 
 # RUN: llvm-mc -triple mips64-unknown-linux %s -filetype=obj -o - | \
 # RUN:   llvm-objdump -d -r -z - | \
 # RUN:   FileCheck -check-prefixes=ALL,NXX,N64 %s
 
 # RUN: llvm-mc -triple mips64-unknown-linux %s | \
-# RUN:   FileCheck -check-prefixes=ALL,ASM,ASM-N64 %s
+# RUN:   FileCheck -check-prefixes=ASM,ASM-N64 %s
 
         .text
         .option pic2
@@ -28,7 +28,8 @@ t1:
         .cpreturn
         nop
 
-# ALL-LABEL: t1:
+# ALL-LABEL: <t1>:
+# ASM-LABEL: t1:
 
 # O32-NOT: __cerror
 
@@ -45,7 +46,7 @@ t1:
 
 # ALL-NEXT: nop
 
-# ASM-NEXT: .cpreturn
+# ASM: .cpreturn
 # NXX-NEXT: ld $gp, 8($sp)
 
 # ALL-NEXT: nop
@@ -56,7 +57,8 @@ t2:
         .cpreturn
         nop
 
-# ALL-LABEL: t2:
+# ALL-LABEL: <t2>:
+# ASM-LABEL: t2:
 
 # O32-NOT: __cerror
 
@@ -73,7 +75,7 @@ t2:
 
 # ALL-NEXT: nop
 
-# ASM-NEXT: .cpreturn
+# ASM: .cpreturn
 # NXX-NEXT: move $gp, $2
 
 # ALL-NEXT: nop
@@ -90,7 +92,8 @@ t3:
         nop
         sub $3, $3, $2
 
-# ALL-LABEL: t3:
+# ALL-LABEL: <t3>:
+# ASM-LABEL: t3:
 # ALL-NEXT:  nop
 
 # O32-NEXT:   nop
@@ -129,7 +132,8 @@ t4:
 # by checking that the next instruction after the first
 # nop is also a 'nop'.
 
-# ALL-LABEL: t4:
+# ALL-LABEL: <t4>:
+# ASM-LABEL: t4:
 
 # NXX-NEXT: nop
 # NXX-NEXT: nop
@@ -147,7 +151,8 @@ t5:
         .cpsetup $25, ((8*4) - (3*8)), __cerror
         nop
 
-# ALL-LABEL: t5:
+# ALL-LABEL: <t5>:
+# ASM-LABEL: t5:
 
 # O32-NOT: __cerror
 
@@ -171,7 +176,8 @@ IMM_8 = 8
         .cpreturn
         nop
 
-# ALL-LABEL: t1b:
+# ALL-LABEL: <t1b>:
+# ASM-LABEL: t1b:
 # ASM-NEXT: .set IMM_8, 8
 
 # O32-NOT: __cerror
@@ -189,7 +195,7 @@ IMM_8 = 8
 
 # ALL-NEXT: nop
 
-# ASM-NEXT: .cpreturn
+# ASM: .cpreturn
 # NXX-NEXT: ld $gp, 8($sp)
 
 # ALL-NEXT: nop

test/MC/Mips/higher-highest-addressing.s

@@ -10,7 +10,7 @@
 # relocations.
 
 test1:
-# CHECK-LABEL:    test1:
+# CHECK-LABEL:    <test1>:
 
         lui     $5, %highest(func)
         daddiu  $5, $5, %higher(func)
@@ -27,7 +27,7 @@ test1:
 # ((x + 0x800080008000) >> 48) & 0xffff (highest).
 
 test2:
-# CHECK-LABEL:    test2:
+# CHECK-LABEL:    <test2>:
 
 # Check the case where relocations are not modified by adding +1.  The constant
 # is chosen so that it is just below the value that triggers the addition of +1

test/MC/Mips/instr-analysis.s

@@ -1,19 +1,19 @@
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o - \
 # RUN:   | llvm-objdump -d - | FileCheck %s
 
-# CHECK:      foo:
+# CHECK:      <foo>:
 # CHECK-NEXT:        0:       0c 00 00 02     jal     8 <loc1>
 # CHECK-NEXT:        4:       00 00 00 00     nop
 #
-# CHECK:      loc1:
+# CHECK:      <loc1>:
 # CHECK-NEXT:        8:       0c 00 00 06     jal     24 <loc3>
 # CHECK-NEXT:        c:       00 00 00 00     nop
 #
-# CHECK:      loc2:
+# CHECK:      <loc2>:
 # CHECK-NEXT:       10:       10 00 ff fd     b       -8 <loc1>
 # CHECK-NEXT:       14:       00 00 00 00     nop
 #
-# CHECK:      loc3:
+# CHECK:      <loc3>:
 # CHECK-NEXT:       18:       10 43 ff fd     beq     $2, $3, -8 <loc2>
 # CHECK-NEXT:       1c:       00 00 00 00     nop
 # CHECK-NEXT:       20:       04 11 ff f9     bal     -24 <loc1>

test/MC/Mips/micromips-jump-pc-region.s

@@ -5,7 +5,7 @@
 
 # Force us into the second 256 MB region with a non-zero instruction index
 .org 256*1024*1024 + 12
-# CHECK-LABEL: 1000000c foo:
+# CHECK-LABEL: 1000000c <foo>:
 # CHECK-NEXT: 1000000c: d4 00 00 06                   j       12 <foo>
 # CHECK-NEXT: 10000010: f4 00 00 08                   jal     16 <foo+0x4>
 # CHECK-NEXT: 10000014: f0 00 00 05                   jalx    20 <foo+0x8>

test/MC/Mips/mips-jump-pc-region.s

@@ -7,7 +7,7 @@
 
 # Force us into the second 256 MB region with a non-zero instruction index
 .org 256*1024*1024 + 12
-# CHECK-LABEL: 1000000c foo:
+# CHECK-LABEL: 1000000c <foo>:
 # CHECK-NEXT: 1000000c: 08 00 00 03                   j       12 <foo>
 # CHECK-NEXT: 10000010: 0c 00 00 04                   jal     16 <foo+0x4>
 # CHECK-NEXT: 10000014: 74 00 00 05                   jalx    20 <foo+0x8>

test/MC/Mips/nacl-mask.s

@@ -17,7 +17,7 @@ test1:
         jr	$ra
         nop
 
-# CHECK-LABEL:   test1:
+# CHECK-LABEL:   <test1>:
 
 # CHECK:         and     $4, $4, $14
 # CHECK-NEXT:    jr      $4
@@ -54,7 +54,7 @@ test2:
         lw      $4, 0($sp)
         lw      $4, 0($t8)
 
-# CHECK-LABEL:   test2:
+# CHECK-LABEL:   <test2>:
 
 # CHECK:         and     $1, $1, $15
 # CHECK-NEXT:    lb      $4, 0($1)
@@ -122,7 +122,7 @@ test3:
         sw      $4, 0($sp)
         sw      $4, 0($t8)
 
-# CHECK-LABEL:   test3:
+# CHECK-LABEL:   <test3>:
 
 # CHECK:         and     $1, $1, $15
 # CHECK-NEXT:    sb      $4, 0($1)
@@ -179,7 +179,7 @@ test4:
         lw      $sp, 123($sp)
         sw      $sp, 123($sp)
 
-# CHECK-LABEL:   test4:
+# CHECK-LABEL:   <test4>:
 
 # CHECK:         addiu   $sp, $sp, 24
 # CHECK-NEXT:    and     $sp, $sp, $15
@@ -254,7 +254,7 @@ test5:
 
 # CHECK:             nop
 # CHECK-NEXT:        nop
-# CHECK-LABEL:       test5:
+# CHECK-LABEL:       <test5>:
 # CHECK-NEXT:        jal
 # CHECK-NEXT:        addiu   $4, $zero, 1
 
@@ -304,7 +304,7 @@ test6:
 
 # CHECK:             nop
 # CHECK-NEXT:        nop
-# CHECK-LABEL:       test6:
+# CHECK-LABEL:       <test6>:
 # CHECK-NEXT:        jal
 # CHECK-NEXT:        sw      $4, 0($sp)
 

test/MC/Mips/set-defined-symbol.s

@@ -9,10 +9,10 @@
 a:
   nop
 # CHECK-NOT: a:
-# CHECK: foo:
+# CHECK: <foo>:
 
 b:
   nop
 # CHECK-NOT: b:
 # CHECK-NOT: foo:
-# CHECK: bar:
+# CHECK: <bar>:

test/MC/Mips/sext_64_32.ll

@@ -11,7 +11,7 @@ entry:
   ret i64 %conv
 }
 
-; CHECK-LABEL: foo_2:
+; CHECK-LABEL: <foo_2>:
 ; CHECK: dext ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0, 32
 
 define i64 @foo_2(i32 %ival_2) nounwind readnone {

test/MC/PowerPC/ppc64-dq-expr.s

@@ -22,7 +22,7 @@ test:
         .comm  vecB, 16, 16
 
 # CHECK: Disassembly of section .text:
-# CHECK-LABEL: test:
+# CHECK-LABEL: <test>:
 # CHECK-NEXT:    addis 2, 12, 0
 # CHECK-NEXT:    R_PPC64_REL16_HA     .TOC.
 # CHECK-NEXT:    addi 2, 2, 0

test/MC/PowerPC/ppc64-prefix-align.s

@@ -53,12 +53,12 @@ paddi 1, 2, 8589934576, 0
 addi 2, 3, 15             # 60
 # CHECK-BE:      b8:	38 43 00 0f
 # CHECK-BE-NEXT: bc:	60 00 00 00 	nop
-# CHECK-BE:      LAB1:
+# CHECK-BE:      <LAB1>:
 # CHECK-BE-NEXT: c0:	06 01 ff ff
 # CHECK-BE-NEXT: c4:	38 22 ff f0
 # CHECK-LE:      b8:	0f 00 43 38
 # CHECK-LE-NEXT: bc:	00 00 00 60 	nop
-# CHECK-LE:      LAB1:
+# CHECK-LE:      <LAB1>:
 # CHECK-LE-NEXT: c0:	ff ff 01 06
 # CHECK-LE-NEXT: c4:	f0 ff 22 38
 LAB1: paddi 1, 2, 8589934576, 0
@@ -70,12 +70,12 @@ paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 addi 2, 3, 15             # 60
 # CHECK-BE:      f8:	38 43 00 0f
-# CHECK-BE:      LAB2:
+# CHECK-BE:      <LAB2>:
 # CHECK-BE-NEXT: fc:	60 00 00 00 	nop
 # CHECK-BE-NEXT: 100:	06 01 ff ff
 # CHECK-BE-NEXT: 104:	38 22 ff f0
 # CHECK-LE:      f8:	0f 00 43 38
-# CHECK-LE:      LAB2:
+# CHECK-LE:      <LAB2>:
 # CHECK-LE-NEXT: fc:	00 00 00 60 	nop
 # CHECK-LE-NEXT: 100:	ff ff 01 06
 # CHECK-LE-NEXT: 104:	f0 ff 22 38

test/MC/RISCV/option-mix.s

@@ -21,17 +21,17 @@
 .option pop
   la a1, another_symbol
 
-# ASM-LABEL: .Lpcrel_hi0:
+# ASM-LABEL: .Lpcrel_hi0{{>?}}:
 # ASM-NEXT: auipc   a0, %pcrel_hi(a_symbol)
 # ASM-NEXT: addi    a0, a0, %pcrel_lo(.Lpcrel_hi0)
-# ASM-LABEL: .Lpcrel_hi1:
+# ASM-LABEL: .Lpcrel_hi1{{>?}}:
 # ASM-NEXT: auipc   a1, %pcrel_hi(another_symbol)
 # ASM-NEXT: addi    a1, a1, %pcrel_lo(.Lpcrel_hi1)
 
-# DISASM-LABEL: .Lpcrel_hi0:
+# DISASM-LABEL: <.Lpcrel_hi0>:
 # DISASM-NEXT: auipc   a0, 0
 # DISASM-NEXT: addi    a0, a0, 0
-# DISASM-LABEL:.Lpcrel_hi1:
+# DISASM-LABEL: <.Lpcrel_hi1>:
 # DISASM-NEXT: auipc   a1, 0
 # DISASM-NEXT: addi    a1, a1, 0
 
@@ -43,17 +43,17 @@
 2:auipc   a1, %pcrel_hi(another_symbol)
   addi    a1, a1, %pcrel_lo(2b)
 
-# ASM-LABEL: .Ltmp0:
+# ASM-LABEL: .Ltmp0{{>?}}:
 # ASM-NEXT: auipc   a0, %pcrel_hi(a_symbol)
 # ASM-NEXT: addi    a0, a0, %pcrel_lo(.Ltmp0)
-# ASM-LABEL: .Ltmp1:
+# ASM-LABEL: .Ltmp1{{>?}}:
 # ASM-NEXT: auipc   a1, %pcrel_hi(another_symbol)
 # ASM-NEXT: addi    a1, a1, %pcrel_lo(.Ltmp1)
 
-# DISASM-LABEL: .Ltmp0:
+# DISASM-LABEL: .Ltmp0{{>?}}:
 # DISASM-NEXT: auipc   a0, 0
 # DISASM-NEXT: addi    a0, a0, 0
-# DISASM-LABEL: .Ltmp1:
+# DISASM-LABEL: .Ltmp1{{>?}}:
 # DISASM-NEXT: auipc   a1, 0
 # DISASM-NEXT: addi    a1, a1, 0
 
@@ -66,19 +66,19 @@
 local_symbol1:
   nop
 
-# ASM-LABEL: .Lpcrel_hi2:
+# ASM-LABEL: .Lpcrel_hi2{{>?}}:
 # ASM-NEXT: auipc   a0, %pcrel_hi(a_symbol)
 # ASM-NEXT: addi    a0, a0, %pcrel_lo(.Lpcrel_hi2)
-# ASM-LABEL: .Lpcrel_hi3:
+# ASM-LABEL: .Lpcrel_hi3{{>?}}:
 # ASM-NEXT: auipc   a1, %pcrel_hi(local_symbol1)
 # ASM-NEXT: addi    a1, a1, %pcrel_lo(.Lpcrel_hi3)
 
-# DISASM-LABEL: .Lpcrel_hi2:
+# DISASM-LABEL: .Lpcrel_hi2{{>?}}:
 # DISASM-NEXT: auipc   a0, 0
 # DISASM-NEXT: addi    a0, a0, 0
 # DISASM-NORELAX-NEXT: auipc   a1, 0
 # DISASM-NORELAX-NEXT: addi    a1, a1, 8
-# DISASM-RELAX-LABEL: .Lpcrel_hi3:
+# DISASM-RELAX-LABEL: .Lpcrel_hi3{{>?}}:
 # DISASM-RELAX-NEXT: auipc   a1, 0
 # DISASM-RELAX-NEXT: addi    a1, a1, 0
 
@@ -93,18 +93,18 @@ local_symbol1:
 local_symbol2:
   nop
 
-# ASM-LABEL: .Ltmp2:
+# ASM-LABEL: .Ltmp2{{>?}}:
 # ASM-NEXT: auipc   a0, %pcrel_hi(a_symbol)
 # ASM-NEXT: addi    a0, a0, %pcrel_lo(.Ltmp2)
-# ASM-LABEL: .Ltmp3:
+# ASM-LABEL: .Ltmp3{{>?}}:
 # ASM-NEXT: auipc   a1, %pcrel_hi(local_symbol2)
 # ASM-NEXT: addi    a1, a1, %pcrel_lo(.Ltmp3)
 
-# DISASM-LABEL: .Ltmp2:
+# DISASM-LABEL: .Ltmp2{{>?}}:
 # DISASM-NEXT: auipc   a0, 0
 # DISASM-NEXT: addi    a0, a0, 0
 # DISASM-NORELAX-NEXT: auipc   a1, 0
 # DISASM-NORELAX-NEXT: addi    a1, a1, 8
-# DISASM-RELAX-LABEL: .Ltmp3:
+# DISASM-RELAX-LABEL: .Ltmp3{{>?}}:
 # DISASM-RELAX-NEXT: auipc   a1, 0
 # DISASM-RELAX-NEXT: addi    a1, a1, 0

test/MC/Sparc/sparc-tls-relocations.s

@@ -19,7 +19,7 @@
 ! REL: ]
 
 
-! OBJDUMP: foo:
+! OBJDUMP: <foo>:
 foo:
 ! Here we use two different sequences to get the address of a static TLS variable 'Local'
 ! (note - there is no intent to have valid assembler function here,

test/MC/SystemZ/directive-insn.s

@@ -15,7 +15,7 @@
   .insn rie,0xec0000000076,%r1,%r2,12
 #CHECK: ec 12 00 03 00 64     cgrj %r1, %r2, 0, 0x12
   .insn rie,0xec0000000064,%r1,%r2,label.rie
-#CHECK: label.rie:
+#CHECK: <label.rie>:
 label.rie:
 
 # GAS considers this instruction's immediate operand to be PC relative.
@@ -23,7 +23,7 @@ label.rie:
   .insn ril,0xc60d00000000,%r1,12
 #CHECK: c6 18 00 00 00 03     cgrl %r1, 0x1e
   .insn ril,0xc60800000000,%r1,label.ril
-#CHECK: label.ril:
+#CHECK: <label.ril>:
 label.ril:
 
 #CHECK: c2 2b 80 00 00 00     alfi %r2, 2147483648
@@ -58,7 +58,7 @@ label.ril:
   .insn rsi,0x84000000,%r1,%r3,8
 #CHECK: 84 13 00 02           brxh %r1, %r3, 0x4a
   .insn rsi,0x84000000,%r1,%r3,label.rsi
-#CHECK: label.rsi:
+#CHECK: <label.rsi>:
 label.rsi:
 
 # RSE formats are short displacement versions of the RSY formats.

test/MC/WebAssembly/objdump.s

@@ -16,11 +16,11 @@ test1:
 
 # CHECK-LABEL: CODE:
 # CHECK:             # 2 functions in section.
-# CHECK-LABEL: test0:
+# CHECK-LABEL: <test0>:
 # CHECK-NEXT:        .local  f32, f64, v128, v128
 # CHECK-NEXT:       9:       20 02  local.get	2
 # CHECK-NEXT:       b:       0b     end
-# CHECK-LABEL: test1:
+# CHECK-LABEL: <test1>:
 # CHECK-NEXT:        .local  i32, i64, exnref
 # CHECK-NEXT:      14:       20 03  local.get	3
 # CHECK-NEXT:      16:       0b     end

test/MC/X86/AlignedBundling/labeloffset.s

@@ -11,7 +11,7 @@
         .align  32, 0x90
         .type   main,@function
 main:                                   # @main
-# CHECK-LABEL: main:
+# CHECK-LABEL: <main>:
 # Call + pop sequence for determining the PIC base.
         .bundle_lock align_to_end
         calll   .L0$pb
@@ -81,5 +81,5 @@ tmp3:
         .comm   obj,4,4
         .section .text.foo
         inc %eax
-# CHECK: tmp3:
+# CHECK: <tmp3>:
 # CHECK-NEXT: 1: incl

test/MC/X86/AlignedBundling/nesting.s

@@ -6,7 +6,7 @@
 # Will be bundle-aligning to 16 byte boundaries
   .bundle_align_mode 4
   .text
-# CHECK-LABEL: foo:
+# CHECK-LABEL: <foo>:
 .type   foo,@function
 foo:
 # Test that bundle alignment mode can be set more than once.
@@ -24,7 +24,7 @@ foo:
 # CHECK-NEXT: 15: callq {{.*}} <bar>
 
   .p2align 4
-# CHECK-LABEL: bar:
+# CHECK-LABEL: <bar>:
 .type   bar,@function
 bar:
   callq foo
@@ -40,7 +40,7 @@ bar:
 # CHECK:      36: callq {{.*}} <bar>
 # CHECK-NEXT: 3b: callq {{.*}} <bar>
 
-# CHECK-LABEL: baz:
+# CHECK-LABEL: <baz>:
 .type   baz,@function
 baz:
   callq foo

test/MC/X86/align-branch-32-1a.s

@@ -1,7 +1,7 @@
 # Check NOP padding is disabled before instruction that has variant symbol operand.
 # RUN: llvm-mc -filetype=obj -triple i386-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=call %s | llvm-objdump -d  - | FileCheck %s
 
-# CHECK: 00000000 foo:
+# CHECK: 00000000 <foo>:
 # CHECK-COUNT-5:      : 64 a3 01 00 00 00                movl    %eax, %fs:1
 # CHECK:            1e: e8 fc ff ff ff                   calll   {{.*}}
 # CHECK-COUNT-4:      : 64 a3 01 00 00 00                movl    %eax, %fs:1

test/MC/X86/align-branch-64-1a.s

@@ -10,7 +10,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - > %t4
 # RUN: cmp %t3 %t4
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK:            18: 48 39 c5                         cmpq    %rax, %rbp
 # CHECK-NEXT:       1b: 31 c0                            xorl    %eax, %eax

test/MC/X86/align-branch-64-1b.s

@@ -1,7 +1,7 @@
 # Check only fused conditional jumps and conditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - | FileCheck %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK-NEXT:       18: 48 39 c5                         cmpq    %rax, %rbp
 # CHECK-NEXT:       1b: 31 c0                            xorl    %eax, %eax

test/MC/X86/align-branch-64-1c.s

@@ -1,7 +1,7 @@
 # Check only conditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=jcc
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jcc %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - | FileCheck %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK:            18: 48 39 c5                         cmpq    %rax, %rbp
 # CHECK-NEXT:       1b: 31 c0                            xorl    %eax, %eax

test/MC/X86/align-branch-64-1d.s

@@ -6,7 +6,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 -mcpu=x86-64 --x86-align-branch=jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - >%t2
 # RUN: FileCheck --input-file=%t2 %s --check-prefixes=CHECK,LONG-NOP
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK:            18: 48 39 c5                         cmpq    %rax, %rbp
 # CHECK-NEXT:       1b: 31 c0                            xorl    %eax, %eax

test/MC/X86/align-branch-64-2a.s

@@ -1,7 +1,7 @@
 # Check only indirect jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=indirect
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=indirect %p/Inputs/align-branch-64-2.s | llvm-objdump -d  - | FileCheck %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK-COUNT-2:      : 89 75 f4                         movl    %esi, -12(%rbp)
 # CHECK-COUNT-2:      : 90                               nop

test/MC/X86/align-branch-64-2b.s

@@ -1,7 +1,7 @@
 # Check only calls are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=call
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=call %p/Inputs/align-branch-64-2.s | llvm-objdump -d  - | FileCheck %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK-COUNT-2:      : 89 75 f4                         movl    %esi, -12(%rbp)
 # CHECK:            1e: ff e0                            jmpq    *%rax

test/MC/X86/align-branch-64-2c.s

@@ -1,7 +1,7 @@
 # Check only indirect jumps and calls are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=indirect+call
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=indirect+call %p/Inputs/align-branch-64-2.s  | llvm-objdump -d  - | FileCheck %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK-COUNT-2:      : 89 75 f4                         movl    %esi, -12(%rbp)
 # CHECK-COUNT-2:      : 90                               nop

test/MC/X86/align-branch-64-3a.s

@@ -1,7 +1,7 @@
 # Check NOP padding is disabled before instruction that has variant symbol operand.
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jmp+call %s | llvm-objdump -d  - | FileCheck %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK-COUNT-2:      : 48 89 e5                         movq    %rsp, %rbp
 # CHECK:            1e: e8 00 00 00 00                   callq   {{.*}}

test/MC/X86/align-branch-64-4a.s

@@ -1,7 +1,7 @@
 # Check only rets are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=ret
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=ret %s | llvm-objdump -d  - | FileCheck %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK-COUNT-2:      : 48 89 e5                         movq    %rsp, %rbp
 # CHECK:            1e: 5a                               popq    %rdx

test/MC/X86/align-branch-64-5a.s

@@ -4,7 +4,7 @@
 # RUN: cmp %t1 %t2
 # RUN: FileCheck --input-file=%t1 %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK:            18: c1 e9 02                         shrl    $2, %ecx
 # CHECK-NEXT:       1b: 89 d1                            movl    %edx, %ecx

test/MC/X86/align-branch-64-6a.s

@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret --mc-relax-all %s | llvm-objdump -d  - > %t1
 # RUN: FileCheck --input-file=%t1 %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-NEXT:        0: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK-NEXT:        8: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
 # CHECK-NEXT:       10: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1

test/MC/X86/align-branch-64-7a.s

@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=16 --x86-align-branch=fused+jcc --mc-relax-all %s | llvm-objdump -d  - > %t1
 # RUN: FileCheck --input-file=%t1 %s
 
-# CHECK: 0000000000000000 foo:
+# CHECK: 0000000000000000 <foo>:
 # CHECK-NEXT:       0: 55                               pushq    %rbp
 # CHECK-NEXT:       1: 48 f7 c2 02 00 00 00             testq    $2, %rdx
 # CHECK-NEXT:       8: 0f 85 f2 ff ff ff                jne      {{.*}}

test/MC/X86/align-branch-64-negative.s

@@ -11,8 +11,8 @@
   # In the first test, we have a label which is expected to be bound to the
   # start of the call.  For instance, we want to associate a fault on the call
   # target with some bit of higher level sementic.
-  # CHECK: labeled_call_test1:
+  # CHECK-LABEL: <labeled_call_test1>:
-  # CHECK: 1f label_before
+  # CHECK: 1f <label_before>:
   # CHECK: 1f: nop
   # CHECK: 20: callq
   .globl  labeled_call_test1
@@ -27,10 +27,10 @@ label_before:
   # In the second test, we have a label which is expected to be bound to the
   # end of the call.  For instance, we want the to associate some data with
   # the return address of the call.
-  # CHECK: labeled_call_test2:
+  # CHECK-LABEL: <labeled_call_test2>:
   # CHECK: 5a: callq
   # CHECK: 5f: nop
-  # CHECK: 60 label_after
+  # CHECK: 60 <label_after>:
   # CHECK: 60: jmp
   .globl  labeled_call_test2
   .p2align  5
@@ -45,8 +45,8 @@ label_after:
   # Our third test is like the first w/a labeled fault, but specifically to
   # a fused memory comparison.  This is the form produced by implicit null
   # checks for instance.
-  # CHECK: implicit_null_check:
+  # CHECK-LABEL: <implicit_null_check>:
-  # CHECK: 9f fault_addr
+  # CHECK: 9f <fault_addr>:
   # CHECK: 9f: nop
   # CHECK: a0: cmpq
   .globl  implicit_null_check

test/MC/X86/align-branch-64.s

@@ -14,7 +14,7 @@
   # Next couple tests are checking the edge cases on the alignment computation
 
   .text
-  # CHECK: test1:
+  # CHECK: <test1>:
   # CHECK: 20: callq
   .globl  test1
   .p2align  5
@@ -24,7 +24,7 @@ test1:
   .endr
   callq bar
 
-  # CHECK: test2:
+  # CHECK: <test2>:
   # CHECK: 60: callq
   .globl  test2
   .p2align  5
@@ -34,7 +34,7 @@ test2:
   .endr
   callq bar
 
-  # CHECK: test3:
+  # CHECK: <test3>:
   # CHECK: a0: callq
   .globl  test3
   .p2align  5
@@ -46,7 +46,7 @@ test3:
 
   # next couple check instruction type coverage
 
-  # CHECK: test_jmp:
+  # CHECK: <test_jmp>:
   # CHECK: e0: jmp
   .globl  test_jmp
   .p2align  5
@@ -56,7 +56,7 @@ test_jmp:
   .endr
   jmp bar
 
-  # CHECK: test_ret:
+  # CHECK: <test_ret>:
   # CHECK: 120: retq
   .globl  test_ret
   .p2align  5
@@ -68,7 +68,7 @@ test_ret:
 
   # check a case with a relaxable instruction
 
-  # CHECK: test_jmp_far:
+  # CHECK: <test_jmp_far>:
   # CHECK: 160: jmp
   .globl  test_jmp_far
   .p2align  5
@@ -78,7 +78,7 @@ test_jmp_far:
   .endr
   jmp baz
 
-  # CHECK: test_jcc:
+  # CHECK: <test_jcc>:
   # CHECK: 1a0: jne
   .globl  test_jcc
   .p2align  5
@@ -88,7 +88,7 @@ test_jcc:
   .endr
   jne bar
 
-  # CHECK: test_indirect:
+  # CHECK: <test_indirect>:
   # CHECK: 1e0: jmp
   .globl  test_indirect
   .p2align  5
@@ -103,7 +103,7 @@ test_indirect:
 bar:
   retq
 
-  # CHECK: test_pad_via_relax:
+  # CHECK: <test_pad_via_relax>:
   # CHECK: 200: testq
   # CHECK: 203: jne
   # CHECK: 209: int3
@@ -123,7 +123,7 @@ test_pad_via_relax:
 
   # This case looks really tempting to pad, but doing so for the call causes
   # the jmp to be misaligned.
-  # CHECK: test_pad_via_relax_neg1:
+  # CHECK: <test_pad_via_relax_neg1>:
   # CHECK: 240: int3
   # CHECK: 25a: testq
   # CHECK: 25d: jne
@@ -140,7 +140,7 @@ test_pad_via_relax_neg1:
   callq bar
 
   # Same as previous, but without fusion
-  # CHECK: test_pad_via_relax_neg2:
+  # CHECK: <test_pad_via_relax_neg2>:
   # CHECK: 280: int3
   # CHECK: 29d: jmp
   # CHECK: 29f: nop

test/MC/X86/align-via-relaxation.s

@@ -30,7 +30,7 @@ foo:
 
   # Check that we're not shifting aroudn the offsets of labels - doing
   # that would require a further round of relaxation
-  # CHECK: bar:
+  # CHECK: <bar>:
   # CHECK: 22: eb fe                          jmp -2 <bar>
   # CHECK: 24: 66 2e 0f 1f 84 00 00 00 00 00  nopw %cs:(%rax,%rax)
   # CHECK: 2e: 66 90                          nop
@@ -45,18 +45,18 @@ nobypass:
 
   # Canonical toy loop to show benefit - we can align the loop header with
   # fewer nops by relaxing the branch, even though we don't need to
-  # CHECK: loop_preheader:
+  # CHECK: <loop_preheader>:
   # CHECK: 45: 48 85 c0                       testq %rax, %rax
   # CHECK: 48: 0f 8e 22 00 00 00              jle 34 <loop_exit>
   # CHECK: 4e: 66 2e 0f 1f 84 00 00 00 00 00  nopw %cs:(%rax,%rax)
   # CHECK: 58: 0f 1f 84 00 00 00 00 00        nopl (%rax,%rax)
-  # CHECK: loop_header:
+  # CHECK: <loop_header>:
   # CHECK: 60: 48 83 e8 01                    subq $1, %rax
   # CHECK: 64: 48 85 c0                       testq %rax, %rax
   # CHECK: 67: 7e 07                          jle 7 <loop_exit>
   # CHECK: 69: e9 f2 ff ff ff                 jmp -14 <loop_header>
   # CHECK: 6e: 66 90                          nop
-  # CHECK: loop_exit:
+  # CHECK: <loop_exit>:
   # CHECK: 70: c3                             retq
   .p2align 5
   .skip 5

test/MC/X86/code16-32-64.s

@@ -14,7 +14,7 @@ foo:
 	.code64
 	retq
 
-# CHECK: foo:
+# CHECK: <foo>:
 # CHECK-NEXT: 67 8b 00                      movl    (%eax), %eax
 # CHECK-NEXT: 8b 00                         movl    (%rax), %eax
 # CHECK-NEXT: 67 66 8b 00                   movw    (%eax), %ax

test/MC/X86/disassemble-zeroes.s

@@ -5,7 +5,7 @@
 // This test checks that we follow these rules and can force
 // dissasembly of zero blocks with the -z and --disassemble-zeroes options.
 
-// NODISASM:       0000000000000000 main:
+// NODISASM:       0000000000000000 <main>:
 // NODISASM-NEXT:   0:  00 00               addb %al, (%rax)
 // NODISASM-NEXT:   2:  00 00               addb %al, (%rax)
 // NODISASM-NEXT:   4:  00 00               addb %al, (%rax)
@@ -13,16 +13,16 @@
 // NODISASM-NEXT:       ...
 // NODISASM-NEXT:   20: 90                  nop
 // NODISASM-NEXT:       ...
-// NODISASM:      0000000000000031 foo:
+// NODISASM:      0000000000000031 <foo>:
 // NODISASM-NEXT:   31: 00 00               addb %al, (%rax)
 // NODISASM-NEXT:   33: 00 00               addb %al, (%rax)
-// NODISASM:      0000000000000035 bar:
+// NODISASM:      0000000000000035 <bar>:
 // NODISASM-NEXT:       ...
 
 // Check that with -z we disassemble blocks of zeroes.
 // RUN: llvm-objdump -d -z %t | FileCheck %s --check-prefix=DISASM
 
-// DISASM:      0000000000000000 main:
+// DISASM:      0000000000000000 <main>:
 // DISASM-NEXT:   0: 00 00              addb %al, (%rax)
 // DISASM-NEXT:   2: 00 00              addb %al, (%rax)
 // DISASM-NEXT:   4: 00 00              addb %al, (%rax)
@@ -46,10 +46,10 @@
 // DISASM-NEXT:  2b: 00 00              addb %al, (%rax)
 // DISASM-NEXT:  2d: 00 00              addb %al, (%rax)
 // DISASM-NEXT:  2f: 00 00              addb %al, (%rax)
-// DISASM:      0000000000000031 foo:
+// DISASM:      0000000000000031 <foo>:
 // DISASM-NEXT:  31: 00 00              addb %al, (%rax)
 // DISASM-NEXT:  33: 00 00              addb %al, (%rax)
-// DISASM:      0000000000000035 bar:
+// DISASM:      0000000000000035 <bar>:
 // DISASM-NEXT:  35: 00 00              addb %al, (%rax)
 // DISASM-NEXT:  37: 00 00              addb %al, (%rax)
 // DISASM-NEXT:  39: 00 00              addb %al, (%rax)