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[AArch64][GlobalISel] Select (variable) shifts.

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For now, no support for immediates.

llvm-svn: 278804
This commit is contained in:
Ahmed Bougacha 2016-08-16 14:02:47 +00:00
parent 9abfe90706
commit 29635e3f55
3 changed files with 208 additions and 0 deletions
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15
lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -60,6 +60,12 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
return AArch64::ADDWrr;
case TargetOpcode::G_SUB:
return AArch64::SUBWrr;
case TargetOpcode::G_SHL:
return AArch64::LSLVWr;
case TargetOpcode::G_LSHR:
return AArch64::LSRVWr;
case TargetOpcode::G_ASHR:
return AArch64::ASRVWr;
default:
return GenericOpc;
}
@ -75,6 +81,12 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
return AArch64::ADDXrr;
case TargetOpcode::G_SUB:
return AArch64::SUBXrr;
case TargetOpcode::G_SHL:
return AArch64::LSLVXr;
case TargetOpcode::G_LSHR:
return AArch64::LSRVXr;
case TargetOpcode::G_ASHR:
return AArch64::ASRVXr;
default:
return GenericOpc;
}
@ -190,6 +202,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
case TargetOpcode::G_OR:
case TargetOpcode::G_XOR:
case TargetOpcode::G_AND:
case TargetOpcode::G_SHL:
case TargetOpcode::G_LSHR:
case TargetOpcode::G_ASHR:
case TargetOpcode::G_ADD:
case TargetOpcode::G_SUB: {
DEBUG(dbgs() << "AArch64: Selecting: binop\n");

4
lib/Target/AArch64/AArch64MachineLegalizer.cpp
View File

@ -42,6 +42,10 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
setAction(BinOp, Ty, WidenScalar);
}
for (auto BinOp : {G_SHL, G_LSHR, G_ASHR})
for (auto Ty : {s32, s64})
setAction(BinOp, Ty, Legal);
for (auto MemOp : {G_LOAD, G_STORE})
for (auto Ty : {s32, s64})
setAction(MemOp, Ty, Legal);

189
test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
View File

@ -22,6 +22,15 @@
define void @and_s32_gpr() { ret void }
define void @and_s64_gpr() { ret void }
define void @shl_s32_gpr() { ret void }
define void @shl_s64_gpr() { ret void }
define void @lshr_s32_gpr() { ret void }
define void @lshr_s64_gpr() { ret void }
define void @ashr_s32_gpr() { ret void }
define void @ashr_s64_gpr() { ret void }
define void @unconditional_br() { ret void }
define void @load_s64_gpr(i64* %addr) { ret void }
@ -340,6 +349,186 @@ body: |
%2(64) = G_AND s64 %0, %1
...
---
# Same as add_s32_gpr, for G_SHL operations.
# CHECK-LABEL: name: shl_s32_gpr
name: shl_s32_gpr
isSSA: true
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
# CHECK: body:
# CHECK: %0 = COPY %w0
# CHECK: %1 = COPY %w1
# CHECK: %2 = LSLVWr %0, %1
body: |
bb.0:
liveins: %w0, %w1
%0(32) = COPY %w0
%1(32) = COPY %w1
%2(32) = G_SHL s32 %0, %1
...
---
# Same as add_s64_gpr, for G_SHL operations.
# CHECK-LABEL: name: shl_s64_gpr
name: shl_s64_gpr
isSSA: true
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
# CHECK: body:
# CHECK: %0 = COPY %x0
# CHECK: %1 = COPY %x1
# CHECK: %2 = LSLVXr %0, %1
body: |
bb.0:
liveins: %x0, %x1
%0(64) = COPY %x0
%1(64) = COPY %x1
%2(64) = G_SHL s64 %0, %1
...
---
# Same as add_s32_gpr, for G_LSHR operations.
# CHECK-LABEL: name: lshr_s32_gpr
name: lshr_s32_gpr
isSSA: true
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
# CHECK: body:
# CHECK: %0 = COPY %w0
# CHECK: %1 = COPY %w1
# CHECK: %2 = LSRVWr %0, %1
body: |
bb.0:
liveins: %w0, %w1
%0(32) = COPY %w0
%1(32) = COPY %w1
%2(32) = G_LSHR s32 %0, %1
...
---
# Same as add_s64_gpr, for G_LSHR operations.
# CHECK-LABEL: name: lshr_s64_gpr
name: lshr_s64_gpr
isSSA: true
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
# CHECK: body:
# CHECK: %0 = COPY %x0
# CHECK: %1 = COPY %x1
# CHECK: %2 = LSRVXr %0, %1
body: |
bb.0:
liveins: %x0, %x1
%0(64) = COPY %x0
%1(64) = COPY %x1
%2(64) = G_LSHR s64 %0, %1
...
---
# Same as add_s32_gpr, for G_ASHR operations.
# CHECK-LABEL: name: ashr_s32_gpr
name: ashr_s32_gpr
isSSA: true
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
# CHECK: body:
# CHECK: %0 = COPY %w0
# CHECK: %1 = COPY %w1
# CHECK: %2 = ASRVWr %0, %1
body: |
bb.0:
liveins: %w0, %w1
%0(32) = COPY %w0
%1(32) = COPY %w1
%2(32) = G_ASHR s32 %0, %1
...
---
# Same as add_s64_gpr, for G_ASHR operations.
# CHECK-LABEL: name: ashr_s64_gpr
name: ashr_s64_gpr
isSSA: true
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
# CHECK: body:
# CHECK: %0 = COPY %x0
# CHECK: %1 = COPY %x1
# CHECK: %2 = ASRVXr %0, %1
body: |
bb.0:
liveins: %x0, %x1
%0(64) = COPY %x0
%1(64) = COPY %x1
%2(64) = G_ASHR s64 %0, %1
...
---
# CHECK-LABEL: name: unconditional_br
name: unconditional_br