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[llvm] Use append_range (NFC)
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@ -385,8 +385,7 @@ bool InterleavedAccess::lowerInterleavedLoad(
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return !Extracts.empty() || BinOpShuffleChanged;
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}
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for (auto SVI : Shuffles)
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DeadInsts.push_back(SVI);
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append_range(DeadInsts, Shuffles);
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DeadInsts.push_back(LI);
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return true;
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@ -932,8 +932,7 @@ void VarLocBasedLDV::collectIDsForRegs(VarLocSet &Collected,
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const VarLocSet &CollectFrom) const {
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assert(!Regs.empty() && "Nothing to collect");
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SmallVector<uint32_t, 32> SortedRegs;
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for (Register Reg : Regs)
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SortedRegs.push_back(Reg);
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append_range(SortedRegs, Regs);
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array_pod_sort(SortedRegs.begin(), SortedRegs.end());
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auto It = CollectFrom.find(LocIndex::rawIndexForReg(SortedRegs.front()));
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auto End = CollectFrom.end();
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@ -284,9 +284,7 @@ public:
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/// vector.
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static void FindPredecessorBlocks(MachineBasicBlock *BB,
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SmallVectorImpl<MachineBasicBlock*> *Preds){
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for (MachineBasicBlock::pred_iterator PI = BB->pred_begin(),
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E = BB->pred_end(); PI != E; ++PI)
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Preds->push_back(*PI);
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append_range(*Preds, BB->predecessors());
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}
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/// GetUndefVal - Create an IMPLICIT_DEF instruction with a new register.
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@ -1022,8 +1022,7 @@ DWARFContext::DIEsForAddress DWARFContext::getDIEsForAddress(uint64_t Address) {
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break;
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}
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for (auto Child : DIE)
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Worklist.push_back(Child);
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append_range(Worklist, DIE);
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}
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return Result;
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@ -892,8 +892,7 @@ CallInst *IRBuilderBase::CreateConstrainedFPCall(
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Optional<fp::ExceptionBehavior> Except) {
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llvm::SmallVector<Value *, 6> UseArgs;
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for (auto *OneArg : Args)
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UseArgs.push_back(OneArg);
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append_range(UseArgs, Args);
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bool HasRoundingMD = false;
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switch (Callee->getIntrinsicID()) {
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default:
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@ -350,8 +350,7 @@ static enum BaseType getBaseType(const Value *Val) {
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// Push all the incoming values of phi node into the worklist for
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// processing.
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if (const auto *PN = dyn_cast<PHINode>(V)) {
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for (Value *InV: PN->incoming_values())
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Worklist.push_back(InV);
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append_range(Worklist, PN->incoming_values());
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continue;
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}
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if (const auto *SI = dyn_cast<SelectInst>(V)) {
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@ -21,8 +21,7 @@ BitstreamRemarkSerializerHelper::BitstreamRemarkSerializerHelper(
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: Encoded(), R(), Bitstream(Encoded), ContainerType(ContainerType) {}
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static void push(SmallVectorImpl<uint64_t> &R, StringRef Str) {
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for (const char C : Str)
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R.push_back(C);
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append_range(R, Str);
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}
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static void setRecordName(unsigned RecordID, BitstreamWriter &Bitstream,
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@ -296,8 +296,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
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Visited.insert(T);
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// Add all registers associated with T.
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USet &Asc = AssocMap[T];
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for (USet::iterator J = Asc.begin(), F = Asc.end(); J != F; ++J)
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WorkQ.push_back(*J);
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append_range(WorkQ, Asc);
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}
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}
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@ -2051,8 +2051,7 @@ void DFSanVisitor::visitCallBase(CallBase &CB) {
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Args.push_back(DFSF.LabelReturnAlloca);
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}
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for (i = CB.arg_begin() + FT->getNumParams(); i != CB.arg_end(); ++i)
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Args.push_back(*i);
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append_range(Args, drop_begin(CB.args(), FT->getNumParams()));
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CallInst *CustomCI = IRB.CreateCall(CustomF, Args);
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CustomCI->setCallingConv(CI->getCallingConv());
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