RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
Code Issues Projects Releases Wiki Activity

[RISCV] Fix isStoreToStackSlot

Browse Source 
Because of the layout of stores (that don't have a destination operand)
this check is exactly the same as the one in
RISCVInstrInfo::isLoadFromStackSlot.

Differential Revision: https://reviews.llvm.org/D81805
This commit is contained in:
Roger Ferrer Ibanez 2020-07-14 07:26:01 +00:00
parent 46d2fe7736
commit 2ec487ff11
2 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/RISCV/RISCVInstrInfo.cpp
View File

@ -76,10 +76,10 @@ unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
break;
}
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) {
FrameIndex = MI.getOperand(0).getIndex();
return MI.getOperand(2).getReg();
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
return 0;

1
test/CodeGen/RISCV/stack-store-check.ll
View File

@ -98,7 +98,6 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: sw a0, 308(sp)
; CHECK-NEXT: sw a3, 304(sp)
; CHECK-NEXT: sw a2, 300(sp)
; CHECK-NEXT: lw a0, 52(sp)
; CHECK-NEXT: sw a1, 296(sp)
; CHECK-NEXT: sw s11, 324(sp)
; CHECK-NEXT: sw s9, 320(sp)