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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
[Thumb] Make load/store optimizer less conservative.
If it's safe to clobber the condition flags, we can do a few extra things: it's then possible to reset the base register writeback using a SUBS, so we can try to merge even if the base register isn't dead after the merged instruction. This is effectively a (heavily bug-fixed) rewrite of r208992. llvm-svn: 218386
This commit is contained in:
Moritz Roth
parent
8ccbd5af71
commit
3559e5b2b3
@ -97,6 +97,10 @@ namespace {
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void findUsesOfImpDef(SmallVectorImpl<MachineOperand *> &UsesOfImpDefs,
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const MemOpQueue &MemOps, unsigned DefReg,
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unsigned RangeBegin, unsigned RangeEnd);
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void UpdateBaseRegUses(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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DebugLoc dl, unsigned Base, unsigned WordOffset,
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ARMCC::CondCodes Pred, unsigned PredReg);
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bool MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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int Offset, unsigned Base, bool BaseKill, int Opcode,
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ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
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@ -140,6 +144,46 @@ namespace {
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char ARMLoadStoreOpt::ID = 0;
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}
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static bool definesCPSR(const MachineInstr *MI) {
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for (const auto &MO : MI->operands()) {
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if (!MO.isReg())
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continue;
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if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
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// If the instruction has live CPSR def, then it's not safe to fold it
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// into load / store.
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return true;
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}
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return false;
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}
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static int getMemoryOpOffset(const MachineInstr *MI) {
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int Opcode = MI->getOpcode();
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bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
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unsigned NumOperands = MI->getDesc().getNumOperands();
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unsigned OffField = MI->getOperand(NumOperands-3).getImm();
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if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
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Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
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Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
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Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
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return OffField;
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// Thumb1 immediate offsets are scaled by 4
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if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi)
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return OffField * 4;
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int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField)
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: ARM_AM::getAM5Offset(OffField) * 4;
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ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField)
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: ARM_AM::getAM5Op(OffField);
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if (Op == ARM_AM::sub)
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return -Offset;
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return Offset;
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}
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static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
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switch (Opcode) {
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default: llvm_unreachable("Unhandled opcode!");
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@ -307,6 +351,120 @@ static bool isi32Store(unsigned Opc) {
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return Opc == ARM::STRi12 || isT1i32Store(Opc) || isT2i32Store(Opc);
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}
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static unsigned getImmScale(unsigned Opc) {
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switch (Opc) {
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default: llvm_unreachable("Unhandled opcode!");
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case ARM::tLDRi:
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case ARM::tSTRi:
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return 1;
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case ARM::tLDRHi:
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case ARM::tSTRHi:
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return 2;
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case ARM::tLDRBi:
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case ARM::tSTRBi:
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return 4;
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}
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}
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/// Update future uses of the base register with the offset introduced
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/// due to writeback. This function only works on Thumb1.
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void
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ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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DebugLoc dl, unsigned Base,
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unsigned WordOffset,
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ARMCC::CondCodes Pred, unsigned PredReg) {
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assert(isThumb1 && "Can only update base register uses for Thumb1!");
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// Start updating any instructions with immediate offsets. Insert a SUB before
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// the first non-updateable instruction (if any).
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for (; MBBI != MBB.end(); ++MBBI) {
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bool InsertSub = false;
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unsigned Opc = MBBI->getOpcode();
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if (MBBI->readsRegister(Base)) {
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int Offset;
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bool IsLoad =
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Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi;
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bool IsStore =
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Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi;
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if (IsLoad || IsStore) {
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// Loads and stores with immediate offsets can be updated, but only if
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// the new offset isn't negative.
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// The MachineOperand containing the offset immediate is the last one
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// before predicates.
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MachineOperand &MO =
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MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
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// The offsets are scaled by 1, 2 or 4 depending on the Opcode.
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Offset = MO.getImm() - WordOffset * getImmScale(Opc);
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// If storing the base register, it needs to be reset first.
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unsigned InstrSrcReg = MBBI->getOperand(0).getReg();
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if (Offset >= 0 && !(IsStore && InstrSrcReg == Base))
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MO.setImm(Offset);
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else
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InsertSub = true;
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} else if ((Opc == ARM::tSUBi8 || Opc == ARM::tADDi8) &&
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!definesCPSR(MBBI)) {
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// SUBS/ADDS using this register, with a dead def of the CPSR.
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// Merge it with the update; if the merged offset is too large,
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// insert a new sub instead.
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MachineOperand &MO =
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MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
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Offset = (Opc == ARM::tSUBi8) ?
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MO.getImm() + WordOffset * 4 :
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MO.getImm() - WordOffset * 4 ;
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if (Offset >= 0 && TL->isLegalAddImmediate(Offset)) {
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// FIXME: Swap ADDS<->SUBS if Offset < 0, erase instruction if
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// Offset == 0.
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MO.setImm(Offset);
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// The base register has now been reset, so exit early.
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return;
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} else {
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InsertSub = true;
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}
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} else {
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// Can't update the instruction.
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InsertSub = true;
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}
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} else if (definesCPSR(MBBI) || MBBI->isCall() || MBBI->isBranch()) {
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// Since SUBS sets the condition flags, we can't place the base reset
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// after an instruction that has a live CPSR def.
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// The base register might also contain an argument for a function call.
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InsertSub = true;
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}
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if (InsertSub) {
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// An instruction above couldn't be updated, so insert a sub.
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base), true)
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.addReg(Base, getKillRegState(false)).addImm(WordOffset * 4)
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.addImm(Pred).addReg(PredReg);
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return;
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}
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if (MBBI->killsRegister(Base))
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// Register got killed. Stop updating.
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return;
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}
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// End of block was reached.
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if (MBB.succ_size() > 0) {
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// FIXME: Because of a bug, live registers are sometimes missing from
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// the successor blocks' live-in sets. This means we can't trust that
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// information and *always* have to reset at the end of a block.
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// See PR21029.
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if (MBBI != MBB.end()) --MBBI;
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AddDefaultT1CC(
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BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base), true)
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.addReg(Base, getKillRegState(false)).addImm(WordOffset * 4)
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.addImm(Pred).addReg(PredReg);
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}
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}
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/// MergeOps - Create and insert a LDM or STM with Base as base register and
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/// registers in Regs as the register operands that would be loaded / stored.
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/// It returns true if the transformation is done.
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@ -329,6 +487,22 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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(MBB.computeRegisterLiveness(TRI, ARM::CPSR, std::prev(MBBI), 15) ==
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MachineBasicBlock::LQR_Dead);
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bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
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// Exception: If the base register is in the input reglist, Thumb1 LDM is
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// non-writeback.
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// It's also not possible to merge an STR of the base register in Thumb1.
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if (isThumb1)
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for (unsigned I = 0; I < NumRegs; ++I)
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if (Base == Regs[I].first) {
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if (Opcode == ARM::tLDRi) {
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Writeback = false;
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break;
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} else if (Opcode == ARM::tSTRi) {
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return false;
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}
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}
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ARM_AM::AMSubMode Mode = ARM_AM::ia;
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// VFP and Thumb2 do not support IB or DA modes. Thumb1 only supports IA.
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bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
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@ -421,24 +595,16 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
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if (!Opcode) return false;
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bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
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// Exception: If the base register is in the input reglist, Thumb1 LDM is
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// non-writeback. Check for this.
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if (Opcode == ARM::tLDMIA && isThumb1)
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for (unsigned I = 0; I < NumRegs; ++I)
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if (Base == Regs[I].first) {
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Writeback = false;
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break;
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}
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// If the merged instruction has writeback and the base register is not killed
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// it's not safe to do the merge on Thumb1. This is because resetting the base
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// register writeback by inserting a SUBS sets the condition flags.
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// FIXME: Try something clever here to see if resetting the base register can
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// be avoided, e.g. by updating a later ADD/SUB of the base register with the
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// writeback.
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if (isThumb1 && Writeback && !BaseKill) return false;
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// Check if a Thumb1 LDM/STM merge is safe. This is the case if:
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// - There is no writeback (LDM of base register),
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// - the base register is killed by the merged instruction,
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// - or it's safe to overwrite the condition flags, i.e. to insert a SUBS
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// to reset the base register.
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// Otherwise, don't merge.
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// It's safe to return here since the code to materialize a new base register
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// above is also conditional on SafeToClobberCPSR.
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if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)
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return false;
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MachineInstrBuilder MIB;
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@ -452,6 +618,12 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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// Thumb1: we might need to set base writeback when building the MI.
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MIB.addReg(Base, getDefRegState(true))
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.addReg(Base, getKillRegState(BaseKill));
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// The base isn't dead after a merged instruction with writeback.
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// Insert a sub instruction after the newly formed instruction to reset.
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if (!BaseKill)
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UpdateBaseRegUses(MBB, MBBI, dl, Base, NumRegs, Pred, PredReg);
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} else {
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// No writeback, simply build the MachineInstr.
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MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
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@ -622,6 +794,11 @@ void ARMLoadStoreOpt::MergeOpsUpdate(MachineBasicBlock &MBB,
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memOps[i].MBBI = Merges.back();
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memOps[i].Position = insertPos;
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}
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// Update memOps offsets, since they may have been modified by MergeOps.
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for (auto &MemOp : memOps) {
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MemOp.Offset = getMemoryOpOffset(MemOp.MBBI);
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}
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}
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/// MergeLDR_STR - Merge a number of load / store instructions into one or more
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@ -704,20 +881,6 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
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Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
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}
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static bool definesCPSR(MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
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// If the instruction has live CPSR def, then it's not safe to fold it
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// into load / store.
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return true;
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}
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return false;
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}
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static bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
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unsigned Bytes, unsigned Limit,
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ARMCC::CondCodes Pred, unsigned PredReg) {
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@ -1255,34 +1418,6 @@ void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) {
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RS->forward(std::prev(Loc));
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}
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static int getMemoryOpOffset(const MachineInstr *MI) {
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int Opcode = MI->getOpcode();
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bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
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unsigned NumOperands = MI->getDesc().getNumOperands();
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unsigned OffField = MI->getOperand(NumOperands-3).getImm();
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if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
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Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
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Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
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Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
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return OffField;
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// Thumb1 immediate offsets are scaled by 4
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if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi)
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return OffField * 4;
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int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField)
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: ARM_AM::getAM5Offset(OffField) * 4;
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if (isAM3) {
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if (ARM_AM::getAM3Op(OffField) == ARM_AM::sub)
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Offset = -Offset;
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} else {
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if (ARM_AM::getAM5Op(OffField) == ARM_AM::sub)
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Offset = -Offset;
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}
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return Offset;
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}
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static void InsertLDR_STR(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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int Offset, bool isDef,
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@ -4,8 +4,8 @@ define void @foo(i32* %A) #0 {
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entry:
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; CHECK-LABEL: foo:
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; CHECK: push {r7, lr}
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; CHECK: ldr
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; CHECK-NEXT: ldr
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; CHECK: ldm
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; CHECK-NEXT: subs
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; CHECK-NEXT: bl
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%0 = load i32* %A, align 4
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%arrayidx1 = getelementptr inbounds i32* %A, i32 1
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -regalloc=basic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=RA_GREEDY
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -regalloc=basic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=RA_BASIC
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%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
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%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
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@ -45,7 +45,8 @@ define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
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; CHECK: sub sp, #
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; CHECK: mov r[[R0:[0-9]+]], sp
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; CHECK: str r{{[0-9+]}}, [r[[R0]]
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; CHECK: str r{{[0-9+]}}, [r[[R0]]
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; RA_GREEDY: str r{{[0-9+]}}, [r[[R0]]
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; RA_BASIC: stm r[[R0]]!
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; CHECK-NOT: ldr r0, [sp
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; CHECK: mov r[[R1:[0-9]+]], sp
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; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r{{[0-9]+}}
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@ -1,5 +1,4 @@
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; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | FileCheck %s
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@d = external global [64 x i32]
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@s = external global [64 x i32]
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@ -7,8 +6,12 @@
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define void @t1() #0 {
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entry:
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; CHECK-LABEL: t1:
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; CHECK-NOT: ldm
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; CHECK-NOT: stm
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; CHECK: ldr r[[LB:[0-9]]],
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; CHECK-NEXT: ldm r[[LB]]!,
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; CHECK-NEXT: ldr r[[SB:[0-9]]],
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; CHECK-NEXT: stm r[[SB]]!,
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; CHECK-NEXT: ldrb {{.*}}, [r[[LB]]]
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; CHECK-NEXT: strb {{.*}}, [r[[SB]]]
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tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([64 x i32]* @s to i8*), i8* bitcast ([64 x i32]* @d to i8*), i32 17, i32 4, i1 false)
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ret void
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}
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@ -17,8 +20,14 @@ entry:
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define void @t2() #0 {
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entry:
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; CHECK-LABEL: t2:
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; CHECK-NOT: ldm
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; CHECK-NOT: stm
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; CHECK: ldr r[[LB:[0-9]]],
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; CHECK-NEXT: ldm r[[LB]]!,
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; CHECK-NEXT: ldr r[[SB:[0-9]]],
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; CHECK-NEXT: stm r[[SB]]!,
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; CHECK-NEXT: ldrh {{.*}}, [r[[LB]]]
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; CHECK-NEXT: ldrb {{.*}}, [r[[LB]], #2]
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; CHECK-NEXT: strb {{.*}}, [r[[SB]], #2]
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; CHECK-NEXT: strh {{.*}}, [r[[SB]]]
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tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([64 x i32]* @s to i8*), i8* bitcast ([64 x i32]* @d to i8*), i32 15, i32 4, i1 false)
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ret void
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}
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