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[mips] Correct the definitions of some control instructions
Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
This commit is contained in:
Simon Dardis
parent
3d43672965
commit
36cd99ffe9
@ -630,7 +630,7 @@ class SYS_FM_MM : MMArch {
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let Inst{5-0} = 0x3c;
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}
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class WAIT_FM_MM {
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class WAIT_FM_MM : MMArch {
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bits<10> code_;
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bits<32> Inst;
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@ -967,17 +967,18 @@ let DecoderNamespace = "MicroMips" in {
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let DecoderMethod = "DecodeSyncI_MM" in
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def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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let Predicates = [InMicroMips] in {
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def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
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def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
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def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
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def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>;
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def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>;
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def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM, ISA_MICROMIPS;
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def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM,
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ISA_MICROMIPS;
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def WAIT_MM : MMRel, WaitMM<"wait">, WAIT_FM_MM, ISA_MICROMIPS;
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def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>,
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ISA_MICROMIPS;
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def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>,
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ISA_MICROMIPS;
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def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
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ISA_MIPS32R2;
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ISA_MICROMIPS;
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def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
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ISA_MIPS32R2;
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}
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ISA_MICROMIPS;
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/// Trap Instructions
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def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>,
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@ -1174,11 +1175,11 @@ let Predicates = [InMicroMips] in {
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def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
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II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
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def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
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def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
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def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
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def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
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def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2;
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def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
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def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
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def : MipsInstAlias<"teq $rs, $rt",
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(TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : MipsInstAlias<"tge $rs, $rt",
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@ -1223,7 +1224,7 @@ let Predicates = [InMicroMips] in {
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(SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
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def : MipsInstAlias<"rotr $rt, $imm",
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(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
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def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
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def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>, ISA_MICROMIPS;
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def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS;
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@ -1257,4 +1258,7 @@ let Predicates = [InMicroMips] in {
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ISA_MIPS32R2_NOT_32R6_64R6;
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def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
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ISA_MIPS32R2_NOT_32R6_64R6;
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def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
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def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
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ISA_MICROMIPS;
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}
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@ -2083,28 +2083,24 @@ let AdditionalPredicates = [NotInMicroMips] in {
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
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def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>;
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}
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def TRAP : TrapBase<BREAK>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
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}
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def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>, ISA_MIPS1;
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def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>,
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ISA_MIPS1;
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def TRAP : TrapBase<BREAK>, ISA_MIPS1;
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def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM,
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ISA_MIPS32_NOT_32R6_64R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def ERET : MMRel, ER_FT<"eret", II_ERET>, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
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def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
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def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>,
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ISA_MIPS32R5;
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def DERET : MMRel, ER_FT<"deret", II_DERET>, ER_FM<0x1f, 0x0>, ISA_MIPS32;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>, ISA_MIPS32R2;
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def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>, ISA_MIPS32R2;
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}
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def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>,
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ISA_MIPS32R2;
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def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>,
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ISA_MIPS32R2;
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let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
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AdditionalPredicates = [NotInMicroMips] in {
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def WAIT : WAIT_FT<"wait">, WAIT_FM;
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def WAIT : MMRel, StdMMR6Rel, WAIT_FT<"wait">, WAIT_FM, INSN_MIPS3_32;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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@ -2116,7 +2112,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;
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/// Jump and Branch Instructions
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def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
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AdditionalRequires<[RelocNotPIC, NotInMicroMips]>, IsBranch;
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def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
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def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
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def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
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def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
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BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
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@ -2589,16 +2585,13 @@ def : MipsInstAlias<"beqz $rs,$offset",
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def : MipsInstAlias<"beqzl $rs,$offset",
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(BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
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}
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def : MipsInstAlias<"syscall", (SYSCALL 0), 1>, ISA_MIPS1;
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def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
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def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"break", (BREAK 0, 0), 1>, ISA_MIPS1;
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def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>, ISA_MIPS1;
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def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
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def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"teq $rs, $rt",
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(TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
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def : MipsInstAlias<"tge $rs, $rt",
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@ -1,6 +1,6 @@
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# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips \
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# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips -show-inst \
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# RUN: | FileCheck -check-prefix=CHECK-EL %s
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# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips \
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# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips -show-inst \
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# RUN: | FileCheck -check-prefix=CHECK-EB %s
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# Check that the assembler can handle the documented syntax
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# for control instructions.
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@ -21,20 +21,31 @@
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# CHECK-EL: ehb # encoding: [0x00,0x00,0x00,0x18]
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# CHECK-EL: pause # encoding: [0x00,0x00,0x00,0x28]
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# CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} BREAK_MM
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# CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} BREAK_MM
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# CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} BREAK_MM
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# CHECK-EL: syscall # encoding: [0x00,0x00,0x7c,0x8b]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SYSCALL_MM
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# CHECK-EL: syscall 396 # encoding: [0x8c,0x01,0x7c,0x8b]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SYSCALL_MM
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# CHECK-EL: eret # encoding: [0x00,0x00,0x7c,0xf3]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} ERET_MM
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# CHECK-EL: deret # encoding: [0x00,0x00,0x7c,0xe3]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} DERET_MM
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# CHECK-EL: di # encoding: [0x00,0x00,0x7c,0x47]
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# CHECK-EL: di # encoding: [0x00,0x00,0x7c,0x47]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} DI_MM
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# CHECK-EL: di $10 # encoding: [0x0a,0x00,0x7c,0x47]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} DI_MM
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# CHECK-EL: ei # encoding: [0x00,0x00,0x7c,0x57]
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# CHECK-EL: ei # encoding: [0x00,0x00,0x7c,0x57]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} EI_MM
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# CHECK-EL: ei $10 # encoding: [0x0a,0x00,0x7c,0x57]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} EI_MM
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# CHECK-EL: wait # encoding: [0x00,0x00,0x7c,0x93]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} WAIT_MM
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# CHECK-EL: wait 17 # encoding: [0x11,0x00,0x7c,0x93]
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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} WAIT_MM
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# CHECK-EL: tlbp # encoding: [0x00,0x00,0x7c,0x03]
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# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13]
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# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23]
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@ -1,20 +1,24 @@
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# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 | \
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# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 -show-inst| \
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# RUN: FileCheck -check-prefix=CHECK32 %s
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# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64r2 \
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# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64r2 -show-inst \
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# RUN: | FileCheck -check-prefix=CHECK64 %s
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# CHECK32: break # encoding: [0x00,0x00,0x00,0x0d]
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# CHECK32-NEXT: # <MCInst #{{[0-9]+}} BREAK
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# CHECK32: break 7 # encoding: [0x00,0x07,0x00,0x0d]
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# CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
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# CHECK32: eret # encoding: [0x42,0x00,0x00,0x18]
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# CHECK32-NEXT: # <MCInst #{{[0-9]+}} ERET
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# CHECK32: deret # encoding: [0x42,0x00,0x00,0x1f]
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# CHECK32-NEXT: # <MCInst #{{[0-9]+}} DERET
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# CHECK32: di # encoding: [0x41,0x60,0x60,0x00]
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# CHECK32: di # encoding: [0x41,0x60,0x60,0x00]
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# CHECK32-NEXT: # <MCInst #{{[0-9]+}} DI
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# CHECK32: di $10 # encoding: [0x41,0x6a,0x60,0x00]
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# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
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# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
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# CHECK32-NEXT: # <MCInst #{{[0-9]+}} EI
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# CHECK32: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
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# CHECK32: wait # encoding: [0x42,0x00,0x00,0x20]
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# CHECK32-NEXT: # <MCInst #{{[0-9]+}} WAIT
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# CHECK32: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
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# CHECK32: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
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# CHECK32: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
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@ -35,17 +39,21 @@
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# CHECK32: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff]
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# CHECK64: break # encoding: [0x00,0x00,0x00,0x0d]
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# CHECK64-NEXT: # <MCInst #{{[0-9]+}} BREAK
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# CHECK64: break 7 # encoding: [0x00,0x07,0x00,0x0d]
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# CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
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# CHECK64: eret # encoding: [0x42,0x00,0x00,0x18]
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# CHECK64-NEXT: # <MCInst #{{[0-9]+}} ERET
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# CHECK64: deret # encoding: [0x42,0x00,0x00,0x1f]
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# CHECK64-NEXT: # <MCInst #{{[0-9]+}} DERET
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# CHECK64: di # encoding: [0x41,0x60,0x60,0x00]
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# CHECK64: di # encoding: [0x41,0x60,0x60,0x00]
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# CHECK64-NEXT: # <MCInst #{{[0-9]+}} DI
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# CHECK64: di $10 # encoding: [0x41,0x6a,0x60,0x00]
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# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
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# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
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# CHECK64-NEXT: # <MCInst #{{[0-9]+}} EI
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# CHECK64: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
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# CHECK64: wait # encoding: [0x42,0x00,0x00,0x20]
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# CHECK64-NEXT: # <MCInst #{{[0-9]+}} WAIT
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# CHECK64: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
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# CHECK64: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
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# CHECK64: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
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