RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
Code Issues Projects Releases Wiki Activity

[X86] Merge LowerADD and LowerSUB into a single LowerADD_SUB since they are identical.

Browse Source 
llvm-svn: 292469
This commit is contained in:
Craig Topper 2017-01-19 03:49:29 +00:00
parent d863e3261f
commit 3abaabacbe
1 changed files with 3 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/X86/X86ISelLowering.cpp
View File

@ -20846,17 +20846,7 @@ static SDValue Lower512IntArith(SDValue Op, SelectionDAG &DAG) {
DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
}
static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
if (Op.getValueType() == MVT::i1)
return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
Op.getOperand(0), Op.getOperand(1));
assert(Op.getSimpleValueType().is256BitVector() &&
Op.getSimpleValueType().isInteger() &&
"Only handle AVX 256-bit vector integer operation");
return Lower256IntArith(Op, DAG);
}
static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
static SDValue LowerADD_SUB(SDValue Op, SelectionDAG &DAG) {
if (Op.getValueType() == MVT::i1)
return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
Op.getOperand(0), Op.getOperand(1));
@ -23404,8 +23394,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ADDE:
case ISD::SUBC:
case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
case ISD::ADD: return LowerADD(Op, DAG);
case ISD::SUB: return LowerSUB(Op, DAG);
case ISD::ADD:
case ISD::SUB: return LowerADD_SUB(Op, DAG);
case ISD::SMAX:
case ISD::SMIN:
case ISD::UMAX: