RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
Code Issues Projects Releases Wiki Activity

r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC.

Browse Source 
llvm-svn: 68671
This commit is contained in:
Sanjiv Gupta 2009-04-09 04:03:43 +00:00
parent 68de98eef3
commit 3baf157321
1 changed files with 10 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -1359,21 +1359,26 @@ SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
// Put one value on stack. // Put one value on stack.
SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
// ADDC and ADDE produces two results.
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
// ADDE has three operands, the last one is a flag.
if (Op.getOpcode() == ISD::ADDE) if (Op.getOpcode() == ISD::ADDE)
return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
NewVal, Op.getOperand(2)); NewVal, Op.getOperand(2));
else // ADDC has two operands.
else if (Op.getOpcode() == ISD::ADDC)
return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
NewVal); NewVal);
// ADD it is. It produces only one result.
else
return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
NewVal);
} }
else if (Op.getOpcode() == ISD::ADD) { else if (Op.getOpcode() == ISD::ADD)
return Op; return Op;
} else
else {
return SDValue(); return SDValue();
}
} }
SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {