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[AArch64] Regenerate SDIV tests
Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
This commit is contained in:
Simon Pilgrim
parent
119d3932c1
commit
4349dfb2f3
@ -1,56 +1,69 @@
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; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK,ISEL
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; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK,FAST
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define i32 @sdiv_i32_exact(i32 %a) {
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; CHECK-LABEL: sdiv_i32_exact
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; CHECK: asr {{w[0-9]+}}, w0, #3
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; CHECK-LABEL: sdiv_i32_exact:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w0, w0, #3
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; CHECK-NEXT: ret
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%1 = sdiv exact i32 %a, 8
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ret i32 %1
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}
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define i32 @sdiv_i32_pos(i32 %a) {
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; CHECK-LABEL: sdiv_i32_pos
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; CHECK: add [[REG1:w[0-9]+]], w0, #7
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
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; CHECK-NEXT: asr {{w[0-9]+}}, [[REG2]], #3
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; CHECK-LABEL: sdiv_i32_pos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #7 // =7
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: csel w8, w8, w0, lt
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; CHECK-NEXT: asr w0, w8, #3
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; CHECK-NEXT: ret
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%1 = sdiv i32 %a, 8
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ret i32 %1
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}
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define i32 @sdiv_i32_neg(i32 %a) {
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; CHECK-LABEL: sdiv_i32_neg
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; CHECK: add [[REG1:w[0-9]+]], w0, #7
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
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; CHECK-NEXT: neg {{w[0-9]+}}, [[REG2]], asr #3
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; CHECK-LABEL: sdiv_i32_neg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #7 // =7
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: csel w8, w8, w0, lt
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; CHECK-NEXT: neg w0, w8, asr #3
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; CHECK-NEXT: ret
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%1 = sdiv i32 %a, -8
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ret i32 %1
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}
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define i64 @sdiv_i64_exact(i64 %a) {
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; CHECK-LABEL: sdiv_i64_exact
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; CHECK: asr {{x[0-9]+}}, x0, #4
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; CHECK-LABEL: sdiv_i64_exact:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr x0, x0, #4
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; CHECK-NEXT: ret
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%1 = sdiv exact i64 %a, 16
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ret i64 %1
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}
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define i64 @sdiv_i64_pos(i64 %a) {
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; CHECK-LABEL: sdiv_i64_pos
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; CHECK: add [[REG1:x[0-9]+]], x0, #15
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; CHECK-NEXT: cmp x0, #0
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; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
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; CHECK-NEXT: asr {{x[0-9]+}}, [[REG2]], #4
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; CHECK-LABEL: sdiv_i64_pos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #15 // =15
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: asr x0, x8, #4
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; CHECK-NEXT: ret
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%1 = sdiv i64 %a, 16
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ret i64 %1
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}
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define i64 @sdiv_i64_neg(i64 %a) {
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; CHECK-LABEL: sdiv_i64_neg
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; CHECK: add [[REG1:x[0-9]+]], x0, #15
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; CHECK-NEXT: cmp x0, #0
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; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
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; CHECK-NEXT: neg {{x[0-9]+}}, [[REG2]], asr #4
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; CHECK-LABEL: sdiv_i64_neg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #15 // =15
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: neg x0, x8, asr #4
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; CHECK-NEXT: ret
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%1 = sdiv i64 %a, -16
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ret i64 %1
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}
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@ -1,73 +1,88 @@
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; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ISEL
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; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,FAST
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: test1
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; CHECK: add w8, w0, #7
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: asr w0, w8, #3
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #7 // =7
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: csel w8, w8, w0, lt
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; CHECK-NEXT: asr w0, w8, #3
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; CHECK-NEXT: ret
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%div = sdiv i32 %x, 8
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ret i32 %div
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2
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; CHECK: add w8, w0, #7
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: neg w0, w8, asr #3
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #7 // =7
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: csel w8, w8, w0, lt
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; CHECK-NEXT: neg w0, w8, asr #3
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; CHECK-NEXT: ret
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%div = sdiv i32 %x, -8
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ret i32 %div
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}
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define i32 @test3(i32 %x) {
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; CHECK-LABEL: test3
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; CHECK: add w8, w0, #31
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: asr w0, w8, #5
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #31 // =31
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: csel w8, w8, w0, lt
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; CHECK-NEXT: asr w0, w8, #5
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; CHECK-NEXT: ret
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%div = sdiv i32 %x, 32
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ret i32 %div
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}
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define i64 @test4(i64 %x) {
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; CHECK-LABEL: test4
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; CHECK: add x8, x0, #7
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #3
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; CHECK-LABEL: test4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #7 // =7
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: asr x0, x8, #3
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; CHECK-NEXT: ret
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%div = sdiv i64 %x, 8
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ret i64 %div
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}
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define i64 @test5(i64 %x) {
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; CHECK-LABEL: test5
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; CHECK: add x8, x0, #7
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: neg x0, x8, asr #3
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; CHECK-LABEL: test5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #7 // =7
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: neg x0, x8, asr #3
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; CHECK-NEXT: ret
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%div = sdiv i64 %x, -8
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ret i64 %div
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}
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define i64 @test6(i64 %x) {
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; CHECK-LABEL: test6
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; CHECK: add x8, x0, #63
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #6
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; CHECK-LABEL: test6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #63 // =63
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: asr x0, x8, #6
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; CHECK-NEXT: ret
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%div = sdiv i64 %x, 64
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ret i64 %div
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}
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define i64 @test7(i64 %x) {
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; CHECK-LABEL: test7
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; CHECK: orr [[REG:x[0-9]+]], xzr, #0xffffffffffff
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; CHECK: add x8, x0, [[REG]]
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #48
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; CHECK-LABEL: test7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x8, xzr, #0xffffffffffff
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; CHECK-NEXT: add x8, x0, x8
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: asr x0, x8, #48
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; CHECK-NEXT: ret
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%div = sdiv i64 %x, 281474976710656
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ret i64 %div
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}
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