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[Hexagon] Bit-based instruction simplification
Analyze bit patterns of operands and values of instructions to perform various simplifications, dead/redundant code elimination, etc. llvm-svn: 250868
This commit is contained in:
Krzysztof Parzyszek
parent
52f05db67a
commit
4625bb8dfb
@ -14,6 +14,7 @@ add_public_tablegen_target(HexagonCommonTableGen)
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add_llvm_target(HexagonCodeGen
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BitTracker.cpp
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HexagonAsmPrinter.cpp
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HexagonBitSimplify.cpp
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HexagonBitTracker.cpp
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HexagonCFGOptimizer.cpp
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HexagonCommonGEP.cpp
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2778
lib/Target/Hexagon/HexagonBitSimplify.cpp
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2778
lib/Target/Hexagon/HexagonBitSimplify.cpp
Normal file
File diff suppressed because it is too large
Load Diff
@ -62,6 +62,12 @@ static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
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static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
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cl::desc("Disable splitting double registers"));
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static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
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cl::Hidden, cl::desc("Bit simplification"));
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static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
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cl::Hidden, cl::desc("Loop rescheduling"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
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@ -84,6 +90,7 @@ SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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createVLIWMachineSched);
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namespace llvm {
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FunctionPass *createHexagonBitSimplify();
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FunctionPass *createHexagonCallFrameInformation();
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FunctionPass *createHexagonCFGOptimizer();
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FunctionPass *createHexagonCommonGEP();
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@ -99,6 +106,7 @@ namespace llvm {
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createHexagonLoopRescheduling();
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FunctionPass *createHexagonNewValueJump();
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FunctionPass *createHexagonOptimizeSZextends();
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FunctionPass *createHexagonPacketizer();
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@ -223,9 +231,15 @@ bool HexagonPassConfig::addInstSelector() {
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// Create logical operations on predicate registers.
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if (EnableGenPred)
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addPass(createHexagonGenPredicate(), false);
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// Rotate loops to expose bit-simplification opportunities.
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if (EnableLoopResched)
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addPass(createHexagonLoopRescheduling(), false);
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// Split double registers.
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if (!DisableHSDR)
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addPass(createHexagonSplitDoubleRegs());
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// Bit simplification.
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if (EnableBitSimplify)
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addPass(createHexagonBitSimplify(), false);
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addPass(createHexagonPeephole());
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printAndVerify("After hexagon peephole pass");
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if (EnableGenInsert)
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@ -1,4 +1,4 @@
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; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 < %s | FileCheck %s
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; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s
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; CHECK: r{{[0-9]+:[0-9]+}} = #1
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; CHECK: r{{[0-9]+:[0-9]+}} = #0
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53
test/CodeGen/Hexagon/bit-eval.ll
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53
test/CodeGen/Hexagon/bit-eval.ll
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@ -0,0 +1,53 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
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target triple = "hexagon"
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; CHECK-LABEL: test1:
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; CHECK: r0 = ##1073741824
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define i32 @test1() #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd(i32 2147483647, i32 0)
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ret i32 %0
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}
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; CHECK-LABEL: test2:
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; CHECK: r0 = ##1073741824
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define i32 @test2() #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 2147483647, i32 1)
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ret i32 %0
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}
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; CHECK-LABEL: test3:
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; CHECK: r1:0 = #1
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define i64 @test3() #0 {
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entry:
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%0 = tail call i64 @llvm.hexagon.S4.extractp(i64 -1, i32 63, i32 63)
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ret i64 %0
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}
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; CHECK-LABEL: test4:
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; CHECK: r0 = #1
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define i32 @test4() #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.S4.extract(i32 -1, i32 31, i32 31)
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ret i32 %0
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}
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; CHECK-LABEL: test5:
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; CHECK: r0 = ##-1073741569
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define i32 @test5() #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 255, i32 -2147483648, i32 1)
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ret i32 %0
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}
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declare i32 @llvm.hexagon.S2.asr.i.r.rnd(i32, i32) #0
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declare i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32, i32) #0
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declare i64 @llvm.hexagon.S4.extractp(i64, i32, i32) #0
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declare i32 @llvm.hexagon.S4.extract(i32, i32, i32) #0
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declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32) #0
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attributes #0 = { nounwind readnone }
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80
test/CodeGen/Hexagon/bit-loop.ll
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80
test/CodeGen/Hexagon/bit-loop.ll
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@ -0,0 +1,80 @@
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; RUN: llc < %s | FileCheck %s
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; CHECK-DAG: memh(r{{[0-9]+}}+#0) = r{{[0-9]+}}
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; CHECK-DAG: memh(r{{[0-9]+}}+#2) = r{{[0-9]+}}.h
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; CHECK-DAG: memh(r{{[0-9]+}}+#4) = r{{[0-9]+}}
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; CHECK-DAG: memh(r{{[0-9]+}}+#6) = r{{[0-9]+}}.h
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target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @foo(i64* nocapture readonly %r64, i16 zeroext %n, i16 zeroext %s, i64* nocapture %p64) #0 {
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entry:
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%conv = zext i16 %n to i32
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%cmp = icmp eq i16 %n, 0
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br i1 %cmp, label %for.end, label %for.body.preheader
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for.body.preheader: ; preds = %entry
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%0 = load i64, i64* %r64, align 8, !tbaa !1
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%v.sroa.0.0.extract.trunc = trunc i64 %0 to i16
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%v.sroa.4.0.extract.shift = lshr i64 %0, 16
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%v.sroa.4.0.extract.trunc = trunc i64 %v.sroa.4.0.extract.shift to i16
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%v.sroa.5.0.extract.shift = lshr i64 %0, 32
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%v.sroa.5.0.extract.trunc = trunc i64 %v.sroa.5.0.extract.shift to i16
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%v.sroa.6.0.extract.shift = lshr i64 %0, 48
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%v.sroa.6.0.extract.trunc = trunc i64 %v.sroa.6.0.extract.shift to i16
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%1 = bitcast i64* %p64 to i16*
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%conv2 = zext i16 %s to i32
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%add.ptr = getelementptr inbounds i16, i16* %1, i32 %conv2
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%add.ptr.sum = add nuw nsw i32 %conv2, 1
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%add.ptr3 = getelementptr inbounds i16, i16* %1, i32 %add.ptr.sum
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%add.ptr.sum50 = add nuw nsw i32 %conv2, 2
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%add.ptr4 = getelementptr inbounds i16, i16* %1, i32 %add.ptr.sum50
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%add.ptr.sum51 = add nuw nsw i32 %conv2, 3
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%add.ptr5 = getelementptr inbounds i16, i16* %1, i32 %add.ptr.sum51
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%add.ptr11.phi = phi i16* [ %add.ptr11.inc, %for.body ], [ %add.ptr, %for.body.preheader ]
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%add.ptr16.phi = phi i16* [ %add.ptr16.inc, %for.body ], [ %add.ptr3, %for.body.preheader ]
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%add.ptr21.phi = phi i16* [ %add.ptr21.inc, %for.body ], [ %add.ptr4, %for.body.preheader ]
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%add.ptr26.phi = phi i16* [ %add.ptr26.inc, %for.body ], [ %add.ptr5, %for.body.preheader ]
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%i.058.pmt = phi i32 [ %inc.pmt, %for.body ], [ 0, %for.body.preheader ]
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%v.sroa.0.157 = phi i16 [ %v.sroa.0.0.extract.trunc34, %for.body ], [ %v.sroa.0.0.extract.trunc, %for.body.preheader ]
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%v.sroa.4.156 = phi i16 [ %v.sroa.4.0.extract.trunc36, %for.body ], [ %v.sroa.4.0.extract.trunc, %for.body.preheader ]
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%v.sroa.5.155 = phi i16 [ %v.sroa.5.0.extract.trunc38, %for.body ], [ %v.sroa.5.0.extract.trunc, %for.body.preheader ]
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%v.sroa.6.154 = phi i16 [ %v.sroa.6.0.extract.trunc40, %for.body ], [ %v.sroa.6.0.extract.trunc, %for.body.preheader ]
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%q64.153.pn = phi i64* [ %q64.153, %for.body ], [ %r64, %for.body.preheader ]
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%q64.153 = getelementptr inbounds i64, i64* %q64.153.pn, i32 1
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store i16 %v.sroa.0.157, i16* %add.ptr11.phi, align 2, !tbaa !5
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store i16 %v.sroa.4.156, i16* %add.ptr16.phi, align 2, !tbaa !5
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store i16 %v.sroa.5.155, i16* %add.ptr21.phi, align 2, !tbaa !5
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store i16 %v.sroa.6.154, i16* %add.ptr26.phi, align 2, !tbaa !5
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%2 = load i64, i64* %q64.153, align 8, !tbaa !1
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%v.sroa.0.0.extract.trunc34 = trunc i64 %2 to i16
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%v.sroa.4.0.extract.shift35 = lshr i64 %2, 16
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%v.sroa.4.0.extract.trunc36 = trunc i64 %v.sroa.4.0.extract.shift35 to i16
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%v.sroa.5.0.extract.shift37 = lshr i64 %2, 32
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%v.sroa.5.0.extract.trunc38 = trunc i64 %v.sroa.5.0.extract.shift37 to i16
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%v.sroa.6.0.extract.shift39 = lshr i64 %2, 48
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%v.sroa.6.0.extract.trunc40 = trunc i64 %v.sroa.6.0.extract.shift39 to i16
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%inc.pmt = add i32 %i.058.pmt, 1
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%cmp8 = icmp slt i32 %inc.pmt, %conv
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%add.ptr11.inc = getelementptr i16, i16* %add.ptr11.phi, i32 4
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%add.ptr16.inc = getelementptr i16, i16* %add.ptr16.phi, i32 4
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%add.ptr21.inc = getelementptr i16, i16* %add.ptr21.phi, i32 4
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%add.ptr26.inc = getelementptr i16, i16* %add.ptr26.phi, i32 4
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br i1 %cmp8, label %for.body, label %for.end
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for.end: ; preds = %for.body, %entry
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ret void
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}
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attributes #0 = { nounwind }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"long long", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = !{!6, !6, i64 0}
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!6 = !{!"short", !3, i64 0}
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@ -1,4 +1,4 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-bit=0 < %s | FileCheck %s
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; Optimized bitwise operations.
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define i32 @my_clrbit(i32 %x) nounwind {
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@ -1,4 +1,4 @@
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; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=hexagonv5 < %s | FileCheck %s
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; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=hexagonv5 -hexagon-bit=0 < %s | FileCheck %s
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; Optimize fabsf to clrbit in V5.
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; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
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@ -1,4 +1,4 @@
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; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 < %s | FileCheck %s
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; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s
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; CHECK: r{{[0-9]+:[0-9]+}} = #1
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; CHECK: r{{[0-9]+:[0-9]+}} = #0
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