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[PowerPC] Implement Vector String Isolate Builtins in Clang/LLVM
This patch implements the vector string isolate (predicate and non-predicate versions) builtins. The predicate builtins are custom selected within PPCISelDAGToDAG. Differential Revision: https://reviews.llvm.org/D87671
This commit is contained in:
Amy Kwan
parent
8864893cb8
commit
4778b6148c
@ -501,6 +501,25 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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// P10 Vector String Isolate Intrinsics.
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def int_ppc_altivec_vstribr : GCCBuiltin<"__builtin_altivec_vstribr">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
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def int_ppc_altivec_vstribl : GCCBuiltin<"__builtin_altivec_vstribl">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
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def int_ppc_altivec_vstrihr : GCCBuiltin<"__builtin_altivec_vstrihr">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
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def int_ppc_altivec_vstrihl : GCCBuiltin<"__builtin_altivec_vstrihl">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
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// Predicate Intrinsics: The first operand specifies interpretation of CR6.
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def int_ppc_altivec_vstribr_p : GCCBuiltin<"__builtin_altivec_vstribr_p">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_v16i8_ty], [IntrNoMem]>;
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def int_ppc_altivec_vstribl_p : GCCBuiltin<"__builtin_altivec_vstribl_p">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_v16i8_ty], [IntrNoMem]>;
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def int_ppc_altivec_vstrihr_p : GCCBuiltin<"__builtin_altivec_vstrihr_p">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_v8i16_ty], [IntrNoMem]>;
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def int_ppc_altivec_vstrihl_p : GCCBuiltin<"__builtin_altivec_vstrihl_p">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_v8i16_ty], [IntrNoMem]>;
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// P10 Vector Centrifuge Builtin.
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def int_ppc_altivec_vcfuged : GCCBuiltin<"__builtin_altivec_vcfuged">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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@ -43,6 +43,7 @@
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/IntrinsicsPowerPC.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/CodeGen.h"
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@ -4677,6 +4678,45 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
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}
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break;
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case ISD::INTRINSIC_WO_CHAIN: {
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if (!PPCSubTarget->isISA3_1())
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break;
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unsigned Opcode = 0;
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switch (N->getConstantOperandVal(0)) {
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default:
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break;
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case Intrinsic::ppc_altivec_vstribr_p:
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Opcode = PPC::VSTRIBR_rec;
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break;
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case Intrinsic::ppc_altivec_vstribl_p:
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Opcode = PPC::VSTRIBL_rec;
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break;
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case Intrinsic::ppc_altivec_vstrihr_p:
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Opcode = PPC::VSTRIHR_rec;
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break;
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case Intrinsic::ppc_altivec_vstrihl_p:
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Opcode = PPC::VSTRIHL_rec;
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break;
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}
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if (!Opcode)
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break;
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// Generate the appropriate vector string isolate intrinsic to match.
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EVT VTs[] = {MVT::v16i8, MVT::Glue};
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SDValue VecStrOp =
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SDValue(CurDAG->getMachineNode(Opcode, dl, VTs, N->getOperand(2)), 0);
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// Vector string isolate instructions update the EQ bit of CR6.
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// Generate a SETBC instruction to extract the bit and place it in a GPR.
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SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_eq, dl, MVT::i32);
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SDValue CR6Reg = CurDAG->getRegister(PPC::CR6, MVT::i32);
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SDValue CRBit = SDValue(
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CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::i1,
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CR6Reg, SubRegIdx, VecStrOp.getValue(1)),
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0);
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CurDAG->SelectNodeTo(N, PPC::SETBC, MVT::i32, CRBit);
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return;
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}
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case ISD::SETCC:
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case ISD::STRICT_FSETCC:
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case ISD::STRICT_FSETCCS:
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@ -1020,13 +1020,21 @@ let Predicates = [IsISA3_1] in {
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v16i8:$VRB,
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i32:$SH))]>;
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defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB),
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"vstribr", "$vT, $vB", IIC_VecGeneral, []>;
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"vstribr", "$vT, $vB", IIC_VecGeneral,
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[(set v16i8:$vT,
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(int_ppc_altivec_vstribr v16i8:$vB))]>;
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defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB),
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"vstribl", "$vT, $vB", IIC_VecGeneral, []>;
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"vstribl", "$vT, $vB", IIC_VecGeneral,
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[(set v16i8:$vT,
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(int_ppc_altivec_vstribl v16i8:$vB))]>;
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defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB),
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"vstrihr", "$vT, $vB", IIC_VecGeneral, []>;
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"vstrihr", "$vT, $vB", IIC_VecGeneral,
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[(set v8i16:$vT,
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(int_ppc_altivec_vstrihr v8i16:$vB))]>;
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defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB),
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"vstrihl", "$vT, $vB", IIC_VecGeneral, []>;
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"vstrihl", "$vT, $vB", IIC_VecGeneral,
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[(set v8i16:$vT,
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(int_ppc_altivec_vstrihl v8i16:$vB))]>;
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def VINSW :
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VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
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"vinsw $vD, $rB, $UIM", IIC_VecGeneral,
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@ -2,6 +2,9 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; These test cases aim to test the vector string isolate builtins on Power10.
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@ -27,3 +30,97 @@ entry:
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%tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8> %a, i32 %n)
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ret <16 x i8> %tmp
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}
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declare <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8>)
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declare <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>)
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declare <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16>)
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declare <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16>)
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declare i32 @llvm.ppc.altivec.vstribr.p(i32, <16 x i8>)
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declare i32 @llvm.ppc.altivec.vstribl.p(i32, <16 x i8>)
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declare i32 @llvm.ppc.altivec.vstrihr.p(i32, <8 x i16>)
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declare i32 @llvm.ppc.altivec.vstrihl.p(i32, <8 x i16>)
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define <16 x i8> @test_vstribr(<16 x i8> %a) {
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; CHECK-LABEL: test_vstribr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstribr v2, v2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8> %a)
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ret <16 x i8> %tmp
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}
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define <16 x i8> @test_vstribl(<16 x i8> %a) {
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; CHECK-LABEL: test_vstribl:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstribl v2, v2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>%a)
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ret <16 x i8> %tmp
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}
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define <8 x i16> @test_vstrihr(<8 x i16> %a) {
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; CHECK-LABEL: test_vstrihr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstrihr v2, v2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16> %a)
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ret <8 x i16> %tmp
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}
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define <8 x i16> @test_vstrihl(<8 x i16> %a) {
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; CHECK-LABEL: test_vstrihl:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstrihl v2, v2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16> %a)
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ret <8 x i16> %tmp
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}
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define i32 @test_vstribr_p(<16 x i8> %a) {
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; CHECK-LABEL: test_vstribr_p:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstribr. v2, v2
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; CHECK-NEXT: setbc r3, 4*cr6+eq
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i32 @llvm.ppc.altivec.vstribr.p(i32 1, <16 x i8> %a)
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ret i32 %tmp
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}
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define i32 @test_vstribl_p(<16 x i8> %a) {
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; CHECK-LABEL: test_vstribl_p:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstribl. v2, v2
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; CHECK-NEXT: setbc r3, 4*cr6+eq
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i32 @llvm.ppc.altivec.vstribl.p(i32 1, <16 x i8> %a)
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ret i32 %tmp
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}
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define i32 @test_vstrihr_p(<8 x i16> %a) {
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; CHECK-LABEL: test_vstrihr_p:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstrihr. v2, v2
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; CHECK-NEXT: setbc r3, 4*cr6+eq
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i32 @llvm.ppc.altivec.vstrihr.p(i32 1, <8 x i16> %a)
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ret i32 %tmp
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}
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define i32 @test_vstrihl_p(<8 x i16> %a) {
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; CHECK-LABEL: test_vstrihl_p:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstrihl. v2, v2
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; CHECK-NEXT: setbc r3, 4*cr6+eq
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i32 @llvm.ppc.altivec.vstrihl.p(i32 1, <8 x i16> %a)
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ret i32 %tmp
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}
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