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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00

Give helpers internal linkage. NFC.

This commit is contained in:
Benjamin Kramer 2020-05-19 22:16:15 +02:00
parent 9846f00871
commit 48794a1de1
4 changed files with 11 additions and 7 deletions

View File

@ -1246,12 +1246,12 @@ static Value *getAISize(LLVMContext &Context, Value *Amt) {
return Amt;
}
Align computeAllocaDefaultAlign(Type *Ty, BasicBlock *BB) {
static Align computeAllocaDefaultAlign(Type *Ty, BasicBlock *BB) {
const DataLayout &DL = BB->getModule()->getDataLayout();
return DL.getPrefTypeAlign(Ty);
}
Align computeAllocaDefaultAlign(Type *Ty, Instruction *I) {
static Align computeAllocaDefaultAlign(Type *Ty, Instruction *I) {
return computeAllocaDefaultAlign(Ty, I->getParent());
}
@ -1333,12 +1333,12 @@ void LoadInst::AssertOK() {
"Alignment required for atomic load");
}
Align computeLoadStoreDefaultAlign(Type *Ty, BasicBlock *BB) {
static Align computeLoadStoreDefaultAlign(Type *Ty, BasicBlock *BB) {
const DataLayout &DL = BB->getModule()->getDataLayout();
return DL.getABITypeAlign(Ty);
}
Align computeLoadStoreDefaultAlign(Type *Ty, Instruction *I) {
static Align computeLoadStoreDefaultAlign(Type *Ty, Instruction *I) {
return computeLoadStoreDefaultAlign(Ty, I->getParent());
}

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@ -960,9 +960,9 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
// S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad)
static const int CMSE_FP_SAVE_SIZE = 136;
void determineGPRegsToClear(const MachineInstr &MI,
const std::initializer_list<unsigned> &Regs,
SmallVectorImpl<unsigned> &ClearRegs) {
static void determineGPRegsToClear(const MachineInstr &MI,
const std::initializer_list<unsigned> &Regs,
SmallVectorImpl<unsigned> &ClearRegs) {
SmallVector<unsigned, 4> OpRegs;
for (const MachineOperand &Op : MI.operands()) {
if (!Op.isReg() || !Op.isUse())

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@ -3330,6 +3330,7 @@ static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
}
#endif
namespace {
/// This is a helper class for lowering variable arguments parameters.
class VarArgsLoweringHelper {
public:
@ -3367,6 +3368,7 @@ private:
CallingConv::ID CallConv;
CCState &CCInfo;
};
} // namespace
void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
SDValue &Chain, unsigned StackSize) {

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@ -447,6 +447,7 @@ PreservedAnalyses AssumeSimplifyPass::run(Function &F,
return PreservedAnalyses::all();
}
namespace {
class AssumeSimplifyPassLegacyPass : public FunctionPass {
public:
static char ID;
@ -469,6 +470,7 @@ public:
AU.setPreservesAll();
}
};
} // namespace
char AssumeSimplifyPassLegacyPass::ID = 0;