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[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
This commit is contained in:
Nemanja Ivanovic
parent
78be6742d5
commit
48de75d5c6
@ -3276,8 +3276,22 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
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ShiftR, ShiftL, SubtractCarry), 0);
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}
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case ISD::SETGT: {
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// {subc.reg, subc.CA} = (subcarry %b, %a)
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// (zext (setcc %a, %b, setgt)) ->
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// (xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
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// (zext (setcc %a, 0, setgt)) -> (lshr (nor (add %a, -1), %a), 63)
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if (IsRHSNegOne)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
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if (IsRHSZero) {
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SDValue Addi =
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SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
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getI64Imm(~0ULL, dl)), 0);
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SDValue Nor =
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SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0);
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return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor,
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getI64Imm(1, dl),
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getI64Imm(63, dl)), 0);
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}
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std::swap(LHS, RHS);
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ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
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IsRHSZero = RHSConst && RHSConst->isNullValue();
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@ -3285,9 +3299,31 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
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LLVM_FALLTHROUGH;
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}
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case ISD::SETLT: {
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// {subc.reg, subc.CA} = (subcarry %a, %b)
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// (zext (setcc %a, %b, setlt)) ->
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// (xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
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// (zext (setcc %a, 0, setlt)) -> (lshr %a, 63)
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if (IsRHSOne)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
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return SDValue();
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if (IsRHSZero)
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return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
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getI64Imm(1, dl),
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getI64Imm(63, dl)), 0);
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SDValue SRADINode =
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SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
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LHS, getI64Imm(63, dl)), 0);
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SDValue SRDINode =
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SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
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RHS, getI64Imm(1, dl),
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getI64Imm(63, dl)), 0);
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SDValue SUBFC8Carry =
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SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
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RHS, LHS), 1);
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SDValue ADDE8Node =
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SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
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SRDINode, SRADINode, SUBFC8Carry), 0);
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return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
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ADDE8Node, getI64Imm(1, dl)), 0);
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}
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}
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}
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@ -3362,8 +3398,21 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
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return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0);
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}
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case ISD::SETGT: {
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// {subc.reg, subc.CA} = (subcarry %b, %a)
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// (zext (setcc %a, %b, setgt)) ->
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// -(xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
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// (zext (setcc %a, 0, setgt)) -> (ashr (nor (add %a, -1), %a), 63)
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if (IsRHSNegOne)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
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if (IsRHSZero) {
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SDValue Add =
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SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
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getI64Imm(-1, dl)), 0);
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SDValue Nor =
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SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0);
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return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor,
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getI64Imm(63, dl)), 0);
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}
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std::swap(LHS, RHS);
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ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
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IsRHSZero = RHSConst && RHSConst->isNullValue();
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@ -3371,9 +3420,34 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
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LLVM_FALLTHROUGH;
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}
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case ISD::SETLT: {
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// {subc.reg, subc.CA} = (subcarry %a, %b)
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// (zext (setcc %a, %b, setlt)) ->
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// -(xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
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// (zext (setcc %a, 0, setlt)) -> (ashr %a, 63)
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if (IsRHSOne)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
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return SDValue();
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if (IsRHSZero) {
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return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS,
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getI64Imm(63, dl)), 0);
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}
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SDValue SRADINode =
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SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
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LHS, getI64Imm(63, dl)), 0);
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SDValue SRDINode =
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SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
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RHS, getI64Imm(1, dl),
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getI64Imm(63, dl)), 0);
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SDValue SUBFC8Carry =
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SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
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RHS, LHS), 1);
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SDValue ADDE8Node =
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SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64,
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SRDINode, SRADINode, SUBFC8Carry), 0);
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SDValue XORI8Node =
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SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
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ADDE8Node, getI64Imm(1, dl)), 0);
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return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
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XORI8Node), 0);
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}
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}
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}
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@ -127,7 +127,7 @@ entry:
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ret i64 %conv1
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; CHECK: @foo2l
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; CHECK: sld. 4, 3, 4
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; CHECK: sld 4, 3, 4
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; CHECK: std 4, 0(5)
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}
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134
test/CodeGen/PowerPC/testComparesigtsll.ll
Normal file
134
test/CodeGen/PowerPC/testComparesigtsll.ll
Normal file
@ -0,0 +1,134 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i64 0, align 8
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
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; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
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; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: xori r3, [[REG4]], 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_sext:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
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; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
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; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK-NEXT: neg r3, [[REG5]]
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; FIXME
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_z(i64 %a) {
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; CHECK-LABEL: test_igtsll_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: nor r3, r4, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_sext_z(i64 %a) {
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; CHECK-LABEL: test_igtsll_sext_z:
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; CHECK: addi [[REG1:r[0-9]+]], r3, -1
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; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3
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; CHECK-NEXT: sradi r3, [[REG2]], 63
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entry:
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%cmp = icmp sgt i64 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
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; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
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; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
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; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK-NOT: neg
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_sext_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
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; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
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; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
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; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK: neg {{r[0-9]+}}, [[REG5]]
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; FIXME
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_z_store(i64 %a) {
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; CHECK-LABEL: test_igtsll_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: addi r5, r3, -1
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: nor r3, r5, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_igtsll_sext_z_store:
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; CHECK: addi [[REG1:r[0-9]+]], r3, -1
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; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3
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; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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99
test/CodeGen/PowerPC/testComparesiltsll.ll
Normal file
99
test/CodeGen/PowerPC/testComparesiltsll.ll
Normal file
@ -0,0 +1,99 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i64 0, align 8
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_iltsll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_iltsll:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
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; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
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; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: xori r3, [[REG4]], 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_iltsll_sext:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
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; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
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; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK-NEXT: neg r3, [[REG5]]
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_iltsll_sext_z(i64 %a) {
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; CHECK-LABEL: test_iltsll_sext_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind
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define void @test_iltsll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_iltsll_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
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; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
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; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
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; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK-NOT: neg {{r[0-9]+}}, [[REG5]]
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entry:
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%cmp = icmp slt i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_iltsll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_iltsll_sext_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
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; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
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; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
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; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
|
||||
; CHECK: neg {{r[0-9]+}}, [[REG5]]
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_iltsll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_iltsll_sext_z_store:
|
||||
; CHECK: sradi r3, r3, 63
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, 0
|
||||
%conv2 = sext i1 %cmp to i64
|
||||
store i64 %conv2, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
134
test/CodeGen/PowerPC/testComparesllgtsll.ll
Normal file
134
test/CodeGen/PowerPC/testComparesllgtsll.ll
Normal file
@ -0,0 +1,134 @@
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llgtsll(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llgtsll:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
|
||||
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
|
||||
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
|
||||
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK-NEXT: xori r3, [[REG4]], 1
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llgtsll_sext:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
|
||||
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
|
||||
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
|
||||
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
|
||||
; CHECK-NEXT: neg r3, [[REG5]]
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; FIXME
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llgtsll_z(i64 %a) {
|
||||
; CHECK-LABEL: test_llgtsll_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addi r4, r3, -1
|
||||
; CHECK-NEXT: nor r3, r4, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, 0
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llgtsll_sext_z(i64 %a) {
|
||||
; CHECK-LABEL: test_llgtsll_sext_z:
|
||||
; CHECK: addi [[REG1:r[0-9]+]], r3, -1
|
||||
; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3
|
||||
; CHECK-NEXT: sradi r3, [[REG2]], 63
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, 0
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llgtsll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llgtsll_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
|
||||
; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
|
||||
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
|
||||
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
|
||||
; CHECK-NOT: neg
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llgtsll_sext_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
|
||||
; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
|
||||
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
|
||||
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
|
||||
; CHECK: neg {{r[0-9]+}}, [[REG5]]
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llgtsll_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_llgtsll_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: addi r5, r3, -1
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: nor r3, r5, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, 0
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llgtsll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_llgtsll_sext_z_store:
|
||||
; CHECK: addi [[REG1:r[0-9]+]], r3, -1
|
||||
; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3
|
||||
; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, 0
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
99
test/CodeGen/PowerPC/testComparesllltsll.ll
Normal file
99
test/CodeGen/PowerPC/testComparesllltsll.ll
Normal file
@ -0,0 +1,99 @@
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llltsll(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llltsll:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
|
||||
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
|
||||
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
|
||||
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK-NEXT: xori r3, [[REG4]], 1
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llltsll_sext(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llltsll_sext:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
|
||||
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
|
||||
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
|
||||
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
|
||||
; CHECK-NEXT: neg r3, [[REG5]]
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llltsll_sext_z(i64 %a) {
|
||||
; CHECK-LABEL: test_llltsll_sext_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi r3, r3, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, 0
|
||||
%sub = sext i1 %cmp to i64
|
||||
ret i64 %sub
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llltsll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llltsll_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
|
||||
; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
|
||||
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
|
||||
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
|
||||
; CHECK-NOT: neg
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llltsll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llltsll_sext_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
|
||||
; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
|
||||
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
|
||||
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
|
||||
; CHECK: neg {{r[0-9]+}}, [[REG5]]
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llltsll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_llltsll_sext_z_store:
|
||||
; CHECK: sradi r3, r3, 63
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, 0
|
||||
%sub = sext i1 %cmp to i64
|
||||
store i64 %sub, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user