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AArch64: Enable AES instruction fusion on Cyclone.
Note that cyclone itself doesn't fuse, but newer apple chips do and we are using cyclone as the default when targeting apple OSes. The current code also does not capture all fusion patterns of apple CPUs yet; I am still looking for ways to refactor the code nicely to extend it. llvm-svn: 316036
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@ -274,14 +274,17 @@ def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
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FeaturePerfMon
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]>;
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// Note that cyclone does not fuse AES instructions, but newer apple chips do
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// perform the fusion and cyclone is used by default when targetting apple OSes.
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def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
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"Cyclone", [
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FeatureAlternateSExtLoadCVTF32Pattern,
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FeatureArithmeticBccFusion,
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FeatureArithmeticCbzFusion,
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FeatureCrypto,
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FeatureDisableLatencySchedHeuristic,
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FeatureFPARMv8,
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FeatureArithmeticBccFusion,
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FeatureArithmeticCbzFusion,
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FeatureFuseAES,
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FeatureNEON,
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FeaturePerfMon,
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FeatureSlowMisaligned128Store,
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