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[ARM] Fixed an assumption of power-of-2 vector MVT
I am about to introduce some non-power-of-2 width vector MVTs. This commit fixes a power-of-2 assumption that my forthcoming change would otherwise break, as shown by test/CodeGen/ARM/vcvt_combine.ll and vdiv_combine.ll. Differential Revision: https://reviews.llvm.org/D58927 Change-Id: I56a282e365d3874ab0621e5bdef98a612f702317 llvm-svn: 356341
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@ -12154,11 +12154,11 @@ static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
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MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
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uint32_t IntBits = IntTy.getSizeInBits();
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unsigned NumLanes = Op.getValueType().getVectorNumElements();
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if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
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if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) {
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// These instructions only exist converting from f32 to i32. We can handle
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// smaller integers by generating an extra truncate, but larger ones would
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// be lossy. We also can't handle more then 4 lanes, since these intructions
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// only support v2i32/v4i32 types.
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// be lossy. We also can't handle anything other than 2 or 4 lanes, since
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// these intructions only support v2i32/v4i32 types.
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return SDValue();
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}
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@ -12212,11 +12212,11 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
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MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
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uint32_t IntBits = IntTy.getSizeInBits();
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unsigned NumLanes = Op.getValueType().getVectorNumElements();
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if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
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if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) {
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// These instructions only exist converting from i32 to f32. We can handle
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// smaller integers by generating an extra extend, but larger ones would
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// be lossy. We also can't handle more then 4 lanes, since these intructions
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// only support v2i32/v4i32 types.
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// be lossy. We also can't handle anything other than 2 or 4 lanes, since
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// these intructions only support v2i32/v4i32 types.
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return SDValue();
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}
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