RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 12:41:49 +01:00
Code Issues Projects Releases Wiki Activity

OpaquePtr: Bulk update tests to use typed byval

Browse Source 
Upgrade of the IR text tests should be the only thing blocking making
typed byval mandatory. Partially done through regex and partially
manual.
This commit is contained in:
Matt Arsenault 2020-11-20 10:52:27 -05:00
parent a385d0e6a4
commit 4bf7d5872e
272 changed files with 957 additions and 957 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
test/Analysis/BasicAA/2008-04-15-Byval.ll
View File

@ -4,13 +4,13 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
target triple = "i386-apple-darwin8"
%struct.x = type { [4 x i32] }
define void @foo(%struct.x* byval align 4 %X) nounwind {
define void @foo(%struct.x* byval(%struct.x) align 4 %X) nounwind {
; CHECK: store i32 2, i32* %tmp1
entry:
%tmp = getelementptr %struct.x, %struct.x* %X, i32 0, i32 0 ; <[4 x i32]*> [#uses=1]
%tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3 ; <i32*> [#uses=1]
store i32 2, i32* %tmp1, align 4
%tmp2 = call i32 (...) @bar( %struct.x* byval align 4 %X ) nounwind ; <i32> [#uses=0]
%tmp2 = call i32 (...) @bar(%struct.x* byval(%struct.x) align 4 %X ) nounwind ; <i32> [#uses=0]
br label %return
return: ; preds = %entry
ret void

2
test/Analysis/BasicAA/byval.ll
View File

@ -4,7 +4,7 @@ target triple = "i686-apple-darwin8"
%struct.x = type { i32, i32, i32, i32 }
@g = weak global i32 0 ; <i32*> [#uses=1]
define i32 @foo(%struct.x* byval %a) nounwind {
define i32 @foo(%struct.x* byval(%struct.x) %a) nounwind {
; CHECK: ret i32 1
%tmp1 = tail call i32 (...) @bar( %struct.x* %a ) nounwind ; <i32> [#uses=0]
%tmp2 = getelementptr %struct.x, %struct.x* %a, i32 0, i32 0 ; <i32*> [#uses=2]

8
test/Analysis/BasicAA/dereferenceable.ll
View File

@ -24,7 +24,7 @@ bb:
ret i32 %tmp
}
define i32 @byval_and_deref_arg_1(i32* byval %obj, i64* dereferenceable(8) %arg) {
define i32 @byval_and_deref_arg_1(i32* byval(i32) %obj, i64* dereferenceable(8) %arg) {
; CHECK: Function: byval_and_deref_arg_1: 2 pointers, 0 call sites
; CHECK-NEXT: NoAlias: i32* %obj, i64* %arg
bb:
@ -34,7 +34,7 @@ bb:
ret i32 %tmp
}
define i32 @byval_and_deref_arg_2(i32* byval %obj, i32* dereferenceable(8) %arg) {
define i32 @byval_and_deref_arg_2(i32* byval(i32) %obj, i32* dereferenceable(8) %arg) {
; CHECK: Function: byval_and_deref_arg_2: 2 pointers, 0 call sites
; CHECK-NEXT: NoAlias: i32* %arg, i32* %obj
bb:
@ -98,7 +98,7 @@ bb:
ret i32 %tmp
}
define i32 @byval_and_deref_arg_non_deref_1(i32* byval %obj, i64* dereferenceable(2) %arg) {
define i32 @byval_and_deref_arg_non_deref_1(i32* byval(i32) %obj, i64* dereferenceable(2) %arg) {
; CHECK: Function: byval_and_deref_arg_non_deref_1: 2 pointers, 0 call sites
; CHECK-NEXT: NoAlias: i32* %obj, i64* %arg
bb:
@ -108,7 +108,7 @@ bb:
ret i32 %tmp
}
define i32 @byval_and_deref_arg_non_deref_2(i32* byval %obj, i32* dereferenceable(2) %arg) {
define i32 @byval_and_deref_arg_non_deref_2(i32* byval(i32) %obj, i32* dereferenceable(2) %arg) {
; CHECK: Function: byval_and_deref_arg_non_deref_2: 2 pointers, 0 call sites
; CHECK-NEXT: NoAlias: i32* %arg, i32* %obj
bb:

6
test/Analysis/BasicAA/tail-byval.ll
View File

@ -1,15 +1,15 @@
; RUN: opt -basic-aa -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s
declare void @takebyval(i32* byval %p)
declare void @takebyval(i32* byval(i32) %p)
define i32 @tailbyval() {
entry:
%p = alloca i32
store i32 42, i32* %p
tail call void @takebyval(i32* byval %p)
tail call void @takebyval(i32* byval(i32) %p)
%rv = load i32, i32* %p
ret i32 %rv
}
; FIXME: This should be Just Ref.
; CHECK-LABEL: Function: tailbyval: 1 pointers, 1 call sites
; CHECK-NEXT: Both ModRef: Ptr: i32* %p <-> tail call void @takebyval(i32* byval %p)
; CHECK-NEXT: Both ModRef: Ptr: i32* %p <-> tail call void @takebyval(i32* byval(i32) %p)

2
test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll
View File

@ -32,7 +32,7 @@ define amdgpu_kernel void @test_amdgpu_kernel([4 x <16 x i8>] addrspace(4)* byre
; CHECK: DIVERGENT:
; CHECK: DIVERGENT:
; CHECK: DIVERGENT:
define void @test_c([4 x <16 x i8>] addrspace(5)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
define void @test_c([4 x <16 x i8>] addrspace(5)* byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
ret void
}

2
test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll
View File

@ -32,7 +32,7 @@ define amdgpu_kernel void @test_amdgpu_kernel([4 x <16 x i8>] addrspace(4)* byre
; CHECK: DIVERGENT:
; CHECK: DIVERGENT:
; CHECK: DIVERGENT:
define void @test_c([4 x <16 x i8>] addrspace(4)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
define void @test_c([4 x <16 x i8>] addrspace(4)* byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
ret void
}

6
test/Analysis/Lint/noalias-byval.ll
View File

@ -26,7 +26,7 @@ entry:
; CHECK: Unusual: noalias argument aliases another argument
; CHECK-NEXT: call void @f1(%s* sret %c, %s* %c)
declare void @f3(%s* noalias nocapture sret, %s* byval nocapture readnone)
declare void @f3(%s* noalias nocapture sret, %s* byval(%s) nocapture readnone)
define void @f4() {
entry:
@ -35,7 +35,7 @@ entry:
%0 = bitcast %s* %c to i8*
%1 = bitcast %s* %tmp to i8*
call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 1, i1 false)
call void @f3(%s* sret %c, %s* byval %c)
call void @f3(%s* sret %c, %s* byval(%s) %c)
ret void
}
@ -43,6 +43,6 @@ entry:
; noalias, since the other one is byval, effectively copying the data to the
; stack instead of passing the pointer itself.
; CHECK-NOT: Unusual: noalias argument aliases another argument
; CHECK-NOT: call void @f3(%s* sret %c, %s* %c)
; CHECK-NOT: call void @f3(%s* sret %c, %s* byval(%s) %c)
attributes #0 = { argmemonly nounwind }

6
test/Analysis/Lint/tail-call-byval.ll
View File

@ -15,12 +15,12 @@ entry:
; CHECK: Undefined behavior: Call with "tail" keyword references alloca
; CHECK-NEXT: tail call void @f1(%s* %c)
declare void @f3(%s* byval)
declare void @f3(%s* byval(%s))
define void @f4() {
entry:
%c = alloca %s
tail call void @f3(%s* byval %c)
tail call void @f3(%s* byval(%s) %c)
ret void
}
@ -28,6 +28,6 @@ entry:
; byval, effectively copying the data to the stack instead of leaking the
; pointer itself.
; CHECK-NOT: Undefined behavior: Call with "tail" keyword references alloca
; CHECK-NOT: tail call void @f3(%s* byval %c)
; CHECK-NOT: tail call void @f3(%s* byval(%s) %c)

12
test/Analysis/StackSafetyAnalysis/local.ll
View File

@ -445,7 +445,7 @@ entry:
ret void
}
define void @ByVal(i16* byval %p) {
define void @ByVal(i16* byval(i16) %p) {
; CHECK-LABEL: @ByVal dso_preemptable{{$}}
; CHECK-NEXT: args uses:
; CHECK-NEXT: allocas uses:
@ -463,16 +463,16 @@ define void @TestByVal() {
; CHECK-EMPTY:
entry:
%x = alloca i16, align 4
call void @ByVal(i16* byval %x)
call void @ByVal(i16* byval(i16) %x)
%y = alloca i64, align 4
%y1 = bitcast i64* %y to i16*
call void @ByVal(i16* byval %y1)
call void @ByVal(i16* byval(i16) %y1)
ret void
}
declare void @ByValArray([100000 x i64]* byval %p)
declare void @ByValArray([100000 x i64]* byval([100000 x i64]) %p)
define void @TestByValArray() {
; CHECK-LABEL: @TestByValArray dso_preemptable{{$}}
@ -485,7 +485,7 @@ entry:
%z1 = bitcast [100000 x i64]* %z to i8*
%z2 = getelementptr i8, i8* %z1, i64 500000
%z3 = bitcast i8* %z2 to [100000 x i64]*
call void @ByValArray([100000 x i64]* byval %z3)
call void @ByValArray([100000 x i64]* byval([100000 x i64]) %z3)
ret void
}

6
test/Analysis/ValueTracking/memory-dereferenceable.ll
View File

@ -24,8 +24,8 @@ define void @test(%struct.A* sret %result,
i32 addrspace(1)* dereferenceable(8) %dparam,
i8 addrspace(1)* dereferenceable(32) align 1 %dparam.align1,
i8 addrspace(1)* dereferenceable(32) align 16 %dparam.align16,
i8* byval %i8_byval,
%struct.A* byval %A_byval)
i8* byval(i8) %i8_byval,
%struct.A* byval(%struct.A) %A_byval)
gc "statepoint-example" {
; CHECK: The following are dereferenceable:
entry:
@ -177,7 +177,7 @@ entry:
define i32 @f_0(i32 %val) {
%ptr = inttoptr i32 %val to i32*, !dereferenceable !0
%load29 = load i32, i32* %ptr, align 8
ret i32 %load29
ret i32 %load29
}
; Just check that we don't crash.

2
test/Assembler/2008-01-11-VarargAttrs.ll
View File

@ -6,6 +6,6 @@
declare void @foo(...)
define void @bar() {
call void (...) @foo(%struct* byval null )
call void (...) @foo(%struct* byval(%struct) null )
ret void
}

4
test/Assembler/byval-type-attr.ll
View File

@ -13,8 +13,8 @@ define void @bar({i32*, i8}* byval({i32*, i8}) align 4 %0) {
define void @caller({ i32*, i8 }* %ptr) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
; CHECK: call void @bar({ i32*, i8 }* byval({ i32*, i8 }) %ptr)
; CHECK: invoke void @bar({ i32*, i8 }* byval({ i32*, i8 }) %ptr)
call void @bar({i32*, i8}* byval %ptr)
invoke void @bar({i32*, i8}* byval %ptr) to label %success unwind label %fail
call void @bar({i32*, i8}* byval({i32*, i8}) %ptr)
invoke void @bar({i32*, i8}* byval({i32*, i8}) %ptr) to label %success unwind label %fail
success:
ret void

2
test/Assembler/invalid-immarg.ll
View File

@ -1,7 +1,7 @@
; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
; CHECK: Attribute 'immarg' is incompatible with other attributes
declare void @llvm.immarg.byval(i32* byval immarg)
declare void @llvm.immarg.byval(i32* byval(i32) immarg)
; CHECK: Attribute 'immarg' is incompatible with other attributes
declare void @llvm.immarg.inalloca(i32* inalloca immarg)

2
test/Bitcode/attributes-3.3.ll
View File

@ -47,7 +47,7 @@ define void @f7(i8* noalias %0)
ret void;
}
define void @f8(i8* byval %0)
define void @f8(i8* byval(i8) %0)
; CHECK: define void @f8(i8* byval(i8) %0)
{
ret void;

2
test/Bitcode/attributes.ll
View File

@ -44,7 +44,7 @@ define void @f7(i8* noalias %0)
ret void;
}
define void @f8(i8* byval %0)
define void @f8(i8* byval(i8) %0)
; CHECK: define void @f8(i8* byval(i8) %0)
{
ret void;

2
test/Bitcode/compatibility-3.6.ll
View File

@ -403,7 +403,7 @@ declare void @f.param.signext(i8 signext)
; CHECK: declare void @f.param.signext(i8 signext)
declare void @f.param.inreg(i8 inreg)
; CHECK: declare void @f.param.inreg(i8 inreg)
declare void @f.param.byval({ i8, i8 }* byval)
declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
declare void @f.param.inalloca(i8* inalloca)
; CHECK: declare void @f.param.inalloca(i8* inalloca)

2
test/Bitcode/compatibility-3.7.ll
View File

@ -409,7 +409,7 @@ declare void @f.param.signext(i8 signext)
; CHECK: declare void @f.param.signext(i8 signext)
declare void @f.param.inreg(i8 inreg)
; CHECK: declare void @f.param.inreg(i8 inreg)
declare void @f.param.byval({ i8, i8 }* byval)
declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
declare void @f.param.inalloca(i8* inalloca)
; CHECK: declare void @f.param.inalloca(i8* inalloca)

2
test/Bitcode/compatibility-3.8.ll
View File

@ -434,7 +434,7 @@ declare void @f.param.signext(i8 signext)
; CHECK: declare void @f.param.signext(i8 signext)
declare void @f.param.inreg(i8 inreg)
; CHECK: declare void @f.param.inreg(i8 inreg)
declare void @f.param.byval({ i8, i8 }* byval)
declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
declare void @f.param.inalloca(i8* inalloca)
; CHECK: declare void @f.param.inalloca(i8* inalloca)

2
test/Bitcode/compatibility-3.9.ll
View File

@ -503,7 +503,7 @@ declare void @f.param.signext(i8 signext)
; CHECK: declare void @f.param.signext(i8 signext)
declare void @f.param.inreg(i8 inreg)
; CHECK: declare void @f.param.inreg(i8 inreg)
declare void @f.param.byval({ i8, i8 }* byval)
declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
declare void @f.param.inalloca(i8* inalloca)
; CHECK: declare void @f.param.inalloca(i8* inalloca)

2
test/Bitcode/compatibility-4.0.ll
View File

@ -503,7 +503,7 @@ declare void @f.param.signext(i8 signext)
; CHECK: declare void @f.param.signext(i8 signext)
declare void @f.param.inreg(i8 inreg)
; CHECK: declare void @f.param.inreg(i8 inreg)
declare void @f.param.byval({ i8, i8 }* byval)
declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
declare void @f.param.inalloca(i8* inalloca)
; CHECK: declare void @f.param.inalloca(i8* inalloca)

2
test/Bitcode/compatibility-5.0.ll
View File

@ -507,7 +507,7 @@ declare void @f.param.signext(i8 signext)
; CHECK: declare void @f.param.signext(i8 signext)
declare void @f.param.inreg(i8 inreg)
; CHECK: declare void @f.param.inreg(i8 inreg)
declare void @f.param.byval({ i8, i8 }* byval)
declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
declare void @f.param.inalloca(i8* inalloca)
; CHECK: declare void @f.param.inalloca(i8* inalloca)

2
test/Bitcode/compatibility-6.0.ll
View File

@ -514,7 +514,7 @@ declare void @f.param.signext(i8 signext)
; CHECK: declare void @f.param.signext(i8 signext)
declare void @f.param.inreg(i8 inreg)
; CHECK: declare void @f.param.inreg(i8 inreg)
declare void @f.param.byval({ i8, i8 }* byval)
declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
declare void @f.param.inalloca(i8* inalloca)
; CHECK: declare void @f.param.inalloca(i8* inalloca)

2
test/Bitcode/compatibility.ll
View File

@ -530,7 +530,7 @@ declare void @f.param.signext(i8 signext)
; CHECK: declare void @f.param.signext(i8 signext)
declare void @f.param.inreg(i8 inreg)
; CHECK: declare void @f.param.inreg(i8 inreg)
declare void @f.param.byval({ i8, i8 }* byval)
declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 }))
declare void @f.param.inalloca(i8* inalloca)
; CHECK: declare void @f.param.inalloca(i8* inalloca)

4
test/Bitcode/highLevelStructure.3.2.ll
View File

@ -42,7 +42,7 @@ declare void @ParamAttr4(i8 signext)
; CHECK: declare void @ParamAttr5(i8* inreg)
declare void @ParamAttr5(i8* inreg)
; CHECK: declare void @ParamAttr6(i8* byval(i8))
declare void @ParamAttr6(i8* byval)
declare void @ParamAttr6(i8* byval(i8))
; CHECK: declare void @ParamAttr7(i8* noalias)
declare void @ParamAttr7(i8* noalias)
; CHECK: declare void @ParamAttr8(i8* nocapture)
@ -52,7 +52,7 @@ declare void @ParamAttr9(i8* nest noalias nocapture)
; CHECK: declare void @ParamAttr10{{[(i8* sret noalias nocapture) | (i8* noalias nocapture sret)]}}
declare void @ParamAttr10(i8* sret noalias nocapture)
;CHECK: declare void @ParamAttr11{{[(i8* byval(i8) noalias nocapture) | (i8* noalias nocapture byval(i8))]}}
declare void @ParamAttr11(i8* byval noalias nocapture)
declare void @ParamAttr11(i8* byval(i8) noalias nocapture)
;CHECK: declare void @ParamAttr12{{[(i8* inreg noalias nocapture) | (i8* noalias nocapture inreg)]}}
declare void @ParamAttr12(i8* inreg noalias nocapture)

2
test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
View File

@ -166,7 +166,7 @@ define void @test_bad_call_conv() {
}
; Shouldn't tail call when the caller has byval arguments.
define void @test_byval(i8* byval %ptr) {
define void @test_byval(i8* byval(i8) %ptr) {
; COMMON-LABEL: name: test_byval
; COMMON: bb.1 (%ir-block.0):
; COMMON: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0

4
test/CodeGen/AArch64/big-callframe.ll
View File

@ -6,11 +6,11 @@
; CHECK: stur {{.*}}, [x29, #{{.*}}] // 8-byte Folded Spill
; CHECK: ldur {{.*}}, [x29, #{{.*}}] // 8-byte Folded Reload
target triple = "aarch64--"
declare void @extfunc([4096 x i64]* byval %p)
declare void @extfunc([4096 x i64]* byval([4096 x i64]) %p)
define void @func([4096 x i64]* %z) {
%lvar = alloca [31 x i8]
%v = load volatile [31 x i8], [31 x i8]* %lvar
store volatile [31 x i8] %v, [31 x i8]* %lvar
call void @extfunc([4096 x i64]* byval %z)
call void @extfunc([4096 x i64]* byval([4096 x i64]) %z)
ret void
}

8
test/CodeGen/AArch64/byval-type.ll
View File

@ -1,6 +1,6 @@
; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s
define i8 @byval_match(i8* byval(i8) align 1, i8* byval %ptr) {
define i8 @byval_match(i8* byval(i8) align 1, i8* byval(i8) %ptr) {
; CHECK-LABEL: byval_match:
; CHECK: ldrb w0, [sp, #8]
%res = load i8, i8* %ptr
@ -14,11 +14,11 @@ define void @caller_match(i8* %p0, i8* %p1) {
; CHECK: ldrb [[P0:w[0-9]+]], [x0]
; CHECK: strb [[P0]], [sp]
; CHECK: bl byval_match
call i8 @byval_match(i8* byval(i8) align 1 %p0, i8* byval %p1)
call i8 @byval_match(i8* byval(i8) align 1 %p0, i8* byval(i8) %p1)
ret void
}
define i8 @byval_large([3 x i64]* byval([3 x i64]) align 8, i8* byval %ptr) {
define i8 @byval_large([3 x i64]* byval([3 x i64]) align 8, i8* byval(i8) %ptr) {
; CHECK-LABEL: byval_large:
; CHECK: ldrb w0, [sp, #24]
%res = load i8, i8* %ptr
@ -32,6 +32,6 @@ define void @caller_large([3 x i64]* %p0, i8* %p1) {
; CHECK: str [[P0HI]], [sp, #16]
; CHECK: str [[P0LO]], [sp]
; CHECK: bl byval_large
call i8 @byval_large([3 x i64]* byval([3 x i64]) align 8 %p0, i8* byval %p1)
call i8 @byval_large([3 x i64]* byval([3 x i64]) align 8 %p0, i8* byval(i8) %p1)
ret void
}

6
test/CodeGen/AArch64/func-argpassing.ll
View File

@ -32,7 +32,7 @@ define void @add_floats(float %val1, float %val2) {
; byval pointers should be allocated to the stack and copied as if
; with memcpy.
define void @take_struct(%myStruct* byval %structval) {
define void @take_struct(%myStruct* byval(%myStruct) %structval) {
; CHECK-LABEL: take_struct:
%addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2
%addr1 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 0
@ -52,7 +52,7 @@ define void @take_struct(%myStruct* byval %structval) {
}
; %structval should be at sp + 16
define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
define void @check_byval_align(i32* byval(i32) %ignore, %myStruct* byval(%myStruct) align 16 %structval) {
; CHECK-LABEL: check_byval_align:
%addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2
@ -126,7 +126,7 @@ define void @return_large_struct(%myStruct* sret %retval) {
; available, but it needs two). Also make sure that %stacked doesn't
; sneak into x7 behind.
define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
i32* %var6, %myStruct* byval(%myStruct) %struct, i32* byval(i32) %stacked,
double %notstacked) {
; CHECK-LABEL: struct_on_stack:
%addr = getelementptr %myStruct, %myStruct* %struct, i64 0, i32 0

4
test/CodeGen/AArch64/func-calls.ll
View File

@ -74,7 +74,7 @@ define void @simple_rets() {
declare i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
i32* %var6, %myStruct* byval %struct, i32 %stacked,
i32* %var6, %myStruct* byval(%myStruct) %struct, i32 %stacked,
double %notstacked)
declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
float %var4, float %var5, float %var6, float %var7,
@ -83,7 +83,7 @@ declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
define void @check_stack_args() {
; CHECK-LABEL: check_stack_args:
call i32 @struct_on_stack(i8 0, i16 12, i32 42, i64 99, i128 1,
i32* @var32, %myStruct* byval @varstruct,
i32* @var32, %myStruct* byval(%myStruct) @varstruct,
i32 999, double 1.0)
; Want to check that the final double is passed in registers and
; that varstruct is passed on the stack. Rather dependent on how a

6
test/CodeGen/AArch64/statepoint-call-lowering.ll
View File

@ -171,9 +171,9 @@ right:
%struct2 = type { i64, i64, i64 }
declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval)
declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval(%struct2))
define void @test_attributes(%struct2* byval %s) gc "statepoint-example" {
define void @test_attributes(%struct2* byval(%struct2) %s) gc "statepoint-example" {
; CHECK-LABEL: test_attributes:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #32 // =32
@ -192,7 +192,7 @@ define void @test_attributes(%struct2* byval %s) gc "statepoint-example" {
entry:
; Check that arguments with attributes are lowered correctly.
; We call a function that has a nest argument and a byval argument.
%statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval %s, i32 0, i32 0)
%statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval(%struct2) %s, i32 0, i32 0)
ret void
}

2
test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0
declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 {
; GCN-LABEL: name: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32

6
test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
View File

@ -67,8 +67,8 @@ declare hidden void @external_void_func_v32i32_i8_i8_i16(<32 x i32>, i8, i8, i16
; Structs
declare hidden void @external_void_func_struct_i8_i32({ i8, i32 }) #0
declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0
declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0
declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
declare hidden void @external_void_func_v2i8(<2 x i8>) #0
declare hidden void @external_void_func_v3i8(<3 x i8>) #0
@ -76,7 +76,7 @@ declare hidden void @external_void_func_v4i8(<4 x i8>) #0
declare hidden void @external_void_func_v8i8(<8 x i8>) #0
declare hidden void @external_void_func_v16i8(<16 x i8>) #0
declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0
declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0
declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0
declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>,
<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0

6
test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
View File

@ -1683,7 +1683,7 @@ define void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 {
ret void
}
define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 {
define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 {
; CHECK-LABEL: name: void_func_byval_struct_i8_i32
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
@ -1706,7 +1706,7 @@ define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0
ret void
}
define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 {
define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: void_func_byval_struct_i8_i32_x2
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
@ -1743,7 +1743,7 @@ define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %a
ret void
}
define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 {
define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i64 addrspace(5)* byval(i64) %arg1) #0 {
; CHECK-LABEL: name: void_func_byval_i32_byval_i64
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31

2
test/CodeGen/AMDGPU/byval-frame-setup.ll
View File

@ -23,7 +23,7 @@
; GCN: [[BB1]]
; GCN: s_or_b64 exec, exec
define hidden void @void_func_byval_struct_use_outside_entry_block(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1, i1 %cond) #1 {
define hidden void @void_func_byval_struct_use_outside_entry_block(%struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg1, i1 %cond) #1 {
entry:
br i1 %cond, label %bb0, label %bb1

12
test/CodeGen/AMDGPU/call-argument-types.ll
View File

@ -52,8 +52,8 @@ declare hidden i32 @external_i32_func_i32(i32) #0
; Structs
declare hidden void @external_void_func_struct_i8_i32({ i8, i32 }) #0
declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0
declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0
declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
declare hidden void @external_void_func_v16i8(<16 x i8>) #0
@ -681,7 +681,7 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 1
store i8 3, i8 addrspace(5)* %gep0
store i32 8, i32 addrspace(5)* %gep1
call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %val)
call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %val)
ret void
}
@ -713,7 +713,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
%in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1
store i8 3, i8 addrspace(5)* %in.gep0
store i32 8, i32 addrspace(5)* %in.gep1
call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* %in.val)
call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %in.val)
%out.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 0
%out.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 1
%out.val0 = load i8, i8 addrspace(5)* %out.gep0
@ -756,7 +756,7 @@ entry:
define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
entry:
%alloca = alloca double, align 8, addrspace(5)
tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval align 16 %alloca)
tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca)
ret void
}
@ -902,7 +902,7 @@ entry:
ret void
}
declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0
declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0
declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0
declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>,
<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0

4
test/CodeGen/AMDGPU/callee-frame-setup.ll
View File

@ -479,7 +479,7 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 {
; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64
define void @scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval align 4 %arg) #1 {
define void @scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #1 {
%alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca
@ -608,7 +608,7 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 {
; FLATSCR: s_add_u32 [[SOFF:s[0-9]+]], s33, 0x1004
; FLATSCR: v_mov_b32_e32 v0, 0
; FLATSCR: scratch_store_dword off, v0, [[SOFF]]
define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval align 4 %arg) #3 {
define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #3 {
%alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca

2
test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
View File

@ -560,7 +560,7 @@ define void @too_many_args_use_workitem_id_x_byval(
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval %arg32) #1 {
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval(i32) %arg32) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
store volatile i32 %val, i32 addrspace(1)* undef

10
test/CodeGen/AMDGPU/enqueue-kernel.ll
View File

@ -53,13 +53,13 @@ entry:
store i8 %b, i8 addrspace(5)* %block.captured1, align 8
%tmp1 = bitcast <{ i32, i32, i8 addrspace(1)*, i8 }> addrspace(5)* %block to void () addrspace(5)*
%tmp4 = addrspacecast void () addrspace(5)* %tmp1 to i8*
%tmp5 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp,
%tmp5 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp,
i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @__test_block_invoke_kernel to i8*), i8* nonnull %tmp4) #2
%tmp10 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp,
%tmp10 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp,
i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @__test_block_invoke_kernel to i8*), i8* nonnull %tmp4) #2
%tmp11 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp,
%tmp11 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp,
i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @0 to i8*), i8* nonnull %tmp4) #2
%tmp12 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp,
%tmp12 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp,
i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @1 to i8*), i8* nonnull %tmp4) #2
%block.size4 = getelementptr inbounds <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }>, <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }> addrspace(5)* %block2, i32 0, i32 0
store i32 41, i32 addrspace(5)* %block.size4, align 8
@ -75,7 +75,7 @@ entry:
store i64 %d, i64 addrspace(5)* %block.captured10, align 8
%tmp6 = bitcast <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }> addrspace(5)* %block2 to void () addrspace(5)*
%tmp8 = addrspacecast void () addrspace(5)* %tmp6 to i8*
%tmp9 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp3,
%tmp9 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp3,
i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }>)* @__test_block_invoke_2_kernel to i8*), i8* nonnull %tmp8) #2
ret void
}

6
test/CodeGen/AMDGPU/frame-index-elimination.ll
View File

@ -128,7 +128,7 @@ define void @func_load_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 {
; GCN-NOT: v_mov
; GCN: ds_write_b32 v0, v0
define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval %arg0) #0 {
define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 {
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1
%load1 = load i32, i32 addrspace(5)* %gep1
@ -142,7 +142,7 @@ define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval %
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
; GFX9-FLATSCR-NEXT: scratch_load_ubyte v0, off, s32
; GFX9-FLATSCR-NEXT: scratch_load_dword v1, off, s32 offset:4
define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* byval %arg0) #0 {
define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 {
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1
%load0 = load i8, i8 addrspace(5)* %gep0
@ -169,7 +169,7 @@ define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* b
; GFX9-FLATSCR: scratch_load_dword v{{[0-9]+}}, [[SP]], off offset:4{{$}}
; GCN: ds_write_b32 v{{[0-9]+}}, [[GEP]]
define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval %arg0, i32 %arg2) #0 {
define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, i32 %arg2) #0 {
%cmp = icmp eq i32 %arg2, 0
br i1 %cmp, label %bb, label %ret

6
test/CodeGen/AMDGPU/function-args.ll
View File

@ -530,7 +530,7 @@ define void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 {
; GCN-DAG: buffer_load_dword v[[ELT1:[0-9]+]], off, s[0:3], s32 offset:4{{$}}
; GCN-DAG: buffer_store_dword v[[ELT1]]
; GCN-DAG: buffer_store_byte v[[ELT0]]
define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 {
define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 {
%arg0.load = load { i8, i32 }, { i8, i32 } addrspace(5)* %arg0
store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef
ret void
@ -544,7 +544,7 @@ define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0
; GCN: ds_write_b32 v0, v0
; GCN: s_setpc_b64
define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 {
define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 {
%arg0.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg0
%arg1.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg1
store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef
@ -559,7 +559,7 @@ define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %a
; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s32 offset:12{{$}}
; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off
; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ARG1_LOAD0]]:[[ARG1_LOAD1]]{{\]}}, off
define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 {
define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i64 addrspace(5)* byval(i64) %arg1) #0 {
%arg0.load = load i32, i32 addrspace(5)* %arg0
%arg1.load = load i64, i64 addrspace(5)* %arg1
store i32 %arg0.load, i32 addrspace(1)* undef

8
test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
View File

@ -86,8 +86,8 @@ declare hidden amdgpu_gfx i32 @external_i32_func_i32(i32) #0
; Structs
declare hidden amdgpu_gfx void @external_void_func_struct_i8_i32({ i8, i32 }) #0
declare hidden amdgpu_gfx void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0
declare hidden amdgpu_gfx void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0
declare hidden amdgpu_gfx void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
declare hidden amdgpu_gfx void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
declare hidden amdgpu_gfx void @external_void_func_v16i8(<16 x i8>) #0
@ -3392,7 +3392,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-NEXT: s_setpc_b64 s[4:5]
entry:
%alloca = alloca double, align 8, addrspace(5)
tail call amdgpu_gfx void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval align 16 %alloca)
tail call amdgpu_gfx void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca)
ret void
}
@ -6542,7 +6542,7 @@ entry:
ret void
}
declare hidden amdgpu_gfx void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0
declare hidden amdgpu_gfx void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0
declare hidden amdgpu_gfx void @stack_passed_f64_arg(<32 x i32>, double) #0
declare hidden amdgpu_gfx void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>,
<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0

16
test/CodeGen/AMDGPU/load-hi16.ll
View File

@ -502,7 +502,7 @@ entry:
; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 {
define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2047
%load = load i16, i16 addrspace(5)* %gep
@ -522,7 +522,7 @@ entry:
; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval %in, half %reg) #0 {
define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval(half) %in, half %reg) #0 {
entry:
%gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2047
%load = load half, half addrspace(5)* %gep
@ -543,7 +543,7 @@ entry:
; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], 0 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval %in, i16 %reg) #0 {
define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 {
entry:
%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
@ -582,7 +582,7 @@ entry:
; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}}
define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 {
define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095
%load = load i8, i8 addrspace(5)* %gep
@ -603,7 +603,7 @@ entry:
; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}}
define void @load_private_hi_v2f16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, half %reg) #0 {
define void @load_private_hi_v2f16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, half %reg) #0 {
entry:
%gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095
%load = load i8, i8 addrspace(5)* %gep
@ -625,7 +625,7 @@ entry:
; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}}
define void @load_private_hi_v2f16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, half %reg) #0 {
define void @load_private_hi_v2f16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, half %reg) #0 {
entry:
%gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095
%load = load i8, i8 addrspace(5)* %gep
@ -647,7 +647,7 @@ entry:
; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}}
define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 {
define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, i16 %reg) #0 {
entry:
%gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095
%load = load i8, i8 addrspace(5)* %gep
@ -1004,7 +1004,7 @@ entry:
; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v0, off, s32 offset:2
; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: s_setpc_b64
define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval %in) #0 {
define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval(i16) %in) #0 {
entry:
%gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i32 1
%load0 = load volatile i16, i16 addrspace(5)* %in

10
test/CodeGen/AMDGPU/load-lo16.ll
View File

@ -1177,7 +1177,7 @@ entry:
ret void
}
define void @load_private_lo_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i32 %reg) #0 {
define void @load_private_lo_v2i16_reglo_vreg(i16 addrspace(5)* byval(i16) %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg:
; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@ -1226,7 +1226,7 @@ entry:
ret void
}
define void @load_private_lo_v2i16_reghi_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 {
define void @load_private_lo_v2i16_reghi_vreg(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reghi_vreg:
; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@ -1279,7 +1279,7 @@ entry:
ret void
}
define void @load_private_lo_v2f16_reglo_vreg(half addrspace(5)* byval %in, i32 %reg) #0 {
define void @load_private_lo_v2f16_reglo_vreg(half addrspace(5)* byval(half) %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg:
; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@ -1477,7 +1477,7 @@ entry:
ret void
}
define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 {
define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8:
; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@ -1528,7 +1528,7 @@ entry:
ret void
}
define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 {
define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8:
; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

8
test/CodeGen/AMDGPU/rewrite-out-arguments.ll
View File

@ -56,7 +56,7 @@ define void @void_one_out_arg_i32_no_use(i32* %val) #0 {
; CHECK-LABEL: define void @skip_byval_arg(
; CHECK-NEXT: store i32 0, i32* %val
; CHECK-NEXT: ret void
define void @skip_byval_arg(i32* byval %val) #0 {
define void @skip_byval_arg(i32* byval(i32) %val) #0 {
store i32 0, i32* %val
ret void
}
@ -65,7 +65,7 @@ define void @skip_byval_arg(i32* byval %val) #0 {
; CHECK-LABEL: define void @skip_optnone(
; CHECK-NEXT: store i32 0, i32* %val
; CHECK-NEXT: ret void
define void @skip_optnone(i32* byval %val) #1 {
define void @skip_optnone(i32* byval(i32) %val) #1 {
store i32 0, i32* %val
ret void
}
@ -74,7 +74,7 @@ define void @skip_optnone(i32* byval %val) #1 {
; CHECK-LABEL: define void @skip_volatile(
; CHECK-NEXT: store volatile i32 0, i32* %val
; CHECK-NEXT: ret void
define void @skip_volatile(i32* byval %val) #0 {
define void @skip_volatile(i32* byval(i32) %val) #0 {
store volatile i32 0, i32* %val
ret void
}
@ -83,7 +83,7 @@ define void @skip_volatile(i32* byval %val) #0 {
; CHECK-LABEL: define void @skip_atomic(
; CHECK-NEXT: store atomic i32 0, i32* %val
; CHECK-NEXT: ret void
define void @skip_atomic(i32* byval %val) #0 {
define void @skip_atomic(i32* byval(i32) %val) #0 {
store atomic i32 0, i32* %val seq_cst, align 4
ret void
}

8
test/CodeGen/AMDGPU/sibling-call.ll
View File

@ -91,7 +91,7 @@ entry:
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval align 4 %arg1) #1 {
define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval(i32) align 4 %arg1) #1 {
%arg1.load = load i32, i32 addrspace(5)* %arg1, align 4
%add0 = add i32 %arg0, %arg1.load
ret i32 %add0
@ -104,9 +104,9 @@ define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)*
; GCN: s_swappc_b64
; GCN-NOT: v_readlane_b32 s32
; GCN: s_setpc_b64
define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval %b.byval, i32 %c) #1 {
define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval(i32) %b.byval, i32 %c) #1 {
entry:
%ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* %b.byval)
%ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) %b.byval)
ret i32 %ret
}
@ -122,7 +122,7 @@ entry:
; GCN-NEXT: s_setpc_b64
define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32(i32 %a, [32 x i32] %large) #1 {
entry:
%ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* inttoptr (i32 16 to i32 addrspace(5)*))
%ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) inttoptr (i32 16 to i32 addrspace(5)*))
ret i32 %ret
}

2
test/CodeGen/AMDGPU/stack-realign.ll
View File

@ -284,7 +284,7 @@ define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #5 {
ret void
}
define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i32 %b, [4096 x i8] addrspace(5)* byval align 4 %arg) #5 {
define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i32 %b, [4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #5 {
; If the size of the offset exceeds the MUBUF offset field we need another
; scratch VGPR to hold the offset.

2
test/CodeGen/AMDGPU/store-hi16.ll
View File

@ -495,7 +495,7 @@ entry:
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16_max_offset(i16 addrspace(5)* byval %out, i32 %arg) #0 {
define void @store_private_hi_v2i16_max_offset(i16 addrspace(5)* byval(i16) %out, i32 %arg) #0 {
entry:
%value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1

2
test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
View File

@ -6,6 +6,6 @@
define fastcc void @t() {
entry:
%tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; <i1> [#uses=0]
%tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval(%tango.time.Time.Time) null) ; <i1> [#uses=0]
ret void
}

4
test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
View File

@ -33,8 +33,8 @@ target triple = "thumbv7-apple-darwin10"
define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize {
entry:
%call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval @"\01_fnmatch.initial", %union.__mbstate_t* byval @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize
%call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize
ret i32 %call4
}
declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval, %union.__mbstate_t* byval, %struct._xlocale*, i32) nounwind optsize
declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval(%union.__mbstate_t), %union.__mbstate_t* byval(%union.__mbstate_t), %struct._xlocale*, i32) nounwind optsize

2
test/CodeGen/ARM/2011-06-16-TailCallByVal.ll
View File

@ -16,7 +16,7 @@ target triple = "thumbv7-apple-ios5.0"
; CHECK: add sp, #12
; CHECK: b.w _puts
define void @f(i8* %s, %struct.A* nocapture byval %a) nounwind optsize {
define void @f(i8* %s, %struct.A* nocapture byval(%struct.A) %a) nounwind optsize {
entry:
%puts = tail call i32 @puts(i8* %s)
ret void

6
test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
View File

@ -34,7 +34,7 @@ entry:
; CHECK: movw r0, #555
define i32 @main() {
entry:
call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val)
call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval(%struct_t) @static_val)
ret i32 0
}
@ -45,7 +45,7 @@ declare void @f(double);
; CHECK-DAG: str r3, [sp, #12]
; CHECK-DAG: str r2, [sp, #8]
; CHECK-NOT: str r1
define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %val) nounwind {
define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval(%struct_t) %val) nounwind {
entry:
%a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0
%0 = load double, double* %a
@ -61,6 +61,6 @@ entry:
; CHECK: movw r0, #555
define i32 @main_fixed_arg() {
entry:
call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val)
call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval(%struct_t) @static_val)
ret i32 0
}

2
test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
View File

@ -10,7 +10,7 @@ declare i32 @printf(i8*, ...)
; CHECK-DAG: str r3, [sp, #12]
; CHECK-DAG: str r2, [sp, #8]
; CHECK: vldr d16, [sp, #8]
define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind {
define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval(%struct_t) %val) nounwind {
entry:
%a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0
%0 = load double, double* %a

4
test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
View File

@ -4,13 +4,13 @@
%my_struct_t = type { i8, i8, i8, i8, i8 }
@main.val = private unnamed_addr constant %my_struct_t { i8 1, i8 2, i8 3, i8 4, i8 5 }
declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val);
declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval(%my_struct_t) %val);
; CHECK-LABEL: main:
define i32 @main() nounwind {
entry:
; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1
call void @f(i32 555, i32 555, i32 555, %my_struct_t* byval @main.val)
call void @f(i32 555, i32 555, i32 555, %my_struct_t* byval(%my_struct_t) @main.val)
ret i32 0
}

6
test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
View File

@ -1,12 +1,12 @@
; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s
%struct.s = type { [4 x i32] }
@v = constant %struct.s zeroinitializer;
@v = constant %struct.s zeroinitializer;
declare void @f(%struct.s* %p);
; CHECK-LABEL: t:
define void @t(i32 %a, %struct.s* byval %s) nounwind {
define void @t(i32 %a, %struct.s* byval(%struct.s) %s) nounwind {
entry:
; Here we need to only check proper start address of restored %s argument.
@ -25,6 +25,6 @@ entry:
define void @caller() {
; CHECK: ldm r{{[0-9]+}}, {r1, r2, r3}
call void @t(i32 0, %struct.s* @v);
call void @t(i32 0, %struct.s* byval(%struct.s) @v);
ret void
}

8
test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
View File

@ -49,12 +49,12 @@
declare void @fooUseParam(%artz* )
define void @foo(%artz* byval %s) {
define void @foo(%artz* byval(%artz) %s) {
call void @fooUseParam(%artz* %s)
ret void
}
define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) {
define void @foo2(%artz* byval(%artz) %s, i32 %p, %artz* byval(%artz) %s2) {
call void @fooUseParam(%artz* %s)
call void @fooUseParam(%artz* %s2)
ret void
@ -62,12 +62,12 @@ define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) {
define void @doFoo() {
call void @foo(%artz* byval @static_val)
call void @foo(%artz* byval(%artz) @static_val)
ret void
}
define void @doFoo2() {
call void @foo2(%artz* byval @static_val, i32 0, %artz* byval @static_val)
call void @foo2(%artz* byval(%artz) @static_val, i32 0, %artz* byval(%artz) @static_val)
ret void
}

4
test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
View File

@ -30,7 +30,7 @@ define void @foo2(double %p0, ; --> D0
double %p7, ; --> D7
double %p8, ; --> Stack
i32 %p9, ; --> R0
%struct_t* byval %p10) ; --> Stack+8
%struct_t* byval(%struct_t) %p10) ; --> Stack+8
{
entry:
;CHECK: push {r7, lr}
@ -55,7 +55,7 @@ entry:
double 23.7, ; --> D7
double 23.8, ; --> Stack
i32 43, ; --> R0, not Stack+8
%struct_t* byval @static_val) ; --> Stack+8, not R1
%struct_t* byval(%struct_t) @static_val) ; --> Stack+8, not R1
ret void
}

8
test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
View File

@ -16,9 +16,9 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP
double %vfp6, ; --> D6, NSAA=SP
double %vfp7, ; --> D7, NSAA=SP
double %vfp8, ; --> SP, NSAA=SP+8 (!)
i32 %p0, ; --> R0, NSAA=SP+8
%st_t* byval %p1, ; --> R1, R2, NSAA=SP+8
i32 %p2, ; --> R3, NSAA=SP+8
i32 %p0, ; --> R0, NSAA=SP+8
%st_t* byval(%st_t) %p1, ; --> R1, R2, NSAA=SP+8
i32 %p2, ; --> R3, NSAA=SP+8
i32 %p3) #0 { ; --> SP+4, NSAA=SP+12
entry:
;CHECK: sub sp, #12
@ -42,7 +42,7 @@ entry:
double 23.6,
double 23.7,
double 23.8,
i32 0, %st_t* byval @static_val, i32 1, i32 2)
i32 0, %st_t* byval(%st_t) @static_val, i32 1, i32 2)
ret void
}

10
test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
View File

@ -14,10 +14,10 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP
double %vfp6, ; --> D6, NSAA=SP
double %vfp7, ; --> D7, NSAA=SP
double %vfp8, ; --> SP, NSAA=SP+8 (!)
i32 %p0, ; --> R0, NSAA=SP+8
%st_t* byval %p1, ; --> SP+8, 4 words NSAA=SP+24
i32 %p2) #0 { ; --> SP+24, NSAA=SP+24
i32 %p0, ; --> R0, NSAA=SP+8
%st_t* byval(%st_t) %p1, ; --> SP+8, 4 words NSAA=SP+24
i32 %p2) #0 { ; --> SP+24, NSAA=SP+24
entry:
;CHECK: push {r7, lr}
;CHECK: ldr r0, [sp, #32]
@ -39,7 +39,7 @@ entry:
double 23.6,
double 23.7,
double 23.8,
i32 0, %st_t* byval @static_val, i32 1)
i32 0, %st_t* byval(%st_t) @static_val, i32 1)
ret void
}

2
test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
View File

@ -5,7 +5,7 @@
define void @check227(
i32 %b,
%struct.S227* byval nocapture %arg0,
%struct.S227* byval(%struct.S227) nocapture %arg0,
%struct.S227* %arg1) {
; b --> R0
; arg0 --> [R1, R2, R3, SP+0 .. SP+188)

4
test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
View File

@ -4,8 +4,8 @@
%struct4bytes = type { i32 }
%struct20bytes = type { i32, i32, i32, i32, i32 }
define void @foo(%struct4bytes* byval %p0, ; --> R0
%struct20bytes* byval %p1 ; --> R1,R2,R3, [SP+0 .. SP+8)
define void @foo(%struct4bytes* byval(%struct4bytes) %p0, ; --> R0
%struct20bytes* byval(%struct20bytes) %p1 ; --> R1,R2,R3, [SP+0 .. SP+8)
) {
;CHECK: sub sp, sp, #16
;CHECK: push {r11, lr}

8
test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll
View File

@ -12,19 +12,19 @@ define void @f(%big_struct0* %p0, %big_struct1* %p1) {
;CHECK: sub sp, sp, #8
;CHECK: sub sp, sp, #2048
;CHECK: bl callme0
call void @callme0(%big_struct0* byval %p0)
call void @callme0(%big_struct0* byval(%big_struct0) %p0)
;CHECK: add sp, sp, #8
;CHECK: add sp, sp, #2048
;CHECK: sub sp, sp, #2048
;CHECK: bl callme1
call void @callme1(%big_struct1* byval %p1)
call void @callme1(%big_struct1* byval(%big_struct1) %p1)
;CHECK: add sp, sp, #2048
ret void
}
declare void @callme0(%big_struct0* byval)
declare void @callme1(%big_struct1* byval)
declare void @callme0(%big_struct0* byval(%big_struct0))
declare void @callme1(%big_struct1* byval(%big_struct1))

12
test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
View File

@ -11,7 +11,7 @@ declare void @usePtr(%struct8bytes8align*)
; a -> r0
; b -> r1..r3
; c -> sp+0..sp+7
define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) {
define void @foo1(i32 %a, %struct12bytes* byval(%struct12bytes) %b, i64 %c) {
; CHECK-LABEL: foo1
; CHECK: sub sp, sp, #12
; CHECK: push {r11, lr}
@ -30,7 +30,7 @@ define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) {
; a -> r0
; b -> r2..r3
define void @foo2(i32 %a, %struct8bytes8align* byval %b) {
define void @foo2(i32 %a, %struct8bytes8align* byval(%struct8bytes8align) %b) {
; CHECK-LABEL: foo2
; CHECK: sub sp, sp, #8
; CHECK: push {r11, lr}
@ -47,7 +47,7 @@ define void @foo2(i32 %a, %struct8bytes8align* byval %b) {
; a -> r0..r1
; b -> r2
define void @foo3(%struct8bytes8align* byval %a, %struct4bytes* byval %b) {
define void @foo3(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4bytes* byval(%struct4bytes) %b) {
; CHECK-LABEL: foo3
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
@ -64,7 +64,7 @@ define void @foo3(%struct8bytes8align* byval %a, %struct4bytes* byval %b) {
; a -> r0
; b -> r2..r3
define void @foo4(%struct4bytes* byval %a, %struct8bytes8align* byval %b) {
define void @foo4(%struct4bytes* byval(%struct4bytes) %a, %struct8bytes8align* byval(%struct8bytes8align) %b) {
; CHECK-LABEL: foo4
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
@ -84,7 +84,7 @@ define void @foo4(%struct4bytes* byval %a, %struct8bytes8align* byval %b) {
; a -> r0..r1
; b -> r2
; c -> r3
define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struct4bytes* byval %c) {
define void @foo5(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4bytes* byval(%struct4bytes) %b, %struct4bytes* byval(%struct4bytes) %c) {
; CHECK-LABEL: foo5
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
@ -102,7 +102,7 @@ define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struc
; a..c -> r0..r2
; d -> sp+0..sp+7
define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval %d) {
define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval(%struct8bytes8align) %d) {
; CHECK-LABEL: foo6
; CHECK: push {r11, lr}
; CHECK: add r0, sp, #8

4
test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
View File

@ -122,7 +122,7 @@ define i32 @test_thread_local_global() {
%byval.class = type { i32 }
define void @test_byval_arg(%byval.class* byval %x) {
define void @test_byval_arg(%byval.class* byval(%byval.class) %x) {
; CHECK: remark: {{.*}} unable to lower arguments: void (%byval.class*)*
; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval
ret void
@ -131,7 +131,7 @@ define void @test_byval_arg(%byval.class* byval %x) {
define void @test_byval_param(%byval.class* %x) {
; CHECK: remark: {{.*}} unable to translate instruction: call
; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval_param
call void @test_byval_arg(%byval.class* byval %x)
call void @test_byval_arg(%byval.class* byval(%byval.class) %x)
ret void
}

4
test/CodeGen/ARM/align-sp-adjustment.ll
View File

@ -11,7 +11,7 @@
@.str.3 = private unnamed_addr constant [2 x i8] c"d\00", align 1
declare i32* @_Z4bar3iiPKcS0_i(i32, i32, i8*, i8*, i32)
declare void @_Z4bar1i8struct_2(i32, %struct.struct_2* byval align 4)
declare void @_Z4bar1i8struct_2(i32, %struct.struct_2* byval(%struct.struct_2) align 4)
declare i32 @_Z4bar2PiPKc(i32*, i8*)
define void @_Z3fooiiiii(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) #0 {
@ -38,7 +38,7 @@ for.inc:
br i1 %cmp, label %for.body, label %for.end
for.end:
call void @_Z4bar1i8struct_2(i32 %p4, %struct.struct_2* byval nonnull align 4 %params) #4
call void @_Z4bar1i8struct_2(i32 %p4, %struct.struct_2* byval(%struct.struct_2) nonnull align 4 %params) #4
br label %cleanup.8
cleanup.8:

4
test/CodeGen/ARM/alloca-align.ll
View File

@ -3,7 +3,7 @@ target triple="arm--"
@glob = external global i32*
declare void @bar(i32*, [20000 x i8]* byval)
declare void @bar(i32*, [20000 x i8]* byval([20000 x i8]))
; CHECK-LABEL: foo:
; We should see the stack getting additional alignment
@ -17,7 +17,7 @@ declare void @bar(i32*, [20000 x i8]* byval)
define void @foo([20000 x i8]* %addr) {
%tmp = alloca [4 x i32], align 32
%tmp0 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
call void @bar(i32* %tmp0, [20000 x i8]* byval %addr)
call void @bar(i32* %tmp0, [20000 x i8]* byval([20000 x i8]) %addr)
ret void
}

8
test/CodeGen/ARM/byval-align.ll
View File

@ -6,7 +6,7 @@
; users of byval alignments > 4, so no real calls for ABI stability.
; "byval align 16" can't fit in any regs with an i8* taking up r0.
define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) {
define i32 @test_align16(i8*, [4 x i32]* byval([4 x i32]) align 16 %b) {
; CHECK-LABEL: test_align16:
; CHECK-NOT: sub sp
; CHECK: push {r4, r7, lr}
@ -22,7 +22,7 @@ define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) {
; byval align 8 can, but we used to incorrectly set r7 here (miscalculating the
; space taken up by arg regs).
define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) {
define i32 @test_align8(i8*, [4 x i32]* byval([4 x i32]) align 8 %b) {
; CHECK-LABEL: test_align8:
; CHECK: sub sp, #8
; CHECK: push {r4, r7, lr}
@ -40,7 +40,7 @@ define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) {
; "byval align 32" can't fit in regs no matter what: it would be misaligned
; unless the incoming stack was deliberately misaligned.
define i32 @test_align32(i8*, [4 x i32]* byval align 32 %b) {
define i32 @test_align32(i8*, [4 x i32]* byval([4 x i32]) align 32 %b) {
; CHECK-LABEL: test_align32:
; CHECK-NOT: sub sp
; CHECK: push {r4, r7, lr}
@ -67,7 +67,7 @@ define void @test_call_align16() {
; While we're here, make sure the caller also puts it at sp
; CHECK: mov r[[BASE:[0-9]+]], sp
; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
call i32 @test_align16(i8* null, [4 x i32]* byval align 16 @var)
call i32 @test_align16(i8* null, [4 x i32]* byval([4 x i32]) align 16 @var)
ret void
}

4
test/CodeGen/ARM/byval_load_align.ll
View File

@ -16,11 +16,11 @@
; Function Attrs: nounwind ssp
define void @Client() #0 {
entry:
tail call void @Logger(i8 signext 97, %struct.ModuleID* byval @sID) #2
tail call void @Logger(i8 signext 97, %struct.ModuleID* byval(%struct.ModuleID) @sID) #2
ret void
}
declare void @Logger(i8 signext, %struct.ModuleID* byval) #1
declare void @Logger(i8 signext, %struct.ModuleID* byval(%struct.ModuleID)) #1
attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

2
test/CodeGen/ARM/copy-by-struct-i32.ll
View File

@ -54,7 +54,7 @@ define arm_aapcscc void @s(i64* %q, %struct.anon* %p) {
entry:
%0 = load i64, i64* %q, align 8
%sub = add nsw i64 %0, -1
tail call arm_aapcscc void bitcast (void (...)* @r to void (%struct.anon*, %struct.anon*, i64)*)(%struct.anon* byval nonnull align 8 %p, %struct.anon* byval nonnull align 8 %p, i64 %sub)
tail call arm_aapcscc void bitcast (void (...)* @r to void (%struct.anon*, %struct.anon*, i64)*)(%struct.anon* byval(%struct.anon) nonnull align 8 %p, %struct.anon* byval(%struct.anon) nonnull align 8 %p, i64 %sub)
ret void
}

18
test/CodeGen/ARM/ssp-data-layout.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -frame-pointer=all -mcpu=cortex-a8 -mtriple arm-linux-gnu -target-abi=apcs -o - | FileCheck %s
; This test is fairly fragile. The goal is to ensure that "large" stack
; objects are allocated closest to the stack protector (i.e., farthest away
; objects are allocated closest to the stack protector (i.e., farthest away
; from the Stack Pointer.) In standard SSP mode this means that large (>=
; ssp-buffer-size) arrays and structures containing such arrays are
; closet to the protector. With sspstrong and sspreq this means large
@ -159,7 +159,7 @@ entry:
%coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
%7 = bitcast [2 x i16]* %coerce.dive26 to i32*
%8 = load i32, i32* %7, align 1
call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
ret void
}
@ -170,7 +170,7 @@ entry:
; 136 large_char . arrays >= ssp-buffer-size
; 128 struct_large_char .
; 96 struct_large_nonchar .
; 84+8 small_non_char | Group 2, nested arrays,
; 84+8 small_non_char | Group 2, nested arrays,
; 90 small_char | arrays < ssp-buffer-size
; 88 struct_small_char |
; 84 struct_small_nonchar |
@ -178,7 +178,7 @@ entry:
; 76 scalar1 + Group 4, everything else
; 72 scalar2 +
; 68 scalar3 +
;
;
; CHECK: layout_sspstrong:
; CHECK: bl get_scalar1
@ -304,14 +304,14 @@ entry:
%coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
%7 = bitcast [2 x i16]* %coerce.dive26 to i32*
%8 = load i32, i32* %7, align 1
call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
ret void
}
define void @layout_sspreq() sspreq {
entry:
; Expected stack layout for sspreq is the same as sspstrong
;
;
; CHECK: layout_sspreq:
; CHECK: bl get_scalar1
@ -437,7 +437,7 @@ entry:
%coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
%7 = bitcast [2 x i16]* %coerce.dive26 to i32*
%8 = load i32, i32* %7, align 1
call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
ret void
}
@ -476,7 +476,7 @@ entry:
%coerce.dive5 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d2, i32 0, i32 0
%5 = bitcast [2 x i16]* %coerce.dive5 to i32*
%6 = load i32, i32* %5, align 1
call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0)
call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0)
ret void
}
@ -519,4 +519,4 @@ declare void @end_struct_large_nonchar()
declare signext i16 @get_struct_small_nonchar()
declare void @end_struct_small_nonchar()
declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32)
declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32)

2
test/CodeGen/ARM/struct-byval-frame-index.ll
View File

@ -33,6 +33,6 @@ entry:
}
; Function Attrs: nounwind
declare void @RestoreMVBlock8x8(i32, i32, %structN* byval nocapture, i32) #1
declare void @RestoreMVBlock8x8(i32, i32, %structN* byval(%structN) nocapture, i32) #1
attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }

24
test/CodeGen/ARM/struct_byval.ll
View File

@ -16,7 +16,7 @@ entry:
; CHECK: str
; CHECK-NOT:bne
%st = alloca %struct.SmallStruct, align 4
%call = call i32 @e1(%struct.SmallStruct* byval %st)
%call = call i32 @e1(%struct.SmallStruct* byval(%struct.SmallStruct) %st)
ret i32 0
}
@ -37,7 +37,7 @@ entry:
; NACL: str
; NACL: bne
%st = alloca %struct.LargeStruct, align 4
%call = call i32 @e2(%struct.LargeStruct* byval %st)
%call = call i32 @e2(%struct.LargeStruct* byval(%struct.LargeStruct) %st)
ret i32 0
}
@ -55,18 +55,18 @@ entry:
; NACL: vst1
; NACL: bne
%st = alloca %struct.LargeStruct, align 16
%call = call i32 @e3(%struct.LargeStruct* byval align 16 %st)
%call = call i32 @e3(%struct.LargeStruct* byval(%struct.LargeStruct) align 16 %st)
ret i32 0
}
declare i32 @e1(%struct.SmallStruct* nocapture byval %in) nounwind
declare i32 @e2(%struct.LargeStruct* nocapture byval %in) nounwind
declare i32 @e3(%struct.LargeStruct* nocapture byval align 16 %in) nounwind
declare i32 @e1(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %in) nounwind
declare i32 @e2(%struct.LargeStruct* nocapture byval(%struct.LargeStruct) %in) nounwind
declare i32 @e3(%struct.LargeStruct* nocapture byval(%struct.LargeStruct) align 16 %in) nounwind
; rdar://12442472
; We can't do tail call since address of s is passed to the callee and part of
; s is in caller's local frame.
define void @f3(%struct.SmallStruct* nocapture byval %s) nounwind optsize {
define void @f3(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
; CHECK-LABEL: f3
; CHECK: bl _consumestruct
entry:
@ -75,7 +75,7 @@ entry:
ret void
}
define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize {
define void @f4(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
; CHECK-LABEL: f4
; CHECK: bl _consumestruct
entry:
@ -86,7 +86,7 @@ entry:
}
; We can do tail call here since s is in the incoming argument area.
define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize {
define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
; CHECK-LABEL: f5
; CHECK: b{{(\.w)?}} _consumestruct
entry:
@ -95,7 +95,7 @@ entry:
ret void
}
define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize {
define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
; CHECK-LABEL: f6
; CHECK: b{{(\.w)?}} _consumestruct
entry:
@ -110,12 +110,12 @@ declare void @consumestruct(i8* nocapture %structp, i32 %structsize) nounwind
; PR17309
%struct.I.8 = type { [10 x i32], [3 x i8] }
declare void @use_I(%struct.I.8* byval)
declare void @use_I(%struct.I.8* byval(%struct.I.8))
define void @test_I_16() {
; CHECK-LABEL: test_I_16
; CHECK: ldrb
; CHECK: strb
entry:
call void @use_I(%struct.I.8* byval align 16 undef)
call void @use_I(%struct.I.8* byval(%struct.I.8) align 16 undef)
ret void
}

152
test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
View File

@ -25,33 +25,33 @@
;cleanup if the number of bytes does not divide evenly by the store size
%struct.A = type <{ [ 10 x i32 ] }> ; 40 bytes
declare void @use_A(%struct.A* byval)
declare void @use_A(%struct.A* byval(%struct.A))
%struct.B = type <{ [ 10 x i32 ], i8 }> ; 41 bytes
declare void @use_B(%struct.B* byval)
declare void @use_B(%struct.B* byval(%struct.B))
%struct.C = type <{ [ 10 x i32 ], [ 3 x i8 ] }> ; 43 bytes
declare void @use_C(%struct.C* byval)
declare void @use_C(%struct.C* byval(%struct.C))
%struct.D = type <{ [ 100 x i32 ] }> ; 400 bytes
declare void @use_D(%struct.D* byval)
declare void @use_D(%struct.D* byval(%struct.D))
%struct.E = type <{ [ 100 x i32 ], i8 }> ; 401 bytes
declare void @use_E(%struct.E* byval)
declare void @use_E(%struct.E* byval(%struct.E))
%struct.F = type <{ [ 100 x i32 ], [ 3 x i8 ] }> ; 403 bytes
declare void @use_F(%struct.F* byval)
declare void @use_F(%struct.F* byval(%struct.F))
%struct.G = type { [ 10 x i32 ] } ; 40 bytes
declare void @use_G(%struct.G* byval)
declare void @use_G(%struct.G* byval(%struct.G))
%struct.H = type { [ 10 x i32 ], i8 } ; 41 bytes
declare void @use_H(%struct.H* byval)
declare void @use_H(%struct.H* byval(%struct.H))
%struct.I = type { [ 10 x i32 ], [ 3 x i8 ] } ; 43 bytes
declare void @use_I(%struct.I* byval)
declare void @use_I(%struct.I* byval(%struct.I))
%struct.J = type { [ 100 x i32 ] } ; 400 bytes
declare void @use_J(%struct.J* byval)
declare void @use_J(%struct.J* byval(%struct.J))
%struct.K = type { [ 100 x i32 ], i8 } ; 401 bytes
declare void @use_K(%struct.K* byval)
declare void @use_K(%struct.K* byval(%struct.K))
%struct.L = type { [ 100 x i32 ], [ 3 x i8 ] } ; 403 bytes
declare void @use_L(%struct.L* byval)
declare void @use_L(%struct.L* byval(%struct.L))
%struct.M = type { [ 64 x i8 ] } ; 64 bytes
declare void @use_M(%struct.M* byval)
declare void @use_M(%struct.M* byval(%struct.M))
%struct.N = type { [ 128 x i8 ] } ; 128 bytes
declare void @use_N(%struct.N* byval)
declare void @use_N(%struct.N* byval(%struct.N))
;ARM-LABEL: <test_A_1>:
;THUMB2-LABEL: <test_A_1>:
@ -71,7 +71,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.A, align 1
call void @use_A(%struct.A* byval align 1 %a)
call void @use_A(%struct.A* byval(%struct.A) align 1 %a)
ret void
}
;ARM-LABEL: <test_A_2>:
@ -92,7 +92,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.A, align 2
call void @use_A(%struct.A* byval align 2 %a)
call void @use_A(%struct.A* byval(%struct.A) align 2 %a)
ret void
}
;ARM-LABEL: <test_A_4>:
@ -113,7 +113,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.A, align 4
call void @use_A(%struct.A* byval align 4 %a)
call void @use_A(%struct.A* byval(%struct.A) align 4 %a)
ret void
}
;ARM-LABEL: <test_A_8>:
@ -135,7 +135,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.A, align 8
call void @use_A(%struct.A* byval align 8 %a)
call void @use_A(%struct.A* byval(%struct.A) align 8 %a)
ret void
}
;ARM-LABEL: <test_A_16>:
@ -159,7 +159,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.A, align 16
call void @use_A(%struct.A* byval align 16 %a)
call void @use_A(%struct.A* byval(%struct.A) align 16 %a)
ret void
}
;ARM-LABEL: <test_B_1>:
@ -180,7 +180,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.B, align 1
call void @use_B(%struct.B* byval align 1 %a)
call void @use_B(%struct.B* byval(%struct.B) align 1 %a)
ret void
}
;ARM-LABEL: <test_B_2>:
@ -205,7 +205,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.B, align 2
call void @use_B(%struct.B* byval align 2 %a)
call void @use_B(%struct.B* byval(%struct.B) align 2 %a)
ret void
}
;ARM-LABEL: <test_B_4>:
@ -230,7 +230,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.B, align 4
call void @use_B(%struct.B* byval align 4 %a)
call void @use_B(%struct.B* byval(%struct.B) align 4 %a)
ret void
}
;ARM-LABEL: <test_B_8>:
@ -256,7 +256,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.B, align 8
call void @use_B(%struct.B* byval align 8 %a)
call void @use_B(%struct.B* byval(%struct.B) align 8 %a)
ret void
}
;ARM-LABEL: <test_B_16>:
@ -282,7 +282,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.B, align 16
call void @use_B(%struct.B* byval align 16 %a)
call void @use_B(%struct.B* byval(%struct.B) align 16 %a)
ret void
}
;ARM-LABEL: <test_C_1>:
@ -303,7 +303,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.C, align 1
call void @use_C(%struct.C* byval align 1 %a)
call void @use_C(%struct.C* byval(%struct.C) align 1 %a)
ret void
}
;ARM-LABEL: <test_C_2>:
@ -328,7 +328,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.C, align 2
call void @use_C(%struct.C* byval align 2 %a)
call void @use_C(%struct.C* byval(%struct.C) align 2 %a)
ret void
}
;ARM-LABEL: <test_C_4>:
@ -354,7 +354,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.C, align 4
call void @use_C(%struct.C* byval align 4 %a)
call void @use_C(%struct.C* byval(%struct.C) align 4 %a)
ret void
}
;ARM-LABEL: <test_C_8>:
@ -381,7 +381,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.C, align 8
call void @use_C(%struct.C* byval align 8 %a)
call void @use_C(%struct.C* byval(%struct.C) align 8 %a)
ret void
}
;ARM-LABEL: <test_C_16>:
@ -408,7 +408,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.C, align 16
call void @use_C(%struct.C* byval align 16 %a)
call void @use_C(%struct.C* byval(%struct.C) align 16 %a)
ret void
}
;ARM-LABEL: <test_D_1>:
@ -433,7 +433,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.D, align 1
call void @use_D(%struct.D* byval align 1 %a)
call void @use_D(%struct.D* byval(%struct.D) align 1 %a)
ret void
}
;ARM-LABEL: <test_D_2>:
@ -458,7 +458,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.D, align 2
call void @use_D(%struct.D* byval align 2 %a)
call void @use_D(%struct.D* byval(%struct.D) align 2 %a)
ret void
}
;ARM-LABEL: <test_D_4>:
@ -483,7 +483,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.D, align 4
call void @use_D(%struct.D* byval align 4 %a)
call void @use_D(%struct.D* byval(%struct.D) align 4 %a)
ret void
}
;ARM-LABEL: <test_D_8>:
@ -509,7 +509,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.D, align 8
call void @use_D(%struct.D* byval align 8 %a)
call void @use_D(%struct.D* byval(%struct.D) align 8 %a)
ret void
}
;ARM-LABEL: <test_D_16>:
@ -535,7 +535,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.D, align 16
call void @use_D(%struct.D* byval align 16 %a)
call void @use_D(%struct.D* byval(%struct.D) align 16 %a)
ret void
}
;ARM-LABEL: <test_E_1>:
@ -560,7 +560,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.E, align 1
call void @use_E(%struct.E* byval align 1 %a)
call void @use_E(%struct.E* byval(%struct.E) align 1 %a)
ret void
}
;ARM-LABEL: <test_E_2>:
@ -589,7 +589,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.E, align 2
call void @use_E(%struct.E* byval align 2 %a)
call void @use_E(%struct.E* byval(%struct.E) align 2 %a)
ret void
}
;ARM-LABEL: <test_E_4>:
@ -618,7 +618,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.E, align 4
call void @use_E(%struct.E* byval align 4 %a)
call void @use_E(%struct.E* byval(%struct.E) align 4 %a)
ret void
}
;ARM-LABEL: <test_E_8>:
@ -648,7 +648,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.E, align 8
call void @use_E(%struct.E* byval align 8 %a)
call void @use_E(%struct.E* byval(%struct.E) align 8 %a)
ret void
}
;ARM-LABEL: <test_E_16>:
@ -678,7 +678,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.E, align 16
call void @use_E(%struct.E* byval align 16 %a)
call void @use_E(%struct.E* byval(%struct.E) align 16 %a)
ret void
}
;ARM-LABEL: <test_F_1>:
@ -703,7 +703,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.F, align 1
call void @use_F(%struct.F* byval align 1 %a)
call void @use_F(%struct.F* byval(%struct.F) align 1 %a)
ret void
}
;ARM-LABEL: <test_F_2>:
@ -732,7 +732,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.F, align 2
call void @use_F(%struct.F* byval align 2 %a)
call void @use_F(%struct.F* byval(%struct.F) align 2 %a)
ret void
}
;ARM-LABEL: <test_F_4>:
@ -762,7 +762,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.F, align 4
call void @use_F(%struct.F* byval align 4 %a)
call void @use_F(%struct.F* byval(%struct.F) align 4 %a)
ret void
}
;ARM-LABEL: <test_F_8>:
@ -793,7 +793,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.F, align 8
call void @use_F(%struct.F* byval align 8 %a)
call void @use_F(%struct.F* byval(%struct.F) align 8 %a)
ret void
}
;ARM-LABEL: <test_F_16>:
@ -824,7 +824,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.F, align 16
call void @use_F(%struct.F* byval align 16 %a)
call void @use_F(%struct.F* byval(%struct.F) align 16 %a)
ret void
}
;ARM-LABEL: <test_G_1>:
@ -845,7 +845,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.G, align 1
call void @use_G(%struct.G* byval align 1 %a)
call void @use_G(%struct.G* byval(%struct.G) align 1 %a)
ret void
}
;ARM-LABEL: <test_G_2>:
@ -866,7 +866,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.G, align 2
call void @use_G(%struct.G* byval align 2 %a)
call void @use_G(%struct.G* byval(%struct.G) align 2 %a)
ret void
}
;ARM-LABEL: <test_G_4>:
@ -887,7 +887,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.G, align 4
call void @use_G(%struct.G* byval align 4 %a)
call void @use_G(%struct.G* byval(%struct.G) align 4 %a)
ret void
}
;ARM-LABEL: <test_G_8>:
@ -909,7 +909,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.G, align 8
call void @use_G(%struct.G* byval align 8 %a)
call void @use_G(%struct.G* byval(%struct.G) align 8 %a)
ret void
}
;ARM-LABEL: <test_G_16>:
@ -931,7 +931,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.G, align 16
call void @use_G(%struct.G* byval align 16 %a)
call void @use_G(%struct.G* byval(%struct.G) align 16 %a)
ret void
}
;ARM-LABEL: <test_H_1>:
@ -952,7 +952,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.H, align 1
call void @use_H(%struct.H* byval align 1 %a)
call void @use_H(%struct.H* byval(%struct.H) align 1 %a)
ret void
}
;ARM-LABEL: <test_H_2>:
@ -973,7 +973,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.H, align 2
call void @use_H(%struct.H* byval align 2 %a)
call void @use_H(%struct.H* byval(%struct.H) align 2 %a)
ret void
}
;ARM-LABEL: <test_H_4>:
@ -994,7 +994,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.H, align 4
call void @use_H(%struct.H* byval align 4 %a)
call void @use_H(%struct.H* byval(%struct.H) align 4 %a)
ret void
}
;ARM-LABEL: <test_H_8>:
@ -1016,7 +1016,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.H, align 8
call void @use_H(%struct.H* byval align 8 %a)
call void @use_H(%struct.H* byval(%struct.H) align 8 %a)
ret void
}
;ARM-LABEL: <test_H_16>:
@ -1038,7 +1038,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.H, align 16
call void @use_H(%struct.H* byval align 16 %a)
call void @use_H(%struct.H* byval(%struct.H) align 16 %a)
ret void
}
;ARM-LABEL: <test_I_1>:
@ -1059,7 +1059,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.I, align 1
call void @use_I(%struct.I* byval align 1 %a)
call void @use_I(%struct.I* byval(%struct.I) align 1 %a)
ret void
}
;ARM-LABEL: <test_I_2>:
@ -1080,7 +1080,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.I, align 2
call void @use_I(%struct.I* byval align 2 %a)
call void @use_I(%struct.I* byval(%struct.I) align 2 %a)
ret void
}
;ARM-LABEL: <test_I_4>:
@ -1101,7 +1101,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.I, align 4
call void @use_I(%struct.I* byval align 4 %a)
call void @use_I(%struct.I* byval(%struct.I) align 4 %a)
ret void
}
;ARM-LABEL: <test_I_8>:
@ -1123,7 +1123,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.I, align 8
call void @use_I(%struct.I* byval align 8 %a)
call void @use_I(%struct.I* byval(%struct.I) align 8 %a)
ret void
}
;ARM-LABEL: <test_I_16>:
@ -1145,7 +1145,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.I, align 16
call void @use_I(%struct.I* byval align 16 %a)
call void @use_I(%struct.I* byval(%struct.I) align 16 %a)
ret void
}
;ARM-LABEL: <test_J_1>:
@ -1170,7 +1170,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.J, align 1
call void @use_J(%struct.J* byval align 1 %a)
call void @use_J(%struct.J* byval(%struct.J) align 1 %a)
ret void
}
;ARM-LABEL: <test_J_2>:
@ -1195,7 +1195,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.J, align 2
call void @use_J(%struct.J* byval align 2 %a)
call void @use_J(%struct.J* byval(%struct.J) align 2 %a)
ret void
}
;ARM-LABEL: <test_J_4>:
@ -1220,7 +1220,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.J, align 4
call void @use_J(%struct.J* byval align 4 %a)
call void @use_J(%struct.J* byval(%struct.J) align 4 %a)
ret void
}
;ARM-LABEL: <test_J_8>:
@ -1246,7 +1246,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.J, align 8
call void @use_J(%struct.J* byval align 8 %a)
call void @use_J(%struct.J* byval(%struct.J) align 8 %a)
ret void
}
;ARM-LABEL: <test_J_16>:
@ -1272,7 +1272,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.J, align 16
call void @use_J(%struct.J* byval align 16 %a)
call void @use_J(%struct.J* byval(%struct.J) align 16 %a)
ret void
}
;ARM-LABEL: <test_K_1>:
@ -1297,7 +1297,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.K, align 1
call void @use_K(%struct.K* byval align 1 %a)
call void @use_K(%struct.K* byval(%struct.K) align 1 %a)
ret void
}
;ARM-LABEL: <test_K_2>:
@ -1322,7 +1322,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.K, align 2
call void @use_K(%struct.K* byval align 2 %a)
call void @use_K(%struct.K* byval(%struct.K) align 2 %a)
ret void
}
;ARM-LABEL: <test_K_4>:
@ -1347,7 +1347,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.K, align 4
call void @use_K(%struct.K* byval align 4 %a)
call void @use_K(%struct.K* byval(%struct.K) align 4 %a)
ret void
}
;ARM-LABEL: <test_K_8>:
@ -1373,7 +1373,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.K, align 8
call void @use_K(%struct.K* byval align 8 %a)
call void @use_K(%struct.K* byval(%struct.K) align 8 %a)
ret void
}
;ARM-LABEL: <test_K_16>:
@ -1399,7 +1399,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.K, align 16
call void @use_K(%struct.K* byval align 16 %a)
call void @use_K(%struct.K* byval(%struct.K) align 16 %a)
ret void
}
;ARM-LABEL: <test_L_1>:
@ -1424,7 +1424,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.L, align 1
call void @use_L(%struct.L* byval align 1 %a)
call void @use_L(%struct.L* byval(%struct.L) align 1 %a)
ret void
}
;ARM-LABEL: <test_L_2>:
@ -1449,7 +1449,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.L, align 2
call void @use_L(%struct.L* byval align 2 %a)
call void @use_L(%struct.L* byval(%struct.L) align 2 %a)
ret void
}
;ARM-LABEL: <test_L_4>:
@ -1474,7 +1474,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.L, align 4
call void @use_L(%struct.L* byval align 4 %a)
call void @use_L(%struct.L* byval(%struct.L) align 4 %a)
ret void
}
;ARM-LABEL: <test_L_8>:
@ -1500,7 +1500,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.L, align 8
call void @use_L(%struct.L* byval align 8 %a)
call void @use_L(%struct.L* byval(%struct.L) align 8 %a)
ret void
}
;ARM-LABEL: <test_L_16>:
@ -1526,7 +1526,7 @@ declare void @use_N(%struct.N* byval)
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.L, align 16
call void @use_L(%struct.L* byval align 16 %a)
call void @use_L(%struct.L* byval(%struct.L) align 16 %a)
ret void
}
;V8MBASE-LABEL: <test_M>:
@ -1537,7 +1537,7 @@ declare void @use_N(%struct.N* byval)
;V8MBASE-NOT: movw
entry:
%a = alloca %struct.M, align 1
call void @use_M(%struct.M* byval align 1 %a)
call void @use_M(%struct.M* byval(%struct.M) align 1 %a)
ret void
}
;V8MBASE-LABEL: <test_N>:
@ -1547,6 +1547,6 @@ declare void @use_N(%struct.N* byval)
;V8MBASE-NOT: b #{{[0-9]+}}
entry:
%a = alloca %struct.N, align 1
call void @use_N(%struct.N* byval align 1 %a)
call void @use_N(%struct.N* byval(%struct.N) align 1 %a)
ret void
}

4
test/CodeGen/BPF/byval.ll
View File

@ -17,11 +17,11 @@ entry:
%arrayinit.start = getelementptr inbounds %struct.S, %struct.S* %.compoundliteral, i64 0, i32 0, i64 3
%scevgep4 = bitcast i32* %arrayinit.start to i8*
call void @llvm.memset.p0i8.i64(i8* align 4 %scevgep4, i8 0, i64 28, i1 false)
call void @foo(i32 %a, %struct.S* byval align 8 %.compoundliteral) #3
call void @foo(i32 %a, %struct.S* byval(%struct.S) align 8 %.compoundliteral) #3
ret void
}
declare void @foo(i32, %struct.S* byval align 8) #1
declare void @foo(i32, %struct.S* byval(%struct.S) align 8) #1
; Function Attrs: nounwind
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3

6
test/CodeGen/Generic/2010-11-04-BigByval.ll
View File

@ -3,9 +3,9 @@
%big = type [131072 x i8]
declare void @foo(%big* byval align 1)
declare void @foo(%big* byval(%big) align 1)
define void @bar(%big* byval align 1 %x) {
call void @foo(%big* byval align 1 %x)
define void @bar(%big* byval(%big) align 1 %x) {
call void @foo(%big* byval(%big) align 1 %x)
ret void
}

2
test/CodeGen/Hexagon/bit-skip-byval.ll
View File

@ -5,7 +5,7 @@
%struct.t0 = type { i32 }
define i32 @foo(%struct.t0* byval align 8 %s, i8 zeroext %t, i8 %u) #0 {
define i32 @foo(%struct.t0* byval(%struct.t0) align 8 %s, i8 zeroext %t, i8 %u) #0 {
%a = zext i8 %u to i32
ret i32 %a
}

6
test/CodeGen/Hexagon/calling-conv.ll
View File

@ -11,7 +11,7 @@
; CHECK-TWO: memw(r29+#52) = r2
; CHECK-THREE: memw(r29+#56) = r2
define void @f0(%s.0* noalias nocapture sret %a0, i32 %a1, i8 zeroext %a2, %s.0* byval nocapture readnone align 8 %a3, %s.1* byval nocapture readnone align 8 %a4) #0 {
define void @f0(%s.0* noalias nocapture sret %a0, i32 %a1, i8 zeroext %a2, %s.0* byval(%s.0) nocapture readnone align 8 %a3, %s.1* byval(%s.1) nocapture readnone align 8 %a4) #0 {
b0:
%v0 = alloca %s.0, align 8
%v1 = load %s.0*, %s.0** @g0, align 4
@ -19,7 +19,7 @@ b0:
%v3 = add nsw i64 %v2, 1
%v4 = add nsw i32 %a1, 2
%v5 = add nsw i64 %v2, 3
call void @f1(%s.0* sret %v0, i32 45, %s.0* byval align 8 %v1, %s.0* byval align 8 %v1, i8 zeroext %a2, i64 %v3, i32 %v4, i64 %v5, i8 zeroext %a2, i8 zeroext %a2, i8 zeroext %a2, i32 45)
call void @f1(%s.0* sret %v0, i32 45, %s.0* byval(%s.0) align 8 %v1, %s.0* byval(%s.0) align 8 %v1, i8 zeroext %a2, i64 %v3, i32 %v4, i64 %v5, i8 zeroext %a2, i8 zeroext %a2, i8 zeroext %a2, i32 45)
%v6 = bitcast %s.0* %v0 to i32*
store i32 20, i32* %v6, align 8
%v7 = bitcast %s.0* %a0 to i8*
@ -28,7 +28,7 @@ b0:
ret void
}
declare void @f1(%s.0* sret, i32, %s.0* byval align 8, %s.0* byval align 8, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32)
declare void @f1(%s.0* sret, i32, %s.0* byval(%s.0) align 8, %s.0* byval(%s.0) align 8, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32)
; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) #1

2
test/CodeGen/Hexagon/cext-opt-negative-fi.mir
View File

@ -22,7 +22,7 @@
%s.9 = type { i8, i8 }
; Function Attrs: nounwind optsize
define dso_local void @f0(%s.0* byval nocapture readonly align 8 %a0) local_unnamed_addr #0 {
define dso_local void @f0(%s.0* byval(%s.0) nocapture readonly align 8 %a0) local_unnamed_addr #0 {
b0:
%v0 = getelementptr inbounds %s.0, %s.0* %a0, i32 0, i32 10
%v1 = load i8, i8* %v0, align 8

2
test/CodeGen/Hexagon/inline-asm-error.ll
View File

@ -6,7 +6,7 @@
%s.1 = type { %s.2 }
%s.2 = type { i32, i8* }
define void @f0(%s.0* byval align 8 %a0) {
define void @f0(%s.0* byval(%s.0) align 8 %a0) {
b0:
call void asm sideeffect ".weak OFFSET_0;jump ##(OFFSET_0 + 0x14c15f0)", "*r"(%s.0* nonnull %a0), !srcloc !0
ret void

4
test/CodeGen/Hexagon/struct_args_large.ll
View File

@ -10,8 +10,8 @@
define void @foo() nounwind {
entry:
call void @bar(%struct.large* byval @s2)
call void @bar(%struct.large* byval(%struct.large) @s2)
ret void
}
declare void @bar(%struct.large* byval)
declare void @bar(%struct.large* byval(%struct.large))

2
test/CodeGen/Hexagon/tail-dup-subreg-map.ll
View File

@ -14,7 +14,7 @@ target triple = "hexagon"
declare hidden fastcc void @foo(%struct.0* noalias nocapture, i8 signext, i8 zeroext, i32, i64, i64) unnamed_addr #0
define void @fred(%struct.0* noalias nocapture sret %agg.result, %struct.1* byval nocapture readonly align 8 %a, i32 %a0) #1 {
define void @fred(%struct.0* noalias nocapture sret %agg.result, %struct.1* byval(%struct.1) nocapture readonly align 8 %a, i32 %a0) #1 {
entry:
%0 = load i64, i64* undef, align 8
switch i32 %a0, label %if.else [

4
test/CodeGen/Hexagon/v6vect-locals1.ll
View File

@ -16,7 +16,7 @@ target triple = "hexagon"
declare i32 @f0(i8* nocapture, ...) #0
; Function Attrs: nounwind
define void @f1(%s.0* byval %a0, <16 x i32> %a1) #0 {
define void @f1(%s.0* byval(%s.0) %a0, <16 x i32> %a1) #0 {
b0:
%v0 = alloca <16 x i32>, align 64
store <16 x i32> %a1, <16 x i32>* %v0, align 64, !tbaa !0
@ -30,7 +30,7 @@ b0:
define i32 @f2() #0 {
b0:
%v0 = load <16 x i32>, <16 x i32>* @g2, align 64, !tbaa !0
tail call void @f1(%s.0* byval @g1, <16 x i32> %v0)
tail call void @f1(%s.0* byval(%s.0) @g1, <16 x i32> %v0)
ret i32 0
}

2
test/CodeGen/Hexagon/vararg.ll
View File

@ -82,7 +82,7 @@ declare void @llvm.va_end(i8*) #1
; Function Attrs: nounwind
define i32 @main() #0 {
entry:
%call = tail call i32 (i32, ...) @foo(i32 undef, i32 2, %struct.AAA* byval align 4 @aaa, i32 4)
%call = tail call i32 (i32, ...) @foo(i32 undef, i32 2, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4)
%call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %call) #1
ret i32 %call
}

4
test/CodeGen/Hexagon/vararg_align_check.ll
View File

@ -29,7 +29,7 @@
@.str = private unnamed_addr constant [13 x i8] c"result = %d\0A\00", align 1
; Function Attrs: nounwind
define i32 @foo(i32 %xx, %struct.BBB* byval align 8 %eee, ...) #0 {
define i32 @foo(i32 %xx, %struct.BBB* byval(%struct.BBB) align 8 %eee, ...) #0 {
entry:
%xx.addr = alloca i32, align 4
%ap = alloca [1 x %struct.__va_list_tag], align 8
@ -169,7 +169,7 @@ entry:
store i32 0, i32* %retval
store i64 1000000, i64* %m, align 8
%0 = load i64, i64* %m, align 8
%call = call i32 (i32, %struct.BBB*, ...) @foo(i32 1, %struct.BBB* byval align 8 bitcast ({ i8, i64, i32, [4 x i8] }* @ddd to %struct.BBB*), i64 %0, %struct.AAA* byval align 4 @aaa, i32 4)
%call = call i32 (i32, %struct.BBB*, ...) @foo(i32 1, %struct.BBB* byval(%struct.BBB) align 8 bitcast ({ i8, i64, i32, [4 x i8] }* @ddd to %struct.BBB*), i64 %0, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4)
store i32 %call, i32* %x, align 4
%1 = load i32, i32* %x, align 4
%call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %1)

2
test/CodeGen/Hexagon/vararg_double_onstack.ll
View File

@ -197,7 +197,7 @@ entry:
store i64 1000000, i64* %y, align 8
%0 = load i64, i64* %y, align 8
%1 = load i64, i64* %y, align 8
%call = call i32 (i32, i32, i32, i32, i32, ...) @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i64 %0, %struct.AAA* byval align 4 @aaa, i32 4, i64 %1)
%call = call i32 (i32, i32, i32, i32, i32, ...) @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i64 %0, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4, i64 %1)
store i32 %call, i32* %x, align 4
%2 = load i32, i32* %x, align 4
%call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %2)

4
test/CodeGen/Hexagon/vararg_named.ll
View File

@ -31,7 +31,7 @@
@.str = private unnamed_addr constant [13 x i8] c"result = %d\0A\00", align 1
; Function Attrs: nounwind
define i32 @foo(i32 %xx, i32 %z, i32 %m, %struct.AAA* byval align 4 %bbb, %struct.AAA* byval align 4 %GGG, ...) #0 {
define i32 @foo(i32 %xx, i32 %z, i32 %m, %struct.AAA* byval(%struct.AAA) align 4 %bbb, %struct.AAA* byval(%struct.AAA) align 4 %GGG, ...) #0 {
entry:
%xx.addr = alloca i32, align 4
%z.addr = alloca i32, align 4
@ -194,7 +194,7 @@ entry:
%retval = alloca i32, align 4
%x = alloca i32, align 4
store i32 0, i32* %retval
%call = call i32 (i32, i32, i32, %struct.AAA*, %struct.AAA*, ...) @foo(i32 1, i32 3, i32 5, %struct.AAA* byval align 4 @aaa, %struct.AAA* byval align 4 @fff, i32 2, %struct.AAA* byval align 4 @xxx, %struct.AAA* byval align 4 @yyy, %struct.AAA* byval align 4 @ccc, i32 4)
%call = call i32 (i32, i32, i32, %struct.AAA*, %struct.AAA*, ...) @foo(i32 1, i32 3, i32 5, %struct.AAA* byval(%struct.AAA) align 4 @aaa, %struct.AAA* byval(%struct.AAA) align 4 @fff, i32 2, %struct.AAA* byval(%struct.AAA) align 4 @xxx, %struct.AAA* byval(%struct.AAA) align 4 @yyy, %struct.AAA* byval(%struct.AAA) align 4 @ccc, i32 4)
store i32 %call, i32* %x, align 4
%0 = load i32, i32* %x, align 4
%call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %0)

2
test/CodeGen/MIR/X86/fixed-stack-di.mir
View File

@ -8,7 +8,7 @@
declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
define hidden void @foo(i32* byval %dstRect) {
define hidden void @foo(i32* byval(i32) %dstRect) {
entry:
call void @llvm.dbg.declare(metadata i32* %dstRect, metadata !3, metadata !DIExpression()), !dbg !5
unreachable

4
test/CodeGen/MSP430/byval.ll
View File

@ -6,7 +6,7 @@ target triple = "msp430---elf"
%struct.Foo = type { i16, i16, i16 }
@foo = global %struct.Foo { i16 1, i16 2, i16 3 }, align 2
define i16 @callee(%struct.Foo* byval %f) nounwind {
define i16 @callee(%struct.Foo* byval(%struct.Foo) %f) nounwind {
entry:
; CHECK-LABEL: callee:
; CHECK: mov 2(r1), r12
@ -21,6 +21,6 @@ entry:
; CHECK: mov &foo+4, 4(r1)
; CHECK-NEXT: mov &foo+2, 2(r1)
; CHECK-NEXT: mov &foo, 0(r1)
%call = call i16 @callee(%struct.Foo* byval @foo)
%call = call i16 @callee(%struct.Foo* byval(%struct.Foo) @foo)
ret void
}

2
test/CodeGen/MSP430/spill-to-stack.ll
View File

@ -2,7 +2,7 @@
%VeryLarge = type { i8, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
; intentionally cause a spill
define void @inc(%VeryLarge* byval align 1 %s) {
define void @inc(%VeryLarge* byval(%VeryLarge) align 1 %s) {
entry:
%p0 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 0
%0 = load i8, i8* %p0

6
test/CodeGen/Mips/cconv/byval.ll
View File

@ -152,11 +152,11 @@ define dso_local void @g() #0 {
; N64-NEXT: daddu $sp, $sp, $1
entry:
%a = alloca %struct.S1, align 4
call void @f2(%struct.S1* byval align 4 %a)
call void @f2(%struct.S1* byval(%struct.S1) align 4 %a)
ret void
}
declare dso_local void @f2(%struct.S1* byval align 4) #1
declare dso_local void @f2(%struct.S1* byval(%struct.S1) align 4) #1
; O32-SDAG-LABEL: Initial selection DAG: %bb.0 'g2:entry'
; O32-SDAG: t{{.*}}: ch,glue = callseq_start t{{.*}}, TargetConstant:i32<{{.*}}>
@ -348,7 +348,7 @@ entry:
%1 = bitcast %struct.S1* %byval-temp to i8*
%2 = bitcast %struct.S1* %0 to i8*
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 1 %2, i32 65520, i1 false)
call void @f2(%struct.S1* byval align 4 %byval-temp)
call void @f2(%struct.S1* byval(%struct.S1) align 4 %byval-temp)
ret void
}

4
test/CodeGen/Mips/cprestore.ll
View File

@ -13,8 +13,8 @@
define void @foo2() nounwind {
entry:
%s = alloca %struct.S, align 4
call void @foo1(%struct.S* byval %s)
call void @foo1(%struct.S* byval(%struct.S) %s)
ret void
}
declare void @foo1(%struct.S* byval)
declare void @foo1(%struct.S* byval(%struct.S))

6
test/CodeGen/Mips/fastcc_byval.ll
View File

@ -5,9 +5,9 @@
%struct.str = type { i32, i32, [3 x i32*] }
declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret %agg.result, %struct.str* byval nocapture readonly align 4 %s)
declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret %agg.result, %struct.str* byval(%struct.str) nocapture readonly align 4 %s)
define i32 @_Z1g3str(%struct.str* byval nocapture readonly align 4 %s) {
define i32 @_Z1g3str(%struct.str* byval(%struct.str) nocapture readonly align 4 %s) {
; CHECK-LABEL: _Z1g3str:
; CHECK: sw $7, [[OFFSET:[0-9]+]]($sp)
; CHECK: lw ${{[0-9]+}}, [[OFFSET]]($sp)
@ -15,7 +15,7 @@ entry:
%ref.tmp = alloca %struct.str, align 4
%0 = bitcast %struct.str* %ref.tmp to i8*
call void @llvm.lifetime.start.p0i8(i64 20, i8* nonnull %0)
call fastcc void @_Z1F3str(%struct.str* nonnull sret %ref.tmp, %struct.str* byval nonnull align 4 %s)
call fastcc void @_Z1F3str(%struct.str* nonnull sret %ref.tmp, %struct.str* byval(%struct.str) nonnull align 4 %s)
%cl.sroa.3.0..sroa_idx2 = getelementptr inbounds %struct.str, %struct.str* %ref.tmp, i32 0, i32 1
%cl.sroa.3.0.copyload = load i32, i32* %cl.sroa.3.0..sroa_idx2, align 4
call void @llvm.lifetime.end.p0i8(i64 20, i8* nonnull %0)

4
test/CodeGen/Mips/largeimmprinting.ll
View File

@ -27,10 +27,10 @@ entry:
%agg.tmp = alloca %struct.S1, align 1
%tmp = getelementptr inbounds %struct.S1, %struct.S1* %agg.tmp, i32 0, i32 0, i32 0
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp, i8* align 1 getelementptr inbounds (%struct.S1, %struct.S1* @s1, i32 0, i32 0, i32 0), i32 65536, i1 false)
call void @f2(%struct.S1* byval %agg.tmp) nounwind
call void @f2(%struct.S1* byval(%struct.S1) %agg.tmp) nounwind
ret void
}
declare void @f2(%struct.S1* byval)
declare void @f2(%struct.S1* byval(%struct.S1))
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind

4
test/CodeGen/Mips/load-store-left-right.ll
View File

@ -535,8 +535,8 @@ entry:
; MIPS64R6: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
tail call void @extern_func([7 x i8]* byval @arr) nounwind
tail call void @extern_func([7 x i8]* byval([7 x i8]) @arr) nounwind
ret void
}
declare void @extern_func([7 x i8]* byval)
declare void @extern_func([7 x i8]* byval([7 x i8]))

24
test/CodeGen/Mips/o32_cc_byval.ll
View File

@ -81,21 +81,21 @@ define void @f1() nounwind {
; CHECK-NEXT: addiu $sp, $sp, 64
entry:
%agg.tmp10 = alloca %struct.S3, align 4
call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
call void @callee2(%struct.S2* byval @f1.s2) nounwind
call void @callee1(float 2.000000e+01, %struct.S1* byval(%struct.S1) bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
call void @callee2(%struct.S2* byval(%struct.S2) @f1.s2) nounwind
%tmp11 = getelementptr inbounds %struct.S3, %struct.S3* %agg.tmp10, i32 0, i32 0
store i8 11, i8* %tmp11, align 4
call void @callee3(float 2.100000e+01, %struct.S3* byval %agg.tmp10, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
call void @callee3(float 2.100000e+01, %struct.S3* byval(%struct.S3) %agg.tmp10, %struct.S1* byval(%struct.S1) bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
ret void
}
declare void @callee1(float, %struct.S1* byval)
declare void @callee1(float, %struct.S1* byval(%struct.S1))
declare void @callee2(%struct.S2* byval)
declare void @callee2(%struct.S2* byval(%struct.S2))
declare void @callee3(float, %struct.S3* byval, %struct.S1* byval)
declare void @callee3(float, %struct.S3* byval(%struct.S3), %struct.S1* byval(%struct.S1))
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
define void @f2(float %f, %struct.S1* nocapture byval(%struct.S1) %s1) nounwind {
; CHECK-LABEL: f2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui $2, %hi(_gp_disp)
@ -144,7 +144,7 @@ entry:
declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float)
define void @f3(%struct.S2* nocapture byval %s2) nounwind {
define void @f3(%struct.S2* nocapture byval(%struct.S2) %s2) nounwind {
; CHECK-LABEL: f3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui $2, %hi(_gp_disp)
@ -184,7 +184,7 @@ entry:
ret void
}
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
define void @f4(float %f, %struct.S3* nocapture byval(%struct.S3) %s3, %struct.S1* nocapture byval(%struct.S1) %s1) nounwind {
; CHECK-LABEL: f4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui $2, %hi(_gp_disp)
@ -230,7 +230,7 @@ entry:
%struct.S4 = type { [4 x i32] }
define void @f5(i64 %a0, %struct.S4* nocapture byval %a1) nounwind {
define void @f5(i64 %a0, %struct.S4* nocapture byval(%struct.S4) %a1) nounwind {
; CHECK-LABEL: f5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui $2, %hi(_gp_disp)
@ -252,8 +252,8 @@ define void @f5(i64 %a0, %struct.S4* nocapture byval %a1) nounwind {
; CHECK-NEXT: jr $ra
; CHECK-NEXT: addiu $sp, $sp, 32
entry:
tail call void @f6(%struct.S4* byval %a1, i64 %a0) nounwind
tail call void @f6(%struct.S4* byval(%struct.S4) %a1, i64 %a0) nounwind
ret void
}
declare void @f6(%struct.S4* nocapture byval, i64)
declare void @f6(%struct.S4* nocapture byval(%struct.S4), i64)

10
test/CodeGen/Mips/tailcall/tailcall.ll
View File

@ -192,7 +192,7 @@ entry:
@gs1 = external global %struct.S
declare i32 @callee9(%struct.S* byval)
declare i32 @callee9(%struct.S* byval(%struct.S))
define i32 @caller9_0() nounwind {
entry:
@ -223,7 +223,7 @@ entry:
; PIC64R6: jalrc $25
; PIC16: jalrc
%call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind
%call = tail call i32 @callee9(%struct.S* byval(%struct.S) @gs1) nounwind
ret i32 %call
}
@ -246,7 +246,7 @@ entry:
ret i32 %call
}
declare i32 @callee11(%struct.S* byval)
declare i32 @callee11(%struct.S* byval(%struct.S))
define i32 @caller11() nounwind noinline {
entry:
@ -261,7 +261,7 @@ entry:
; PIC64R6: jalrc $25
; PIC16: jalrc
%call = tail call i32 @callee11(%struct.S* byval @gs1) nounwind
%call = tail call i32 @callee11(%struct.S* byval(%struct.S) @gs1) nounwind
ret i32 %call
}
@ -269,7 +269,7 @@ declare i32 @callee12()
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
define i32 @caller12(%struct.S* nocapture byval %a0) nounwind {
define i32 @caller12(%struct.S* nocapture byval(%struct.S) %a0) nounwind {
entry:
; ALL-LABEL: caller12:
; PIC32: jalr $25

8
test/CodeGen/Mips/unalignedload.ll
View File

@ -30,7 +30,7 @@ entry:
; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]])
tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind
tail call void @foo2(%struct.S1* byval(%struct.S1) getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind
ret void
}
@ -76,10 +76,10 @@ entry:
; MIPS32R6-EB-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8
; MIPS32R6-EB-DAG: or $5, $[[T2]], $[[T3]]
tail call void @foo4(%struct.S4* byval @s4) nounwind
tail call void @foo4(%struct.S4* byval(%struct.S4) @s4) nounwind
ret void
}
declare void @foo2(%struct.S1* byval)
declare void @foo2(%struct.S1* byval(%struct.S1))
declare void @foo4(%struct.S4* byval)
declare void @foo4(%struct.S4* byval(%struct.S4))

2
test/CodeGen/NVPTX/bug21465.ll
View File

@ -7,7 +7,7 @@ target triple = "nvptx64-unknown-unknown"
%struct.S = type { i32, i32 }
; Function Attrs: nounwind
define void @_Z11TakesStruct1SPi(%struct.S* byval nocapture readonly %input, i32* nocapture %output) #0 {
define void @_Z11TakesStruct1SPi(%struct.S* byval(%struct.S) nocapture readonly %input, i32* nocapture %output) #0 {
entry:
; CHECK-LABEL: @_Z11TakesStruct1SPi
; PTX-LABEL: .visible .entry _Z11TakesStruct1SPi(

4
test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll
View File

@ -28,7 +28,7 @@ define void @kernel2(float addrspace(1)* %input, float addrspace(1)* %output) {
%struct.S = type { i32*, i32* }
define void @ptr_in_byval_kernel(%struct.S* byval %input, i32* %output) {
define void @ptr_in_byval_kernel(%struct.S* byval(%struct.S) %input, i32* %output) {
; CHECK-LABEL: .visible .entry ptr_in_byval_kernel(
; CHECK: ld.param.u64 %[[optr:rd.*]], [ptr_in_byval_kernel_param_1]
; CHECK: cvta.to.global.u64 %[[optr_g:.*]], %[[optr]];
@ -46,7 +46,7 @@ define void @ptr_in_byval_kernel(%struct.S* byval %input, i32* %output) {
; Regular functions lower byval arguments differently. We need to make
; sure that we're loading byval argument data using [symbol+offset].
; There's also no assumption that all pointers within are in global space.
define void @ptr_in_byval_func(%struct.S* byval %input, i32* %output) {
define void @ptr_in_byval_func(%struct.S* byval(%struct.S) %input, i32* %output) {
; CHECK-LABEL: .visible .func ptr_in_byval_func(
; CHECK: ld.param.u64 %[[optr:rd.*]], [ptr_in_byval_func_param_1]
; CHECK: ld.param.u64 %[[iptr:rd.*]], [ptr_in_byval_func_param_0+8]

12
test/CodeGen/NVPTX/param-align.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
;;; Need 4-byte alignment on float* passed byval
define ptx_device void @t1(float* byval %x) {
define ptx_device void @t1(float* byval(float) %x) {
; CHECK: .func t1
; CHECK: .param .align 4 .b8 t1_param_0[4]
ret void
@ -9,7 +9,7 @@ define ptx_device void @t1(float* byval %x) {
;;; Need 8-byte alignment on double* passed byval
define ptx_device void @t2(double* byval %x) {
define ptx_device void @t2(double* byval(double) %x) {
; CHECK: .func t2
; CHECK: .param .align 8 .b8 t2_param_0[8]
ret void
@ -18,7 +18,7 @@ define ptx_device void @t2(double* byval %x) {
;;; Need 4-byte alignment on float2* passed byval
%struct.float2 = type { float, float }
define ptx_device void @t3(%struct.float2* byval %x) {
define ptx_device void @t3(%struct.float2* byval(%struct.float2) %x) {
; CHECK: .func t3
; CHECK: .param .align 4 .b8 t3_param_0[8]
ret void
@ -26,19 +26,19 @@ define ptx_device void @t3(%struct.float2* byval %x) {
;;; Need at least 4-byte alignment in order to avoid miscompilation by
;;; ptxas for sm_50+
define ptx_device void @t4(i8* byval %x) {
define ptx_device void @t4(i8* byval(i8) %x) {
; CHECK: .func t4
; CHECK: .param .align 4 .b8 t4_param_0[1]
ret void
}
;;; Make sure we adjust alignment at the call site as well.
define ptx_device void @t5(i8* align 2 byval %x) {
define ptx_device void @t5(i8* align 2 byval(i8) %x) {
; CHECK: .func t5
; CHECK: .param .align 4 .b8 t5_param_0[1]
; CHECK: {
; CHECK: .param .align 4 .b8 param0[1];
; CHECK: call.uni
call void @t4(i8* byval %x)
call void @t4(i8* byval(i8) %x)
ret void
}

8
test/CodeGen/PowerPC/MMO-flags-assertion.ll
View File

@ -3,7 +3,7 @@
; void llvm::MachineMemOperand::refineAlignment(const llvm::MachineMemOperand*):
; Assertion `MMO->getFlags() == getFlags() && "Flags mismatch !"' failed.
declare void @_Z3fn11F(%class.F* byval align 8) local_unnamed_addr
declare void @_Z3fn11F(%class.F* byval(%class.F) align 8) local_unnamed_addr
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1)
declare signext i32 @_ZN1F11isGlobalRegEv(%class.F*) local_unnamed_addr
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
@ -12,9 +12,9 @@ declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
%class.F = type { i32, i64, i8, [64 x i8], i8, i32* }
define signext i32 @_Z29EmitOMPAtomicSimpleUpdateExpr1F(%class.F* byval align 8 %p1) local_unnamed_addr {
define signext i32 @_Z29EmitOMPAtomicSimpleUpdateExpr1F(%class.F* byval(%class.F) align 8 %p1) local_unnamed_addr {
entry:
call void @_Z3fn11F(%class.F* byval nonnull align 8 %p1)
call void @_Z3fn11F(%class.F* byval(%class.F) nonnull align 8 %p1)
%call = call signext i32 @_ZN1F11isGlobalRegEv(%class.F* nonnull %p1)
ret i32 %call
}
@ -29,7 +29,7 @@ entry:
%1 = bitcast %class.F* %agg.tmp1 to i8*
call void @llvm.lifetime.start.p0i8(i64 96, i8* nonnull %1)
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 nonnull %1, i8* align 8 nonnull %0, i64 96, i1 false)
call void @_Z3fn11F(%class.F* byval nonnull align 8 %XLValue)
call void @_Z3fn11F(%class.F* byval(%class.F) nonnull align 8 %XLValue)
%call.i = call signext i32 @_ZN1F11isGlobalRegEv(%class.F* nonnull %agg.tmp1)
call void @llvm.lifetime.end.p0i8(i64 96, i8* nonnull %1)
call void @llvm.lifetime.end.p0i8(i64 96, i8* nonnull %0)

Some files were not shown because too many files have changed in this diff Show More