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[FPEnv] Invert sense of MIFlag::FPExcept flag
In D71841 we inverted the sense of the SDNode-level flag to ensure all nodes default to potentially raising FP exceptions unless otherwise specified -- i.e. if we forget to propagate the flag somewhere, the effect is now only lost performance, not incorrect code. However, the related flag at the MI level still defaults to nodes not raising FP exceptions unless otherwise specified. To be fully on the (conservatively) safe side, we should invert that flag as well. This patch does so by replacing MIFlag::FPExcept with MIFlag::NoFPExcept. (Note that this does also introduce an incompatible change in the MIR format.) Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D72466
This commit is contained in:
Ulrich Weigand
parent
5ff915b04d
commit
4e7ea868cb
@ -104,8 +104,8 @@ public:
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// no signed wrap.
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IsExact = 1 << 13, // Instruction supports division is
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// known to be exact.
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FPExcept = 1 << 14, // Instruction may raise floating-point
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// exceptions.
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NoFPExcept = 1 << 14, // Instruction does not raise
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// floatint-point exceptions.
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};
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private:
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@ -885,10 +885,10 @@ public:
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/// instruction that can in principle raise an exception, as indicated
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/// by the MCID::MayRaiseFPException property, *and* at the same time,
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/// the instruction is used in a context where we expect floating-point
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/// exceptions might be enabled, as indicated by the FPExcept MI flag.
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/// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
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bool mayRaiseFPException() const {
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return hasProperty(MCID::MayRaiseFPException) &&
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getFlag(MachineInstr::MIFlag::FPExcept);
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!getFlag(MachineInstr::MIFlag::NoFPExcept);
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}
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//===--------------------------------------------------------------------===//
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@ -204,7 +204,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
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.Case("nuw" , MIToken::kw_nuw)
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.Case("nsw" , MIToken::kw_nsw)
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.Case("exact" , MIToken::kw_exact)
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.Case("fpexcept", MIToken::kw_fpexcept)
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.Case("nofpexcept", MIToken::kw_nofpexcept)
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.Case("debug-location", MIToken::kw_debug_location)
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.Case("same_value", MIToken::kw_cfi_same_value)
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.Case("offset", MIToken::kw_cfi_offset)
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@ -73,7 +73,7 @@ struct MIToken {
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kw_nuw,
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kw_nsw,
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kw_exact,
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kw_fpexcept,
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kw_nofpexcept,
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kw_debug_location,
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kw_cfi_same_value,
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kw_cfi_offset,
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@ -1185,7 +1185,7 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
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Token.is(MIToken::kw_nuw) ||
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Token.is(MIToken::kw_nsw) ||
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Token.is(MIToken::kw_exact) ||
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Token.is(MIToken::kw_fpexcept)) {
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Token.is(MIToken::kw_nofpexcept)) {
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// Mine frame and fast math flags
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if (Token.is(MIToken::kw_frame_setup))
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Flags |= MachineInstr::FrameSetup;
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@ -1211,8 +1211,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
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Flags |= MachineInstr::NoSWrap;
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if (Token.is(MIToken::kw_exact))
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Flags |= MachineInstr::IsExact;
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if (Token.is(MIToken::kw_fpexcept))
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Flags |= MachineInstr::FPExcept;
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if (Token.is(MIToken::kw_nofpexcept))
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Flags |= MachineInstr::NoFPExcept;
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lex();
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}
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@ -752,8 +752,8 @@ void MIPrinter::print(const MachineInstr &MI) {
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OS << "nsw ";
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if (MI.getFlag(MachineInstr::IsExact))
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OS << "exact ";
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if (MI.getFlag(MachineInstr::FPExcept))
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OS << "fpexcept ";
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if (MI.getFlag(MachineInstr::NoFPExcept))
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OS << "nofpexcept ";
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OS << TII->getName(MI.getOpcode());
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if (I < E)
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@ -1538,8 +1538,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
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OS << "nsw ";
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if (getFlag(MachineInstr::IsExact))
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OS << "exact ";
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if (getFlag(MachineInstr::FPExcept))
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OS << "fpexcept ";
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if (getFlag(MachineInstr::NoFPExcept))
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OS << "nofpexcept ";
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// Print the opcode name.
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if (TII)
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@ -882,8 +882,8 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
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if (Flags.hasExact())
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MI->setFlag(MachineInstr::MIFlag::IsExact);
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if (MI->getDesc().mayRaiseFPException() && !Flags.hasNoFPExcept())
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MI->setFlag(MachineInstr::MIFlag::FPExcept);
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if (Flags.hasNoFPExcept())
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MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
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}
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// Emit all of the actual operands of this instruction, adding them to the
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@ -297,10 +297,10 @@ bool SystemZElimCompare::convertToLoadAndTest(
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MIB.setMemRefs(MI.memoperands());
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MI.eraseFromParent();
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// Mark instruction as raising an FP exception if applicable. We already
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// Mark instruction as not raising an FP exception if applicable. We already
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// verified earlier that this move is valid.
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if (Compare.mayRaiseFPException())
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MIB.setMIFlag(MachineInstr::MIFlag::FPExcept);
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if (!Compare.mayRaiseFPException())
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MIB.setMIFlag(MachineInstr::MIFlag::NoFPExcept);
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return true;
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}
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@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -O0 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -O0 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx512f | FileCheck %s --check-prefix=AVX512
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@ -12,9 +12,10 @@ define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_oeq_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpeqss %xmm1, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: andnps %xmm3, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_oeq_f32:
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@ -38,9 +39,10 @@ define double @select_fcmp_oeq_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_oeq_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpeqsd %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andpd %xmm2, %xmm1
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; SSE-NEXT: andnpd %xmm3, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_oeq_f64:
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@ -64,9 +66,10 @@ define float @select_fcmp_ogt_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_ogt_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpltss %xmm0, %xmm1
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; SSE-NEXT: andps %xmm1, %xmm2
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: andnps %xmm3, %xmm1
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; SSE-NEXT: orps %xmm2, %xmm1
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; SSE-NEXT: orps %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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@ -91,10 +94,11 @@ define double @select_fcmp_ogt_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_ogt_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpltsd %xmm0, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm2
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm2, %xmm0
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; SSE-NEXT: andnpd %xmm3, %xmm1
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; SSE-NEXT: orpd %xmm2, %xmm1
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; SSE-NEXT: movapd %xmm1, %xmm0
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; SSE-NEXT: orpd %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_ogt_f64:
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@ -118,9 +122,10 @@ define float @select_fcmp_oge_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_oge_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpless %xmm0, %xmm1
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; SSE-NEXT: andps %xmm1, %xmm2
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: andnps %xmm3, %xmm1
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; SSE-NEXT: orps %xmm2, %xmm1
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; SSE-NEXT: orps %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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@ -145,10 +150,11 @@ define double @select_fcmp_oge_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_oge_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cmplesd %xmm0, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm2
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm2, %xmm0
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; SSE-NEXT: andnpd %xmm3, %xmm1
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; SSE-NEXT: orpd %xmm2, %xmm1
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; SSE-NEXT: movapd %xmm1, %xmm0
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; SSE-NEXT: orpd %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_oge_f64:
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@ -172,9 +178,10 @@ define float @select_fcmp_olt_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_olt_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpltss %xmm1, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: andnps %xmm3, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_olt_f32:
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@ -198,9 +205,10 @@ define double @select_fcmp_olt_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_olt_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpltsd %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andpd %xmm2, %xmm1
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; SSE-NEXT: andnpd %xmm3, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_olt_f64:
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@ -224,9 +232,10 @@ define float @select_fcmp_ole_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_ole_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpless %xmm1, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: andnps %xmm3, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_ole_f32:
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@ -250,9 +259,10 @@ define double @select_fcmp_ole_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_ole_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cmplesd %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andpd %xmm2, %xmm1
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; SSE-NEXT: andnpd %xmm3, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_ole_f64:
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@ -276,9 +286,10 @@ define float @select_fcmp_ord_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_ord_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpordss %xmm1, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: andnps %xmm3, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_ord_f32:
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@ -302,9 +313,10 @@ define double @select_fcmp_ord_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_ord_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpordsd %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andpd %xmm2, %xmm1
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; SSE-NEXT: andnpd %xmm3, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_ord_f64:
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@ -328,9 +340,10 @@ define float @select_fcmp_uno_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_uno_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpunordss %xmm1, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: andnps %xmm3, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_uno_f32:
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@ -354,9 +367,10 @@ define double @select_fcmp_uno_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_uno_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpunordsd %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andpd %xmm2, %xmm1
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; SSE-NEXT: andnpd %xmm3, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_uno_f64:
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@ -380,9 +394,10 @@ define float @select_fcmp_ugt_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_ugt_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpnless %xmm1, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: andnps %xmm3, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_ugt_f32:
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@ -406,9 +421,10 @@ define double @select_fcmp_ugt_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_ugt_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpnlesd %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: andpd %xmm2, %xmm1
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; SSE-NEXT: andnpd %xmm3, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_ugt_f64:
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@ -432,9 +448,10 @@ define float @select_fcmp_uge_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_uge_f32:
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; SSE: # %bb.0:
|
||||
; SSE-NEXT: cmpnltss %xmm1, %xmm0
|
||||
; SSE-NEXT: andps %xmm0, %xmm2
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: andps %xmm2, %xmm1
|
||||
; SSE-NEXT: andnps %xmm3, %xmm0
|
||||
; SSE-NEXT: orps %xmm2, %xmm0
|
||||
; SSE-NEXT: orps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: select_fcmp_uge_f32:
|
||||
@ -458,9 +475,10 @@ define double @select_fcmp_uge_f64(double %a, double %b, double %c, double %d) {
|
||||
; SSE-LABEL: select_fcmp_uge_f64:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: cmpnltsd %xmm1, %xmm0
|
||||
; SSE-NEXT: andpd %xmm0, %xmm2
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: andpd %xmm2, %xmm1
|
||||
; SSE-NEXT: andnpd %xmm3, %xmm0
|
||||
; SSE-NEXT: orpd %xmm2, %xmm0
|
||||
; SSE-NEXT: orpd %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: select_fcmp_uge_f64:
|
||||
@ -484,9 +502,10 @@ define float @select_fcmp_ult_f32(float %a, float %b, float %c, float %d) {
|
||||
; SSE-LABEL: select_fcmp_ult_f32:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: cmpnless %xmm0, %xmm1
|
||||
; SSE-NEXT: andps %xmm1, %xmm2
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: andps %xmm2, %xmm0
|
||||
; SSE-NEXT: andnps %xmm3, %xmm1
|
||||
; SSE-NEXT: orps %xmm2, %xmm1
|
||||
; SSE-NEXT: orps %xmm0, %xmm1
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
@ -511,10 +530,11 @@ define double @select_fcmp_ult_f64(double %a, double %b, double %c, double %d) {
|
||||
; SSE-LABEL: select_fcmp_ult_f64:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: cmpnlesd %xmm0, %xmm1
|
||||
; SSE-NEXT: andpd %xmm1, %xmm2
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: andpd %xmm2, %xmm0
|
||||
; SSE-NEXT: andnpd %xmm3, %xmm1
|
||||
; SSE-NEXT: orpd %xmm2, %xmm1
|
||||
; SSE-NEXT: movapd %xmm1, %xmm0
|
||||
; SSE-NEXT: orpd %xmm0, %xmm1
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: select_fcmp_ult_f64:
|
||||
@ -538,9 +558,10 @@ define float @select_fcmp_ule_f32(float %a, float %b, float %c, float %d) {
|
||||
; SSE-LABEL: select_fcmp_ule_f32:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: cmpnltss %xmm0, %xmm1
|
||||
; SSE-NEXT: andps %xmm1, %xmm2
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: andps %xmm2, %xmm0
|
||||
; SSE-NEXT: andnps %xmm3, %xmm1
|
||||
; SSE-NEXT: orps %xmm2, %xmm1
|
||||
; SSE-NEXT: orps %xmm0, %xmm1
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
@ -565,10 +586,11 @@ define double @select_fcmp_ule_f64(double %a, double %b, double %c, double %d) {
|
||||
; SSE-LABEL: select_fcmp_ule_f64:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: cmpnltsd %xmm0, %xmm1
|
||||
; SSE-NEXT: andpd %xmm1, %xmm2
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: andpd %xmm2, %xmm0
|
||||
; SSE-NEXT: andnpd %xmm3, %xmm1
|
||||
; SSE-NEXT: orpd %xmm2, %xmm1
|
||||
; SSE-NEXT: movapd %xmm1, %xmm0
|
||||
; SSE-NEXT: orpd %xmm0, %xmm1
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: select_fcmp_ule_f64:
|
||||
@ -592,9 +614,10 @@ define float @select_fcmp_une_f32(float %a, float %b, float %c, float %d) {
|
||||
; SSE-LABEL: select_fcmp_une_f32:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: cmpneqss %xmm1, %xmm0
|
||||
; SSE-NEXT: andps %xmm0, %xmm2
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: andps %xmm2, %xmm1
|
||||
; SSE-NEXT: andnps %xmm3, %xmm0
|
||||
; SSE-NEXT: orps %xmm2, %xmm0
|
||||
; SSE-NEXT: orps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: select_fcmp_une_f32:
|
||||
@ -618,9 +641,10 @@ define double @select_fcmp_une_f64(double %a, double %b, double %c, double %d) {
|
||||
; SSE-LABEL: select_fcmp_une_f64:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: cmpneqsd %xmm1, %xmm0
|
||||
; SSE-NEXT: andpd %xmm0, %xmm2
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: andpd %xmm2, %xmm1
|
||||
; SSE-NEXT: andnpd %xmm3, %xmm0
|
||||
; SSE-NEXT: orpd %xmm2, %xmm0
|
||||
; SSE-NEXT: orpd %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: select_fcmp_une_f64:
|
||||
|
||||
@ -4,7 +4,7 @@ define i32 @f20u(double %x) #0 {
|
||||
; CHECK-LABEL: name: f20u
|
||||
; CHECK: liveins: $xmm0
|
||||
; CHECK: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
|
||||
; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = fpexcept CVTTSD2SI64rr [[COPY]], implicit $mxcsr
|
||||
; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = CVTTSD2SI64rr [[COPY]], implicit $mxcsr
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[CVTTSD2SI64rr]].sub_32bit
|
||||
; CHECK: $eax = COPY [[COPY1]]
|
||||
; CHECK: RET 0, $eax
|
||||
|
||||
@ -6,7 +6,7 @@ entry:
|
||||
; CHECK: [[MOVSX32rm8_:%[0-9]+]]:gr32 = MOVSX32rm8 %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 1 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr killed [[MOVSX32rm8_]]
|
||||
; CHECK: MOVSDmr %stack.0, 1, $noreg, 0, $noreg, killed [[CVTSI2SDrr]] :: (store 8 into %stack.0, align 4)
|
||||
; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
|
||||
; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = nofpexcept LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
|
||||
; CHECK: RET 0, killed [[LD_Fp64m80_]]
|
||||
%result = call double @llvm.experimental.constrained.sitofp.f64.i8(i8 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
|
||||
ret double %result
|
||||
@ -18,7 +18,7 @@ entry:
|
||||
; CHECK: [[MOVSX32rm16_:%[0-9]+]]:gr32 = MOVSX32rm16 %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 2 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr killed [[MOVSX32rm16_]]
|
||||
; CHECK: MOVSDmr %stack.0, 1, $noreg, 0, $noreg, killed [[CVTSI2SDrr]] :: (store 8 into %stack.0, align 4)
|
||||
; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
|
||||
; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = nofpexcept LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
|
||||
; CHECK: RET 0, killed [[LD_Fp64m80_]]
|
||||
%result = call double @llvm.experimental.constrained.sitofp.f64.i16(i16 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
|
||||
ret double %result
|
||||
@ -29,14 +29,14 @@ entry:
|
||||
; CHECK-LABEL: name: f20u64
|
||||
; CHECK: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[MOVSDrm_alt1:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool)
|
||||
; CHECK: fpexcept COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
|
||||
; CHECK: COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
|
||||
; CHECK: [[FsFLD0SD:%[0-9]+]]:fr64 = FsFLD0SD
|
||||
; CHECK: JCC_1
|
||||
; CHECK: [[PHI:%[0-9]+]]:fr64 = PHI [[MOVSDrm_alt1]], {{.*}}, [[FsFLD0SD]], {{.*}}
|
||||
; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = fpexcept SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
|
||||
; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
|
||||
; CHECK: MOVSDmr %stack.0, 1, $noreg, 0, $noreg, killed [[SUBSDrr]] :: (store 8 into %stack.0)
|
||||
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
|
||||
; CHECK: [[LD_Fp64m:%[0-9]+]]:rfp64 = fpexcept LD_Fp64m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0)
|
||||
; CHECK: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0)
|
||||
; CHECK: FNSTCW16m %stack.1, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (store 2 into %stack.1)
|
||||
; CHECK: [[MOVZX32rm16_:%[0-9]+]]:gr32 = MOVZX32rm16 %stack.1, 1, $noreg, 0, $noreg :: (load 2 from %stack.1)
|
||||
; CHECK: [[OR32ri:%[0-9]+]]:gr32 = OR32ri killed [[MOVZX32rm16_]], 3072, implicit-def $eflags
|
||||
@ -59,7 +59,7 @@ entry:
|
||||
define i8 @f20s8(double %x) #0 {
|
||||
entry:
|
||||
; CHECK-LABEL: name: f20s8
|
||||
; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[COPY:%[0-9]+]]:gr32_abcd = COPY [[CVTTSD2SIrm]]
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
|
||||
; CHECK: $al = COPY [[COPY1]]
|
||||
@ -71,7 +71,7 @@ entry:
|
||||
define i16 @f20s16(double %x) #0 {
|
||||
entry:
|
||||
; CHECK-LABEL: name: f20s16
|
||||
; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY [[CVTTSD2SIrm]].sub_16bit
|
||||
; CHECK: $ax = COPY [[COPY]]
|
||||
; CHECK: RET 0, $ax
|
||||
@ -84,15 +84,15 @@ entry:
|
||||
; CHECK-LABEL: name: f20u
|
||||
; CHECK: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
|
||||
; CHECK: [[MOVSDrm_alt1:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool)
|
||||
; CHECK: fpexcept COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
|
||||
; CHECK: COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
|
||||
; CHECK: [[FsFLD0SD:%[0-9]+]]:fr64 = FsFLD0SD
|
||||
; CHECK: JCC_1
|
||||
; CHECK: [[PHI:%[0-9]+]]:fr64 = PHI [[MOVSDrm_alt1]], {{.*}}, [[FsFLD0SD]], {{.*}}
|
||||
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
|
||||
; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
|
||||
; CHECK: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[MOVZX32rr8_]], 31, implicit-def dead $eflags
|
||||
; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = fpexcept SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
|
||||
; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrr killed [[SUBSDrr]], implicit $mxcsr
|
||||
; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
|
||||
; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr killed [[SUBSDrr]], implicit $mxcsr
|
||||
; CHECK: [[XOR32rr:%[0-9]+]]:gr32 = XOR32rr [[CVTTSD2SIrr]], killed [[SHL32ri]], implicit-def dead $eflags
|
||||
; CHECK: $eax = COPY [[XOR32rr]]
|
||||
; CHECK: RET 0, $eax
|
||||
|
||||
@ -7,18 +7,18 @@ define float @foo(float %f) #0 {
|
||||
; CHECK: body:
|
||||
; CHECK: %0:fr32 = COPY $xmm0
|
||||
; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0
|
||||
; CHECK: %3:fr32 = VMULSSrr %0, %1
|
||||
; CHECK: %3:fr32 = nofpexcept VMULSSrr %0, %1
|
||||
; CHECK: %4:fr32 = VMOVSSrm
|
||||
; CHECK: %5:fr32 = VFMADD213SSr %1, killed %3, %4
|
||||
; CHECK: %5:fr32 = nofpexcept VFMADD213SSr %1, killed %3, %4
|
||||
; CHECK: %6:fr32 = VMOVSSrm
|
||||
; CHECK: %7:fr32 = VMULSSrr %1, %6
|
||||
; CHECK: %8:fr32 = VMULSSrr killed %7, killed %5
|
||||
; CHECK: %9:fr32 = VMULSSrr %0, %8
|
||||
; CHECK: %10:fr32 = VFMADD213SSr %8, %9, %4
|
||||
; CHECK: %11:fr32 = VMULSSrr %9, %6
|
||||
; CHECK: %12:fr32 = VMULSSrr killed %11, killed %10
|
||||
; CHECK: %7:fr32 = nofpexcept VMULSSrr %1, %6
|
||||
; CHECK: %8:fr32 = nofpexcept VMULSSrr killed %7, killed %5
|
||||
; CHECK: %9:fr32 = nofpexcept VMULSSrr %0, %8
|
||||
; CHECK: %10:fr32 = nofpexcept VFMADD213SSr %8, %9, %4
|
||||
; CHECK: %11:fr32 = nofpexcept VMULSSrr %9, %6
|
||||
; CHECK: %12:fr32 = nofpexcept VMULSSrr killed %11, killed %10
|
||||
; CHECK: %14:fr32 = FsFLD0SS
|
||||
; CHECK: %15:fr32 = VCMPSSrr %0, killed %14, 0
|
||||
; CHECK: %15:fr32 = nofpexcept VCMPSSrr %0, killed %14, 0
|
||||
; CHECK: %17:vr128 = VPANDNrr killed %16, killed %13
|
||||
; CHECK: $xmm0 = COPY %18
|
||||
; CHECK: RET 0, $xmm0
|
||||
@ -31,16 +31,16 @@ define float @rfoo(float %f) #0 {
|
||||
; CHECK: body: |
|
||||
; CHECK: %0:fr32 = COPY $xmm0
|
||||
; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0
|
||||
; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %0, %1
|
||||
; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %0, %1
|
||||
; CHECK: %4:fr32 = VMOVSSrm
|
||||
; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc VFMADD213SSr %1, killed %3, %4
|
||||
; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %1, killed %3, %4
|
||||
; CHECK: %6:fr32 = VMOVSSrm
|
||||
; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %1, %6
|
||||
; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr killed %7, killed %5
|
||||
; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %0, %8
|
||||
; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc VFMADD213SSr %8, killed %9, %4
|
||||
; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %8, %6
|
||||
; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr killed %11, killed %10
|
||||
; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %1, %6
|
||||
; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed %5
|
||||
; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %0, %8
|
||||
; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %8, killed %9, %4
|
||||
; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %8, %6
|
||||
; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %11, killed %10
|
||||
; CHECK: $xmm0 = COPY %12
|
||||
; CHECK: RET 0, $xmm0
|
||||
%sqrt = tail call float @llvm.sqrt.f32(float %f)
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
define <1 x float> @constrained_vector_fadd_v1f32() #0 {
|
||||
; CHECK-LABEL: name: constrained_vector_fadd_v1f32
|
||||
; CHECK: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: $xmm0 = COPY [[ADDSSrm]]
|
||||
; CHECK: RET 0, $xmm0
|
||||
entry:
|
||||
@ -15,9 +15,9 @@ define <3 x float> @constrained_vector_fadd_v3f32() #0 {
|
||||
; CHECK-LABEL: name: constrained_vector_fadd_v3f32
|
||||
; CHECK: [[FsFLD0SS:%[0-9]+]]:fr32 = FsFLD0SS
|
||||
; CHECK: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrr:%[0-9]+]]:fr32 = fpexcept ADDSSrr [[MOVSSrm_alt]], killed [[FsFLD0SS]], implicit $mxcsr
|
||||
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrm1:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[MOVSSrm_alt]], killed [[FsFLD0SS]], implicit $mxcsr
|
||||
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[ADDSSrm1:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
|
||||
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY [[ADDSSrm1]]
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[ADDSSrm]]
|
||||
; CHECK: [[UNPCKLPSrr:%[0-9]+]]:vr128 = UNPCKLPSrr [[COPY1]], killed [[COPY]]
|
||||
@ -38,8 +38,8 @@ entry:
|
||||
define <4 x double> @constrained_vector_fadd_v4f64() #0 {
|
||||
; CHECK-LABEL: name: constrained_vector_fadd_v4f64
|
||||
; CHECK: [[MOVAPDrm:%[0-9]+]]:vr128 = MOVAPDrm $rip, 1, $noreg, %const.0, $noreg :: (load 16 from constant-pool)
|
||||
; CHECK: [[ADDPDrm:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
|
||||
; CHECK: [[ADDPDrm1:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
|
||||
; CHECK: [[ADDPDrm:%[0-9]+]]:vr128 = ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
|
||||
; CHECK: [[ADDPDrm1:%[0-9]+]]:vr128 = ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
|
||||
; CHECK: $xmm0 = COPY [[ADDPDrm]]
|
||||
; CHECK: $xmm1 = COPY [[ADDPDrm1]]
|
||||
; CHECK: RET 0, $xmm0, $xmm1
|
||||
|
||||
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Reference in New Issue
Block a user