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[AArch64][SME] Improve diagnostic for vector select register

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Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D106540
This commit is contained in:
Cullen Rhodes 2021-07-22 13:46:19 +00:00
parent 19374d4da0
commit 5202ca9718
16 changed files with 36 additions and 31 deletions
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4
lib/Target/AArch64/AArch64RegisterInfo.td
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@ -1352,7 +1352,9 @@ class MatrixOperand<RegisterClass RC, int EltSize> : RegisterOperand<RC> {
def MatrixOp : MatrixOperand<MPR, 0>;
def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>;
def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)> {
let DiagnosticType = "InvalidMatrixIndexGPR32_12_15";
}
def MatrixIndexGPR32Op12_15 : RegisterOperand<MatrixIndexGPR32_12_15> {
let EncoderMethod = "encodeMatrixIndexGPR32";
}

3
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -5102,6 +5102,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
return Error(Loc, "invalid matrix operand, expected za[0-7].d");
case Match_InvalidMatrix:
return Error(Loc, "invalid matrix operand, expected za");
case Match_InvalidMatrixIndexGPR32_12_15:
return Error(Loc, "operand must be a register in range [w12, w15]");
default:
llvm_unreachable("unexpected error code!");
}
@ -5637,6 +5639,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidMatrixTileVectorV64:
case Match_InvalidMatrixTileVectorV128:
case Match_InvalidSVCR:
case Match_InvalidMatrixIndexGPR32_12_15:
case Match_MSR:
case Match_MRS: {
if (ErrorInfo >= Operands.size())

4
test/MC/AArch64/SME/dup-diagnostics.s
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@ -25,12 +25,12 @@ dup p0.b, p0/z, p0[w12]
// Invalid index base register register (w12-w15)
dup p0.b, p0/z, p0.b[w11]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: dup p0.b, p0/z, p0.b[w11]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
dup p0.b, p0/z, p0.b[w16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: dup p0.b, p0/z, p0.b[w16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/ld1b-diagnostics.s
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@ -22,12 +22,12 @@ ld1b {za15v.q[w12, #0]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
ld1b {za0h.b[w11, #0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1b {za0h.b[w11, #0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1b {za0h.b[w16, #0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1b {za0h.b[w16, #0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/ld1d-diagnostics.s
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@ -22,12 +22,12 @@ ld1d {za3h.s[w12, #0]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
ld1d {za0h.d[w11, #0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1d {za0h.d[w11, #0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1d {za0h.d[w16, #0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1d {za0h.d[w16, #0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/ld1h-diagnostics.s
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@ -22,12 +22,12 @@ ld1h {za0.b[w12, #0]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
ld1h {za0h.h[w11, #0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1h {za0h.h[w11, #0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1h {za0h.h[w16, #0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1h {za0h.h[w16, #0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/ld1q-diagnostics.s
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@ -22,12 +22,12 @@ ld1q {za7v.d[w12]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
ld1q {za0h.q[w11]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1q {za0h.q[w11]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1q {za0h.q[w16]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1q {za0h.q[w16]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/ld1w-diagnostics.s
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@ -22,12 +22,12 @@ ld1w {za1v.h[w12, #0]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
ld1w {za0h.s[w11, #0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1w {za0h.s[w11, #0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1w {za0h.s[w16, #0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ld1w {za0h.s[w16, #0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/ldr-diagnostics.s
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@ -17,12 +17,12 @@ ldr za3.s[w12, #0], [x0]
// Invalid vector select register (expected: w12-w15)
ldr za[w11, #0], [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ldr za[w11, #0], [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldr za[w16, #0], [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: ldr za[w16, #0], [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

8
test/MC/AArch64/SME/mova-diagnostics.s
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@ -107,22 +107,22 @@ mova za[w12, #0], p0/m, z0.b
// Invalid vector select register (expected: w12-w15)
mova z0.h, p0/m, za0h.h[w11, #0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: mova z0.h, p0/m, za0h.h[w11, #0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mova z0.s, p0/m, za0h.s[w16, #0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: mova z0.s, p0/m, za0h.s[w16, #0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mova za0h.d[w11, #0], p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: mova za0h.d[w11, #0], p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mova za0h.q[w16, #0], p0/m, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: mova za0h.q[w16, #0], p0/m, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/st1b-diagnostics.s
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@ -22,12 +22,12 @@ st1b {za15v.q[w12, #0]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
st1b {za0h.b[w11, #0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1b {za0h.b[w11, #0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1b {za0h.b[w16, #0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1b {za0h.b[w16, #0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/st1d-diagnostics.s
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@ -22,12 +22,12 @@ st1d {za3h.s[w12, #0]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
st1d {za0h.d[w11, #0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1d {za0h.d[w11, #0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1d {za0h.d[w16, #0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1d {za0h.d[w16, #0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/st1h-diagnostics.s
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@ -22,12 +22,12 @@ st1h {za0.b[w12, #0]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
st1h {za0h.h[w11, #0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1h {za0h.h[w11, #0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1h {za0h.h[w16, #0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1h {za0h.h[w16, #0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/st1q-diagnostics.s
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@ -22,12 +22,12 @@ st1q {za7v.d[w12]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
st1q {za0h.q[w11]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1q {za0h.q[w11]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1q {za0h.q[w16]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1q {za0h.q[w16]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/st1w-diagnostics.s
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@ -22,12 +22,12 @@ st1w {za1v.h[w12, #0]}, p0/z, [x0]
// Invalid vector select register (expected: w12-w15)
st1w {za0h.s[w11, #0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1w {za0h.s[w11, #0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1w {za0h.s[w16, #0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: st1w {za0h.s[w16, #0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
test/MC/AArch64/SME/str-diagnostics.s
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@ -17,12 +17,12 @@ str za3.s[w12, #0], [x0]
// Invalid vector select register (expected: w12-w15)
str za[w11, #0], [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: str za[w11, #0], [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
str za[w16, #0], [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: str za[w16, #0], [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: