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[SDAG] Ignore chain operand in REG_SEQUENCE when emitting instructions

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llvm-svn: 349186
This commit is contained in:
Krzysztof Parzyszek 2018-12-14 20:14:12 +00:00
parent 6f096d4f5a
commit 52a4d61628
1 changed files with 4 additions and 0 deletions
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4
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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@ -652,6 +652,10 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
unsigned NumOps = Node->getNumOperands();
// REG_SEQUENCE can "inherit" a chain from a subnode.
if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
--NumOps; // Ignore chain if it exists.
assert((NumOps & 1) == 1 &&
"REG_SEQUENCE must have an odd number of operands!");
for (unsigned i = 1; i != NumOps; ++i) {