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[mips] Add madd4 subtarget feature
Addition of a feature and a predicate used to control generation of madd.fmt and similar instructions. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33400 llvm-svn: 304801
This commit is contained in:
Petar Jovanovic
parent
c26a4baf9a
commit
53474bdb0f
@ -185,6 +185,9 @@ def FeatureUseTCCInDIV : SubtargetFeature<
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"UseTCCInDIV", "false",
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"Force the assembler to use trapping">;
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def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
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"Disable 4-operand madd.fmt and related instructions">;
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//===----------------------------------------------------------------------===//
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// Mips processors supported.
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//===----------------------------------------------------------------------===//
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@ -557,11 +557,11 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
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defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
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def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
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MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
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MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
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def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
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MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
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MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
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let AdditionalPredicates = [NoNaNsFPMath] in {
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let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
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def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
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MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
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def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
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@ -569,11 +569,11 @@ let AdditionalPredicates = [NoNaNsFPMath] in {
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}
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def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
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MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
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MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
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def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
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MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
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MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
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let AdditionalPredicates = [NoNaNsFPMath] in {
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let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
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def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
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MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
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def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
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@ -582,12 +582,12 @@ let AdditionalPredicates = [NoNaNsFPMath] in {
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let DecoderNamespace = "Mips64" in {
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def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
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MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
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MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
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def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
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MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
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MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
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}
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let AdditionalPredicates = [NoNaNsFPMath],
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let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
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DecoderNamespace = "Mips64" in {
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def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
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MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
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@ -238,6 +238,8 @@ def HasEVA : Predicate<"Subtarget->hasEVA()">,
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AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
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def HasMSA : Predicate<"Subtarget->hasMSA()">,
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AssemblerPredicate<"FeatureMSA">;
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def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
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AssemblerPredicate<"!FeatureMadd4">;
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//===----------------------------------------------------------------------===//
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@ -390,6 +392,10 @@ class ASE_NOT_DSP {
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list<Predicate> InsnPredicates = [NotDSP];
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}
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class MADD4 {
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list<Predicate> AdditionalPredicates = [HasMadd4];
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}
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//===----------------------------------------------------------------------===//
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class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
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@ -70,7 +70,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
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Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
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HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(),
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HasEVA(false), DisableMadd4(false), TM(TM), TargetTriple(TT), TSInfo(),
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InstrInfo(
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MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
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FrameLowering(MipsFrameLowering::create(*this)),
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@ -144,6 +144,10 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
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// HasEVA -- supports EVA ASE.
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bool HasEVA;
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// nomadd4 - disables generation of 4-operand madd.s, madd.d and
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// related instructions.
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bool DisableMadd4;
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InstrItineraryData InstrItins;
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@ -253,6 +257,7 @@ public:
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bool hasDSPR2() const { return HasDSPR2; }
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bool hasDSPR3() const { return HasDSPR3; }
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bool hasMSA() const { return HasMSA; }
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bool disableMadd4() const { return DisableMadd4; }
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bool hasEVA() const { return HasEVA; }
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bool useSmallSection() const { return UseSmallSection; }
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@ -5,52 +5,63 @@
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; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only
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; available when -enable-no-nans-fp-math is given.
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32,32-NONAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6,32R6-NONAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NONAN-NOMADD
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6,64R6-NONAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32,32-NAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
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; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6,32R6-NAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NAN-NOMADD
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6,64R6-NAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
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; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated
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; when +nomadd attribute is specified.
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; Output for mips32 and mips64r6 reused since aforementioned instructions are
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; not generated in those cases.
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
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define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO0float:
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; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2: add.s $f0, $[[T1]], $[[T2]]
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; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2: add.s $f0, $[[T1]], $[[T2]]
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; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
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; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
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; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64R2: add.s $f0, $[[T0]], $[[T1]]
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; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64R2: add.s $f0, $[[T0]], $[[T1]]
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; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
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; 64R6-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
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; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
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; 64R6-NOMADD-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
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; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
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%mul = fmul float %a, %b
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%add = fadd float %mul, %c
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@ -62,35 +73,35 @@ define float @FOO1float(float %a, float %b, float %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO1float:
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; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2: add.s $f0, $[[T1]], $[[T2]]
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; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2: add.s $f0, $[[T1]], $[[T2]]
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; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
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; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
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; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2: add.s $f0, $[[T0]], $[[T1]]
|
||||
; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2: add.s $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
|
||||
; 64R6-DAG: sub.s $[[T1:f[0-9]+]], $[[T0]], $f14
|
||||
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]]
|
||||
; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
|
||||
; 64R6-NOMADD-DAG: sub.s $[[T1:f[0-9]+]], $[[T0]], $f14
|
||||
; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%sub = fsub float %mul, %c
|
||||
@ -102,42 +113,42 @@ define float @FOO2float(float %a, float %b, float %c) nounwind readnone {
|
||||
entry:
|
||||
; ALL-LABEL: FOO2float:
|
||||
|
||||
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
|
||||
; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
|
||||
|
||||
; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
|
||||
; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
|
||||
; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
|
||||
|
||||
; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
|
||||
; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
|
||||
|
||||
; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
|
||||
; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
|
||||
|
||||
; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
|
||||
; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
|
||||
|
||||
; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
; 64R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%add = fadd float %mul, %c
|
||||
@ -149,34 +160,34 @@ define float @FOO3float(float %a, float %b, float %c) nounwind readnone {
|
||||
entry:
|
||||
; ALL-LABEL: FOO3float:
|
||||
|
||||
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
|
||||
; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
|
||||
|
||||
; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
|
||||
; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
|
||||
; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
|
||||
; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
|
||||
|
||||
; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13
|
||||
; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13
|
||||
|
||||
; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
|
||||
; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
|
||||
|
||||
; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
; 64R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%sub = fsub float %mul, %c
|
||||
@ -188,36 +199,36 @@ define double @FOO10double(double %a, double %b, double %c) nounwind readnone {
|
||||
entry:
|
||||
; ALL-LABEL: FOO10double:
|
||||
|
||||
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
|
||||
; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2: mthc1 $zero, $[[T2]]
|
||||
; 32R2: add.d $f0, $[[T1]], $[[T2]]
|
||||
; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2: mthc1 $zero, $[[T2]]
|
||||
; 32R2: add.d $f0, $[[T1]], $[[T2]]
|
||||
|
||||
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
|
||||
; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
|
||||
; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2: add.d $f0, $[[T0]], $[[T1]]
|
||||
; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2: add.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
|
||||
%mul = fmul double %a, %b
|
||||
%add = fadd double %mul, %c
|
||||
@ -229,36 +240,36 @@ define double @FOO11double(double %a, double %b, double %c) nounwind readnone {
|
||||
entry:
|
||||
; ALL-LABEL: FOO11double:
|
||||
|
||||
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
|
||||
; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2: mthc1 $zero, $[[T2]]
|
||||
; 32R2: add.d $f0, $[[T1]], $[[T2]]
|
||||
; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2: mthc1 $zero, $[[T2]]
|
||||
; 32R2: add.d $f0, $[[T1]], $[[T2]]
|
||||
|
||||
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
|
||||
; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
|
||||
; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2: add.d $f0, $[[T0]], $[[T1]]
|
||||
; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2: add.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
|
||||
|
||||
%mul = fmul double %a, %b
|
||||
%sub = fsub double %mul, %c
|
||||
@ -270,43 +281,43 @@ define double @FOO12double(double %a, double %b, double %c) nounwind readnone {
|
||||
entry:
|
||||
; ALL-LABEL: FOO12double:
|
||||
|
||||
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
|
||||
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
|
||||
|
||||
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2-NAN: mthc1 $zero, $[[T2]]
|
||||
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
|
||||
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2-NAN: mthc1 $zero, $[[T2]]
|
||||
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13
|
||||
; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13
|
||||
|
||||
; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
||||
; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
||||
|
||||
; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
|
||||
; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
|
||||
|
||||
; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
||||
; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
||||
|
||||
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
|
||||
%mul = fmul double %a, %b
|
||||
%add = fadd double %mul, %c
|
||||
@ -318,43 +329,43 @@ define double @FOO13double(double %a, double %b, double %c) nounwind readnone {
|
||||
entry:
|
||||
; ALL-LABEL: FOO13double:
|
||||
|
||||
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
|
||||
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
|
||||
|
||||
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2-NAN: mthc1 $zero, $[[T2]]
|
||||
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
|
||||
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
||||
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R2-NAN: mthc1 $zero, $[[T2]]
|
||||
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
||||
; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
||||
; 32R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 32R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
|
||||
; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13
|
||||
; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13
|
||||
|
||||
; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
||||
; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
||||
|
||||
; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
|
||||
; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
|
||||
|
||||
; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
||||
; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
||||
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
||||
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
||||
|
||||
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
||||
; 64R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
||||
; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
||||
; 64R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
||||
|
||||
%mul = fmul double %a, %b
|
||||
%sub = fsub double %mul, %c
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user