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Add sanity check for Ld/St Dual forms of Thumb2 instructions.

Browse Source 
rdar://problem/9273947

llvm-svn: 129411
This commit is contained in:
Johnny Chen 2011-04-12 23:31:00 +00:00
parent b2c47a2087
commit 5ae9980472
3 changed files with 52 additions and 0 deletions
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29
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@ -1275,6 +1275,35 @@ static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode,
&& OpInfo[3].RegClass < 0
&& "Expect >= 4 operands and first 3 as reg operands");
// Thumnb allows for specifying Rt and Rt2, unlike ARM (which has Rt2==Rt+1).
unsigned Rt = decodeRd(insn);
unsigned Rt2 = decodeRs(insn);
unsigned Rn = decodeRn(insn);
// Some sanity checking first.
// A8.6.67 LDRD (literal) has its W bit as (0).
if (Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2LDRD_PRE || Opcode == ARM::t2LDRD_POST) {
if (Rn == 15 && slice(insn, 21, 21) != 0)
return false;
} else {
// For Dual Store, PC cannot be used as the base register.
if (Rn == 15) {
DEBUG(errs() << "if n == 15 then UNPREDICTABLE\n");
return false;
}
}
if (Rt == Rt2) {
DEBUG(errs() << "if t == t2 then UNPREDICTABLE\n");
return false;
}
if (Opcode != ARM::t2LDRDi8 && Opcode != ARM::t2STRDi8) {
if (Rn == Rt || Rn == Rt2) {
DEBUG(errs() << "if wback && (n == t || n == t2) then UNPREDICTABLE\n");
return false;
}
}
// Add the <Rt> <Rt2> operands.
unsigned RegClassPair = OpInfo[0].RegClass;
unsigned RegClassBase = OpInfo[2].RegClass;

13
test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt Normal file
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@ -0,0 +1,13 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
# -------------------------------------------------------------------------------------------------
#
# A8.6.66 LDRD (immediate)
# if Rn = '1111' then SEE LDRD (literal)
# A8.6.67 LDRD (literal)
# Inst{21} = 0
0xff 0xe9 0x0 0xeb

10
test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt Normal file
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@ -0,0 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
#
# if wback && (n == t || n == t2) then UNPREDICTABLE
0xe4 0xe9 0x02 0x46