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[AArch64][GlobalISel] Add some missing vector support for FP arithmetic ops.
Moved the fneg lowering legalization test from AArch64 to X86, as we want to specify that it's already legal. llvm-svn: 352338
This commit is contained in:
Amara Emerson
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@ -119,8 +119,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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getActionDefinitionsBuilder({G_UADDE, G_USUBE, G_SADDO, G_SSUBO})
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.legalFor({{s32, s1}, {s64, s1}});
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMA, G_FMUL, G_FDIV})
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.legalFor({s32, s64});
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMA, G_FMUL, G_FDIV, G_FNEG})
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.legalFor({s32, s64, v2s64, v4s32, v2s32});
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getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
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75
test/CodeGen/AArch64/GlobalISel/legalize-fp-arith.mir
Normal file
75
test/CodeGen/AArch64/GlobalISel/legalize-fp-arith.mir
Normal file
@ -0,0 +1,75 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_fadd_v2s64
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_fadd_v2s64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
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; CHECK: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[FADD]](<2 x s64>)
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = COPY $q1
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%2:_(<2 x s64>) = G_FADD %0, %1
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$q0 = COPY %2(<2 x s64>)
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...
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---
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name: test_fdiv_v2s32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_fdiv_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK: [[FDIV:%[0-9]+]]:_(<2 x s32>) = G_FDIV [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[FDIV]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = COPY $d1
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%2:_(<2 x s32>) = G_FDIV %0, %1
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$d0 = COPY %2(<2 x s32>)
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...
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---
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name: test_fsub_v2s32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_fsub_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK: [[FSUB:%[0-9]+]]:_(<2 x s32>) = G_FSUB [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[FSUB]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = COPY $d1
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%2:_(<2 x s32>) = G_FSUB %0, %1
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$d0 = COPY %2(<2 x s32>)
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...
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---
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name: test_fneg_v2s32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_fneg_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[FNEG:%[0-9]+]]:_(<2 x s32>) = G_FNEG [[COPY]]
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; CHECK: $d0 = COPY [[FNEG]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = G_FNEG %0
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$d0 = COPY %1(<2 x s32>)
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...
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---
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name: test_fmul_v4s32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_fmul_v4s32
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[FMUL]](<4 x s32>)
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%2:_(<4 x s32>) = G_FMUL %0, %1
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$q0 = COPY %2(<4 x s32>)
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...
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@ -197,6 +197,24 @@ body: |
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$x0 = COPY %2
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...
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---
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name: test_uitofp_s64_s8
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: test_uitofp_s64_s8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
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; CHECK: $x0 = COPY [[UITOFP]](s64)
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%0:_(s32) = COPY $w0
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%1:_(s8) = G_TRUNC %0
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%2:_(s64) = G_UITOFP %1
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$x0 = COPY %2
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...
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---
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name: test_sitofp_v4s32
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body: |
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@ -225,24 +243,6 @@ body: |
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$q0 = COPY %1
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...
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---
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name: test_uitofp_s64_s8
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: test_uitofp_s64_s8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
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; CHECK: $x0 = COPY [[UITOFP]](s64)
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%0:_(s32) = COPY $w0
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%1:_(s8) = G_TRUNC %0
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%2:_(s64) = G_UITOFP %1
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$x0 = COPY %2
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...
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---
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name: test_sitofp_s32_s16
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body: |
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@ -271,7 +271,7 @@
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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#
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# DEBUG-NEXT: G_FNEG (opcode {{[0-9]+}}): 1 type index
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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# DEBUG: .. the first uncovered type index: 1, OK
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#
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# DEBUG-NEXT: G_FPEXT (opcode {{[0-9]+}}): 2 type indices
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# DEBUG: .. the first uncovered type index: 2, OK
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@ -2,8 +2,7 @@
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# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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target triple = "x86_64--"
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define void @test_fneg_f32() {
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entry:
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ret void
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@ -20,15 +19,15 @@ registers:
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- { id: 1, class: _ }
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body: |
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bb.1:
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liveins: $s0
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liveins:
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; CHECK-LABEL: name: test_fneg_f32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -0.000000e+00
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; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[C]], [[COPY]]
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; CHECK: $s0 = COPY [[FSUB]](s32)
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%0(s32) = COPY $s0
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; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[C]], [[DEF]]
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; CHECK: $edi = COPY [[FSUB]](s32)
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%0(s32) = IMPLICIT_DEF
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%1(s32) = G_FNEG %0
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$s0 = COPY %1(s32)
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$edi = COPY %1
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...
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---
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name: test_fneg_f64
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@ -37,13 +36,13 @@ registers:
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- { id: 1, class: _ }
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body: |
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bb.1:
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liveins: $d0
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liveins:
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; CHECK-LABEL: name: test_fneg_f64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -0.000000e+00
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; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[C]], [[COPY]]
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; CHECK: $d0 = COPY [[FSUB]](s64)
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%0(s64) = COPY $d0
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; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[C]], [[DEF]]
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; CHECK: $rdi = COPY [[FSUB]](s64)
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%0(s64) = G_IMPLICIT_DEF
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%1(s64) = G_FNEG %0
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$d0 = COPY %1(s64)
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$rdi = COPY %1
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...
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