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Reduce global namespace pollution. NFC.
llvm-svn: 284521
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@ -41,7 +41,7 @@
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using namespace llvm;
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using namespace lto;
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LLVM_ATTRIBUTE_NORETURN void reportOpenError(StringRef Path, Twine Msg) {
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LLVM_ATTRIBUTE_NORETURN static void reportOpenError(StringRef Path, Twine Msg) {
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errs() << "failed to open " << Path << ": " << Msg << '\n';
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errs().flush();
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exit(1);
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@ -1194,7 +1194,7 @@ StringRef sys::getHostCPUName() { return "generic"; }
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// On Linux, the number of physical cores can be computed from /proc/cpuinfo,
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// using the number of unique physical/core id pairs. The following
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// implementation reads the /proc/cpuinfo format on an x86_64 system.
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int computeHostNumPhysicalCores() {
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static int computeHostNumPhysicalCores() {
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// Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
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// mmapped because it appears to have 0 size.
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llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
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@ -1236,7 +1236,7 @@ int computeHostNumPhysicalCores() {
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}
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#else
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// On other systems, return -1 to indicate unknown.
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int computeHostNumPhysicalCores() { return -1; }
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static int computeHostNumPhysicalCores() { return -1; }
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#endif
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int sys::getHostNumPhysicalCores() {
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@ -47,8 +47,9 @@ LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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// Forward declare because the autogenerated code will reference this.
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// Definition is further down.
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DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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@ -73,11 +73,12 @@ static MCInstPrinter *createLanaiMCInstPrinter(const Triple & /*T*/,
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return 0;
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}
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MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple,
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MCContext &Ctx) {
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static MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple,
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MCContext &Ctx) {
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return createMCRelocationInfo(TheTriple, Ctx);
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}
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namespace {
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class LanaiMCInstrAnalysis : public MCInstrAnalysis {
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public:
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explicit LanaiMCInstrAnalysis(const MCInstrInfo *Info)
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@ -106,6 +107,7 @@ public:
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}
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}
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};
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} // end anonymous namespace
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static MCInstrAnalysis *createLanaiInstrAnalysis(const MCInstrInfo *Info) {
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return new LanaiMCInstrAnalysis(Info);
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@ -29151,7 +29151,8 @@ static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, SelectionDAG &DAG,
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// into:
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// srl(ctlz x), log2(bitsize(x))
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// Input pattern is checked by caller.
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SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy, SelectionDAG &DAG) {
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static SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy,
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SelectionDAG &DAG) {
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SDValue Cmp = Op.getOperand(1);
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EVT VT = Cmp.getOperand(0).getValueType();
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unsigned Log2b = Log2_32(VT.getSizeInBits());
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@ -16,6 +16,7 @@
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#include "X86InstrInfo.h"
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#include "llvm/Support/ManagedStatic.h"
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#include "llvm/Support/Threading.h"
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using namespace llvm;
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/// This flag is used in the method llvm::call_once() used below to make the
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/// initialization of the map 'OpcodeToGroup' thread safe.
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@ -20,8 +20,7 @@
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#include <cassert>
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#include <set>
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using namespace llvm;
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namespace llvm {
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/// This class is used to group {132, 213, 231} forms of FMA opcodes together.
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/// Each of the groups has either 3 register opcodes, 3 memory opcodes,
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/// or 6 register and memory opcodes. Also, each group has an attrubutes field
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@ -311,5 +310,6 @@ public:
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return rm_iterator(getX86InstrFMA3Info()->OpcodeToGroup.end());
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}
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};
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} // namespace llvm
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#endif
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