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[Hexagon] Add LLVM instruction definitions for Hexagon V68
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@ -48,7 +48,10 @@ def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion",
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def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V67", "Hexagon HVX instructions",
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[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>;
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def ExtensionHVXV68: SubtargetFeature<"hvxv68", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V68", "Hexagon HVX instructions",
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[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
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ExtensionHVXV67]>;
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def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
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"true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
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@ -107,6 +110,8 @@ def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">,
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AssemblerPredicate<(all_of ExtensionHVXV66)>;
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def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">,
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AssemblerPredicate<(all_of ExtensionHVXV67)>;
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def UseHVXV68 : Predicate<"HST->useHVXV68Ops()">,
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AssemblerPredicate<(all_of ExtensionHVXV68)>;
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def UseAudio : Predicate<"HST->useAudioOps()">,
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AssemblerPredicate<(all_of ExtensionAudio)>;
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def UseZReg : Predicate<"HST->useZRegOps()">,
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@ -394,6 +399,11 @@ def : Proc<"hexagonv67", HexagonModelV67,
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[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
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FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
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FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv68", HexagonModelV68,
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[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
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ArchV68,
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FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
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FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
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// Need to update the correct features for tiny core.
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// Disable NewValueJumps since the packetizer is unable to handle a packet with
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// a new value jump and another SLOT0 instruction.
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@ -14,35 +14,76 @@
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include <map>
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#include <string>
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namespace llvm {
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namespace Hexagon {
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enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67 };
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enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67, V68 };
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static constexpr unsigned ArchValsNumArray[] = {5, 55, 60, 62, 65, 66, 67};
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static constexpr unsigned ArchValsNumArray[] = {5, 55, 60, 62, 65, 66, 67, 68};
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static constexpr ArrayRef<unsigned> ArchValsNum(ArchValsNumArray);
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static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67" };
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static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v68" };
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static constexpr ArrayRef<StringLiteral> ArchValsText(ArchValsTextArray);
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static constexpr StringLiteral CpuValsTextArray[] = { "hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65", "hexagonv66", "hexagonv67", "hexagonv67t" };
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static constexpr StringLiteral CpuValsTextArray[] = { "hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65", "hexagonv66", "hexagonv67", "hexagonv67t", "hexagonv68" };
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static constexpr ArrayRef<StringLiteral> CpuValsText(CpuValsTextArray);
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static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v67t" };
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static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v67t", "v68" };
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static constexpr ArrayRef<StringLiteral> CpuNickText(CpuNickTextArray);
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static const std::map<std::string, ArchEnum> CpuTable{
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{"generic", Hexagon::ArchEnum::V60},
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{"hexagonv5", Hexagon::ArchEnum::V5},
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{"hexagonv55", Hexagon::ArchEnum::V55},
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{"hexagonv60", Hexagon::ArchEnum::V60},
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{"hexagonv62", Hexagon::ArchEnum::V62},
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{"hexagonv65", Hexagon::ArchEnum::V65},
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{"hexagonv66", Hexagon::ArchEnum::V66},
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{"hexagonv67", Hexagon::ArchEnum::V67},
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{"hexagonv67t", Hexagon::ArchEnum::V67},
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{"generic", Hexagon::ArchEnum::V5},
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{"hexagonv5", Hexagon::ArchEnum::V5},
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{"hexagonv55", Hexagon::ArchEnum::V55},
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{"hexagonv60", Hexagon::ArchEnum::V60},
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{"hexagonv62", Hexagon::ArchEnum::V62},
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{"hexagonv65", Hexagon::ArchEnum::V65},
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{"hexagonv66", Hexagon::ArchEnum::V66},
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{"hexagonv67", Hexagon::ArchEnum::V67},
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{"hexagonv67t", Hexagon::ArchEnum::V67},
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{"hexagonv68", Hexagon::ArchEnum::V68},
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};
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static const std::map<std::string, unsigned> ElfFlagsByCpuStr = {
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{"generic", llvm::ELF::EF_HEXAGON_MACH_V5},
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{"hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5},
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{"hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55},
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{"hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60},
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{"hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62},
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{"hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65},
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{"hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66},
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{"hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67},
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{"hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T},
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{"hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68},
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};
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static const std::map<unsigned, std::string> ElfArchByMachFlags = {
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{llvm::ELF::EF_HEXAGON_MACH_V5, "V5"},
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{llvm::ELF::EF_HEXAGON_MACH_V55, "V55"},
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{llvm::ELF::EF_HEXAGON_MACH_V60, "V60"},
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{llvm::ELF::EF_HEXAGON_MACH_V62, "V62"},
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{llvm::ELF::EF_HEXAGON_MACH_V65, "V65"},
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{llvm::ELF::EF_HEXAGON_MACH_V66, "V66"},
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{llvm::ELF::EF_HEXAGON_MACH_V67, "V67"},
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{llvm::ELF::EF_HEXAGON_MACH_V67T, "V67T"},
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{llvm::ELF::EF_HEXAGON_MACH_V68, "V68"},
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};
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static const std::map<unsigned, std::string> ElfCpuByMachFlags = {
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{llvm::ELF::EF_HEXAGON_MACH_V5, "hexagonv5"},
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{llvm::ELF::EF_HEXAGON_MACH_V55, "hexagonv55"},
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{llvm::ELF::EF_HEXAGON_MACH_V60, "hexagonv60"},
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{llvm::ELF::EF_HEXAGON_MACH_V62, "hexagonv62"},
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{llvm::ELF::EF_HEXAGON_MACH_V65, "hexagonv65"},
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{llvm::ELF::EF_HEXAGON_MACH_V66, "hexagonv66"},
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{llvm::ELF::EF_HEXAGON_MACH_V67, "hexagonv67"},
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{llvm::ELF::EF_HEXAGON_MACH_V67T, "hexagonv67t"},
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{llvm::ELF::EF_HEXAGON_MACH_V68, "hexagonv68"},
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};
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} // namespace Hexagon
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} // namespace llvm;
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
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@ -22,3 +22,5 @@ def ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V
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def HasV66 : Predicate<"HST->hasV66Ops()">, AssemblerPredicate<(all_of ArchV66)>;
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def ArchV67: SubtargetFeature<"v67", "HexagonArchVersion", "Hexagon::ArchEnum::V67", "Enable Hexagon V67 architecture">;
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def HasV67 : Predicate<"HST->hasV67Ops()">, AssemblerPredicate<(all_of ArchV67)>;
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def ArchV68: SubtargetFeature<"v68", "HexagonArchVersion", "Hexagon::ArchEnum::V68", "Enable Hexagon V68 architecture">;
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def HasV68 : Predicate<"HST->hasV68Ops()">, AssemblerPredicate<(all_of ArchV68)>;
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@ -8,21 +8,14 @@
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// Automatically generated file, do not edit!
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//===----------------------------------------------------------------------===//
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// clang-format off
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#if defined(__clang__)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wunused-function"
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#endif
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static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp,
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static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<8>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<4>(MI, tmp, Decoder);
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signedDecoder<6>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
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@ -30,44 +23,49 @@ static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
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signedDecoder<12>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<5>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<13>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<6>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<14>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<3>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<4>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<5>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<6>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<7>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<6>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<9>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
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static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t, const void *Decoder) {
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signedDecoder<3>(MI, tmp, Decoder);
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signedDecoder<8>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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@ -75,4 +73,3 @@ static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
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#pragma clang diagnostic pop
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#endif
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// clang-format on
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File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
@ -8,6 +8,10 @@
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// Automatically generated file, do not edit!
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPITYPES_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPITYPES_H
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namespace llvm {
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namespace HexagonII {
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enum Type {
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@ -16,48 +20,50 @@ enum Type {
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TypeALU32_ADDI = 2,
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TypeALU64 = 3,
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TypeCJ = 4,
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TypeCR = 7,
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TypeCVI_4SLOT_MPY = 8,
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TypeCVI_GATHER = 9,
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TypeCVI_GATHER_DV = 10,
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TypeCVI_GATHER_RST = 11,
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TypeCVI_HIST = 12,
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TypeCVI_SCATTER = 13,
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TypeCVI_SCATTER_DV = 14,
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TypeCVI_SCATTER_NEW_RST = 15,
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TypeCVI_SCATTER_NEW_ST = 16,
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TypeCVI_SCATTER_RST = 17,
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TypeCVI_VA = 18,
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TypeCVI_VA_DV = 19,
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TypeCVI_VM_LD = 20,
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TypeCVI_VM_NEW_ST = 21,
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TypeCVI_VM_ST = 22,
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TypeCVI_VM_STU = 23,
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TypeCVI_VM_TMP_LD = 24,
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TypeCVI_VM_VP_LDU = 25,
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TypeCVI_VP = 26,
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TypeCVI_VP_VS = 27,
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TypeCVI_VS = 28,
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TypeCVI_VS_VX = 29,
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TypeCVI_VX = 30,
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TypeCVI_VX_DV = 31,
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TypeCVI_VX_LATE = 32,
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TypeCVI_ZW = 33,
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TypeDUPLEX = 34,
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TypeENDLOOP = 35,
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TypeEXTENDER = 36,
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TypeJ = 37,
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TypeLD = 38,
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TypeM = 39,
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TypeMAPPING = 40,
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TypeNCJ = 41,
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TypePSEUDO = 42,
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TypeST = 43,
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TypeSUBINSN = 44,
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TypeS_2op = 45,
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TypeS_3op = 46,
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TypeV2LDST = 49,
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TypeV4LDST = 50,
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TypeCR = 5,
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TypeCVI_4SLOT_MPY = 6,
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TypeCVI_GATHER = 7,
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TypeCVI_GATHER_DV = 8,
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TypeCVI_GATHER_RST = 9,
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TypeCVI_HIST = 10,
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TypeCVI_SCATTER = 11,
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TypeCVI_SCATTER_DV = 12,
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TypeCVI_SCATTER_NEW_RST = 13,
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TypeCVI_SCATTER_NEW_ST = 14,
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TypeCVI_SCATTER_RST = 15,
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TypeCVI_VA = 16,
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TypeCVI_VA_DV = 17,
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TypeCVI_VM_LD = 18,
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TypeCVI_VM_NEW_ST = 19,
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TypeCVI_VM_ST = 20,
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TypeCVI_VM_STU = 21,
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TypeCVI_VM_TMP_LD = 22,
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TypeCVI_VM_VP_LDU = 23,
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TypeCVI_VP = 24,
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TypeCVI_VP_VS = 25,
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TypeCVI_VS = 26,
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TypeCVI_VS_VX = 27,
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TypeCVI_VX = 28,
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TypeCVI_VX_DV = 29,
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TypeCVI_VX_LATE = 30,
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TypeCVI_ZW = 31,
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TypeDUPLEX = 32,
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TypeENDLOOP = 33,
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TypeEXTENDER = 34,
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TypeJ = 35,
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TypeLD = 36,
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TypeM = 37,
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TypeMAPPING = 38,
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TypeNCJ = 39,
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TypePSEUDO = 40,
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TypeST = 41,
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TypeSUBINSN = 42,
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TypeS_2op = 43,
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TypeS_3op = 44,
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TypeV2LDST = 47,
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TypeV4LDST = 48,
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};
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}
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}
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPITYPES_H
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@ -14,45 +14,45 @@ def TypeALU32_3op : IType<1>;
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def TypeALU32_ADDI : IType<2>;
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def TypeALU64 : IType<3>;
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def TypeCJ : IType<4>;
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def TypeCR : IType<7>;
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def TypeCVI_4SLOT_MPY : IType<8>;
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def TypeCVI_GATHER : IType<9>;
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def TypeCVI_GATHER_DV : IType<10>;
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def TypeCVI_GATHER_RST : IType<11>;
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def TypeCVI_HIST : IType<12>;
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def TypeCVI_SCATTER : IType<13>;
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def TypeCVI_SCATTER_DV : IType<14>;
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def TypeCVI_SCATTER_NEW_RST : IType<15>;
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def TypeCVI_SCATTER_NEW_ST : IType<16>;
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def TypeCVI_SCATTER_RST : IType<17>;
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def TypeCVI_VA : IType<18>;
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def TypeCVI_VA_DV : IType<19>;
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def TypeCVI_VM_LD : IType<20>;
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def TypeCVI_VM_NEW_ST : IType<21>;
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def TypeCVI_VM_ST : IType<22>;
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def TypeCVI_VM_STU : IType<23>;
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def TypeCVI_VM_TMP_LD : IType<24>;
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def TypeCVI_VM_VP_LDU : IType<25>;
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def TypeCVI_VP : IType<26>;
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def TypeCVI_VP_VS : IType<27>;
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def TypeCVI_VS : IType<28>;
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def TypeCVI_VS_VX : IType<29>;
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def TypeCVI_VX : IType<30>;
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def TypeCVI_VX_DV : IType<31>;
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def TypeCVI_VX_LATE : IType<32>;
|
||||
def TypeCVI_ZW : IType<33>;
|
||||
def TypeDUPLEX : IType<34>;
|
||||
def TypeENDLOOP : IType<35>;
|
||||
def TypeEXTENDER : IType<36>;
|
||||
def TypeJ : IType<37>;
|
||||
def TypeLD : IType<38>;
|
||||
def TypeM : IType<39>;
|
||||
def TypeMAPPING : IType<40>;
|
||||
def TypeNCJ : IType<41>;
|
||||
def TypePSEUDO : IType<42>;
|
||||
def TypeST : IType<43>;
|
||||
def TypeSUBINSN : IType<44>;
|
||||
def TypeS_2op : IType<45>;
|
||||
def TypeS_3op : IType<46>;
|
||||
def TypeV2LDST : IType<49>;
|
||||
def TypeV4LDST : IType<50>;
|
||||
def TypeCR : IType<5>;
|
||||
def TypeCVI_4SLOT_MPY : IType<6>;
|
||||
def TypeCVI_GATHER : IType<7>;
|
||||
def TypeCVI_GATHER_DV : IType<8>;
|
||||
def TypeCVI_GATHER_RST : IType<9>;
|
||||
def TypeCVI_HIST : IType<10>;
|
||||
def TypeCVI_SCATTER : IType<11>;
|
||||
def TypeCVI_SCATTER_DV : IType<12>;
|
||||
def TypeCVI_SCATTER_NEW_RST : IType<13>;
|
||||
def TypeCVI_SCATTER_NEW_ST : IType<14>;
|
||||
def TypeCVI_SCATTER_RST : IType<15>;
|
||||
def TypeCVI_VA : IType<16>;
|
||||
def TypeCVI_VA_DV : IType<17>;
|
||||
def TypeCVI_VM_LD : IType<18>;
|
||||
def TypeCVI_VM_NEW_ST : IType<19>;
|
||||
def TypeCVI_VM_ST : IType<20>;
|
||||
def TypeCVI_VM_STU : IType<21>;
|
||||
def TypeCVI_VM_TMP_LD : IType<22>;
|
||||
def TypeCVI_VM_VP_LDU : IType<23>;
|
||||
def TypeCVI_VP : IType<24>;
|
||||
def TypeCVI_VP_VS : IType<25>;
|
||||
def TypeCVI_VS : IType<26>;
|
||||
def TypeCVI_VS_VX : IType<27>;
|
||||
def TypeCVI_VX : IType<28>;
|
||||
def TypeCVI_VX_DV : IType<29>;
|
||||
def TypeCVI_VX_LATE : IType<30>;
|
||||
def TypeCVI_ZW : IType<31>;
|
||||
def TypeDUPLEX : IType<32>;
|
||||
def TypeENDLOOP : IType<33>;
|
||||
def TypeEXTENDER : IType<34>;
|
||||
def TypeJ : IType<35>;
|
||||
def TypeLD : IType<36>;
|
||||
def TypeM : IType<37>;
|
||||
def TypeMAPPING : IType<38>;
|
||||
def TypeNCJ : IType<39>;
|
||||
def TypePSEUDO : IType<40>;
|
||||
def TypeST : IType<41>;
|
||||
def TypeSUBINSN : IType<42>;
|
||||
def TypeS_2op : IType<43>;
|
||||
def TypeS_3op : IType<44>;
|
||||
def TypeV2LDST : IType<47>;
|
||||
def TypeV4LDST : IType<48>;
|
||||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -197,6 +197,8 @@ def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_
|
||||
def V6_stu0Alias : InstAlias<"vmemu($Rt32) = $Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
|
||||
def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32) = $Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
|
||||
def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32) = $Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>;
|
||||
def V6_v6mpyhubs10_altAlias : InstAlias<"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):h", (V6_v6mpyhubs10 HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii)>, Requires<[UseHVX]>;
|
||||
def V6_v6mpyvubs10_altAlias : InstAlias<"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):v", (V6_v6mpyvubs10 HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii)>, Requires<[UseHVX]>;
|
||||
def V6_vabsb_altAlias : InstAlias<"$Vd32 = vabsb($Vu32)", (V6_vabsb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
|
||||
def V6_vabsb_sat_altAlias : InstAlias<"$Vd32 = vabsb($Vu32):sat", (V6_vabsb_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
|
||||
def V6_vabsdiffh_altAlias : InstAlias<"$Vd32 = vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
|
@ -8,10 +8,10 @@
|
||||
// Automatically generated file, do not edit!
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H
|
||||
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H
|
||||
|
||||
// clang-format off
|
||||
HexagonInstruction InstructionEncodings[] = {
|
||||
{ /*Tag:A2_addi*/
|
||||
/*Rd32=add(Rs32,#s16)*/
|
||||
@ -2816,6 +2816,5 @@ HexagonInstruction InstructionEncodings[] = {
|
||||
0x00002404,
|
||||
0 }
|
||||
};
|
||||
// clang-format off
|
||||
|
||||
#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H
|
||||
|
@ -13,120 +13,120 @@ multiclass ImmOpPred<code pred, ValueType vt = i32> {
|
||||
def _timm : PatLeaf<(vt timm), pred>;
|
||||
}
|
||||
|
||||
def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; }
|
||||
defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
|
||||
def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; }
|
||||
defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
|
||||
def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; }
|
||||
defm s8_0ImmPred : ImmOpPred<[{ return isShiftedInt<8, 0>(N->getSExtValue());}]>;
|
||||
def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>;
|
||||
def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>;
|
||||
def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u8_0ImmPred : ImmOpPred<[{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>;
|
||||
def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
|
||||
def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>;
|
||||
def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u7_0ImmPred : ImmOpPred<[{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>;
|
||||
def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_0ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>;
|
||||
def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
|
||||
def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
|
||||
def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
|
||||
def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
|
||||
def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
|
||||
def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
|
||||
def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
|
||||
def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
|
||||
def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
|
||||
def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; }
|
||||
defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
|
||||
def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; }
|
||||
defm s31_1ImmPred : ImmOpPred<[{ return isShiftedInt<32, 1>(N->getSExtValue());}]>;
|
||||
def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; }
|
||||
defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>;
|
||||
def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; }
|
||||
defm s30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
|
||||
def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; }
|
||||
defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>;
|
||||
def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; }
|
||||
defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>;
|
||||
def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; }
|
||||
defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>;
|
||||
def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u29_3ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>;
|
||||
def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u31_1ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>;
|
||||
def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u30_2ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>;
|
||||
def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>;
|
||||
def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
|
||||
def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_2ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>;
|
||||
def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>;
|
||||
def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>;
|
||||
def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u4_0ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>;
|
||||
def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; }
|
||||
defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
|
||||
def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_1ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>;
|
||||
def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>;
|
||||
def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_3ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>;
|
||||
def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>;
|
||||
def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_2Imm : Operand<i32> { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_2ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>;
|
||||
def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; }
|
||||
defm s6_3ImmPred : ImmOpPred<[{ return isShiftedInt<6, 3>(N->getSExtValue());}]>;
|
||||
def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; }
|
||||
defm s3_0ImmPred : ImmOpPred<[{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
|
||||
def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; }
|
||||
defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
|
||||
def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; }
|
||||
defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>;
|
||||
def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; }
|
||||
defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>;
|
||||
def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; }
|
||||
defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>;
|
||||
def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; }
|
||||
defm s6_3ImmPred : ImmOpPred<[{ return isShiftedInt<6, 3>(N->getSExtValue());}]>;
|
||||
def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; }
|
||||
defm s8_0ImmPred : ImmOpPred<[{ return isShiftedInt<8, 0>(N->getSExtValue());}]>;
|
||||
def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u1_0ImmPred : ImmOpPred<[{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>;
|
||||
def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>;
|
||||
def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>;
|
||||
def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>;
|
||||
def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>;
|
||||
def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>;
|
||||
def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>;
|
||||
def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u4_0ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>;
|
||||
def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>;
|
||||
def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>;
|
||||
def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_2Imm : Operand<i32> { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_2ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>;
|
||||
def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_3ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>;
|
||||
def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_0ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>;
|
||||
def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_1ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>;
|
||||
def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u31_1ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>;
|
||||
def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_2ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>;
|
||||
def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u30_2ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>;
|
||||
def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u29_3ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>;
|
||||
def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u7_0ImmPred : ImmOpPred<[{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>;
|
||||
def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u8_0ImmPred : ImmOpPred<[{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>;
|
||||
|
@ -95,6 +95,16 @@ inline bool is_TC2(unsigned SchedClass) {
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC2early(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_45f9d1be:
|
||||
case Hexagon::Sched::tc_a4ee89db:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC3x(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_01e1be3b:
|
||||
@ -126,16 +136,6 @@ inline bool is_TC3x(unsigned SchedClass) {
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC2early(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_45f9d1be:
|
||||
case Hexagon::Sched::tc_a4ee89db:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC4x(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_02fe1c65:
|
||||
|
@ -68,3 +68,4 @@ include "HexagonScheduleV65.td"
|
||||
include "HexagonScheduleV66.td"
|
||||
include "HexagonScheduleV67.td"
|
||||
include "HexagonScheduleV67T.td"
|
||||
include "HexagonScheduleV68.td"
|
||||
|
38
lib/Target/Hexagon/HexagonScheduleV68.td
Normal file
38
lib/Target/Hexagon/HexagonScheduleV68.td
Normal file
@ -0,0 +1,38 @@
|
||||
//=-HexagonScheduleV68.td - HexagonV68 Scheduling Definitions *- tablegen -*-=//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//
|
||||
// ScalarItin and HVXItin contain some old itineraries
|
||||
// still used by a handful of instructions. Hopefully, we will be able
|
||||
// to get rid of them soon.
|
||||
def HexagonV68ItinList : DepScalarItinV68, ScalarItin,
|
||||
DepHVXItinV68, HVXItin, PseudoItin {
|
||||
list<InstrItinData> ItinList =
|
||||
!listconcat(DepScalarItinV68_list, ScalarItin_list,
|
||||
DepHVXItinV68_list, HVXItin_list, PseudoItin_list);
|
||||
}
|
||||
|
||||
def HexagonItinerariesV68 :
|
||||
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
|
||||
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
|
||||
CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
|
||||
CVI_ALL_NOMEM, CVI_ZW],
|
||||
[Hex_FWD, HVX_FWD],
|
||||
HexagonV68ItinList.ItinList>;
|
||||
|
||||
def HexagonModelV68 : SchedMachineModel {
|
||||
// Max issue per cycle == bundle width.
|
||||
let IssueWidth = 4;
|
||||
let Itineraries = HexagonItinerariesV68;
|
||||
let LoadLatency = 1;
|
||||
let CompleteModel = 0;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Hexagon V68 Resource Definitions -
|
||||
//===----------------------------------------------------------------------===//
|
@ -179,6 +179,12 @@ public:
|
||||
bool hasV67OpsOnly() const {
|
||||
return getHexagonArchVersion() == Hexagon::ArchEnum::V67;
|
||||
}
|
||||
bool hasV68Ops() const {
|
||||
return getHexagonArchVersion() >= Hexagon::ArchEnum::V68;
|
||||
}
|
||||
bool hasV68OpsOnly() const {
|
||||
return getHexagonArchVersion() == Hexagon::ArchEnum::V68;
|
||||
}
|
||||
|
||||
bool useAudioOps() const { return UseAudioOps; }
|
||||
bool useCompound() const { return UseCompound; }
|
||||
@ -212,6 +218,9 @@ public:
|
||||
bool useHVXV67Ops() const {
|
||||
return HexagonHVXVersion >= Hexagon::ArchEnum::V67;
|
||||
}
|
||||
bool useHVXV68Ops() const {
|
||||
return HexagonHVXVersion >= Hexagon::ArchEnum::V68;
|
||||
}
|
||||
bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
|
||||
bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
|
||||
|
||||
|
@ -78,6 +78,8 @@ cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
|
||||
cl::init(false));
|
||||
cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
|
||||
cl::init(false));
|
||||
cl::opt<bool> MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"),
|
||||
cl::init(false));
|
||||
|
||||
cl::opt<Hexagon::ArchEnum>
|
||||
EnableHVX("mhvx",
|
||||
@ -88,6 +90,7 @@ cl::opt<Hexagon::ArchEnum>
|
||||
clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
|
||||
clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
|
||||
clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
|
||||
clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
|
||||
// Sentinel for no value specified.
|
||||
clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
|
||||
// Sentinel for flag not present.
|
||||
@ -118,6 +121,8 @@ static StringRef HexagonGetArchVariant() {
|
||||
return "hexagonv67";
|
||||
if (MV67T)
|
||||
return "hexagonv67t";
|
||||
if (MV68)
|
||||
return "hexagonv68";
|
||||
return "";
|
||||
}
|
||||
|
||||
@ -363,6 +368,9 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) {
|
||||
case Hexagon::ArchEnum::V67:
|
||||
Result.push_back("+hvxv67");
|
||||
break;
|
||||
case Hexagon::ArchEnum::V68:
|
||||
Result.push_back("+hvxv68");
|
||||
break;
|
||||
case Hexagon::ArchEnum::Generic:{
|
||||
Result.push_back(StringSwitch<StringRef>(CPU)
|
||||
.Case("hexagonv60", "+hvxv60")
|
||||
@ -370,7 +378,8 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) {
|
||||
.Case("hexagonv65", "+hvxv65")
|
||||
.Case("hexagonv66", "+hvxv66")
|
||||
.Case("hexagonv67", "+hvxv67")
|
||||
.Case("hexagonv67t", "+hvxv67"));
|
||||
.Case("hexagonv67t", "+hvxv67")
|
||||
.Case("hexagonv68", "+hvxv68"));
|
||||
break;
|
||||
}
|
||||
case Hexagon::ArchEnum::NoArch:
|
||||
@ -413,8 +422,8 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
|
||||
// turns on hvxvNN, corresponding to the existing ArchVNN.
|
||||
FeatureBitset FB = S;
|
||||
unsigned CpuArch = ArchV5;
|
||||
for (unsigned F : {ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, ArchV55,
|
||||
ArchV5}) {
|
||||
for (unsigned F : {ArchV68, ArchV67, ArchV66, ArchV65, ArchV62, ArchV60,
|
||||
ArchV55, ArchV5}) {
|
||||
if (!FB.test(F))
|
||||
continue;
|
||||
CpuArch = F;
|
||||
@ -429,7 +438,7 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
|
||||
}
|
||||
bool HasHvxVer = false;
|
||||
for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
|
||||
ExtensionHVXV66, ExtensionHVXV67}) {
|
||||
ExtensionHVXV66, ExtensionHVXV67, ExtensionHVXV68}) {
|
||||
if (!FB.test(F))
|
||||
continue;
|
||||
HasHvxVer = true;
|
||||
@ -442,6 +451,9 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
|
||||
|
||||
// HasHvxVer is false, and UseHvx is true.
|
||||
switch (CpuArch) {
|
||||
case ArchV68:
|
||||
FB.set(ExtensionHVXV68);
|
||||
LLVM_FALLTHROUGH;
|
||||
case ArchV67:
|
||||
FB.set(ExtensionHVXV67);
|
||||
LLVM_FALLTHROUGH;
|
||||
@ -525,6 +537,7 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
|
||||
{"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
|
||||
{"hexagonv67", ELF::EF_HEXAGON_MACH_V67},
|
||||
{"hexagonv67t", ELF::EF_HEXAGON_MACH_V67T},
|
||||
{"hexagonv68", ELF::EF_HEXAGON_MACH_V68},
|
||||
};
|
||||
|
||||
auto F = ElfFlags.find(STI.getCPU());
|
||||
|
Loading…
Reference in New Issue
Block a user