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Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def. This is the naive solution to the problem: insert a copy to the pre-chosen vreg. Other solutions might be preferable, such as: 1) Passing the dest reg into FastEmit_. However, this would require the higher level code to know about reg classes, which they don't currently. 2) Selecting blocks in reverse postorder. This has some compile time cost for computing the order, and we'd need to measure its impact. llvm-svn: 55555
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@ -225,6 +225,9 @@ private:
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bool SelectCast(Instruction *I, ISD::NodeType Opcode,
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bool SelectCast(Instruction *I, ISD::NodeType Opcode,
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DenseMap<const Value*, unsigned> &ValueMap);
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DenseMap<const Value*, unsigned> &ValueMap);
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void UpdateValueMap(Instruction* I, unsigned Reg,
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DenseMap<const Value*, unsigned> &ValueMap);
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};
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};
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}
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}
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@ -63,6 +63,21 @@ unsigned FastISel::getRegForValue(Value *V, DenseMap<const Value*, unsigned> &Va
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return Reg;
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return Reg;
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}
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}
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/// UpdateValueMap - Update the value map to include the new mapping for this
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/// instruction, or insert an extra copy to get the result in a previous
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/// determined register.
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/// NOTE: This is only necessary because we might select a block that uses
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/// a value before we select the block that defines the value. It might be
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/// possible to fix this by selecting blocks in reverse postorder.
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void FastISel::UpdateValueMap(Instruction* I, unsigned Reg,
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DenseMap<const Value*, unsigned> &ValueMap) {
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if (!ValueMap.count(I))
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ValueMap[I] = Reg;
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else
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TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
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Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
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}
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// which has an opcode which directly corresponds to the given ISD opcode.
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/// which has an opcode which directly corresponds to the given ISD opcode.
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///
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///
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@ -90,7 +105,7 @@ bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
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ISDOpcode, Op0, CI->getZExtValue());
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ISDOpcode, Op0, CI->getZExtValue());
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if (ResultReg != 0) {
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if (ResultReg != 0) {
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// We successfully emitted code for the given LLVM Instruction.
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// We successfully emitted code for the given LLVM Instruction.
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ValueMap[I] = ResultReg;
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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return true;
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}
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}
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}
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}
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@ -101,7 +116,7 @@ bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
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ISDOpcode, Op0, CF);
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ISDOpcode, Op0, CF);
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if (ResultReg != 0) {
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if (ResultReg != 0) {
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// We successfully emitted code for the given LLVM Instruction.
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// We successfully emitted code for the given LLVM Instruction.
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ValueMap[I] = ResultReg;
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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return true;
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}
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}
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}
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}
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@ -120,7 +135,7 @@ bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
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return false;
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return false;
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// We successfully emitted code for the given LLVM Instruction.
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// We successfully emitted code for the given LLVM Instruction.
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ValueMap[I] = ResultReg;
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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return true;
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}
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}
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@ -196,7 +211,7 @@ bool FastISel::SelectGetElementPtr(Instruction *I,
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}
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}
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// We successfully emitted code for the given LLVM Instruction.
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// We successfully emitted code for the given LLVM Instruction.
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ValueMap[I] = N;
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UpdateValueMap(I, N, ValueMap);
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return true;
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return true;
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}
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}
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@ -223,7 +238,7 @@ bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
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if (!ResultReg)
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if (!ResultReg)
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return false;
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return false;
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ValueMap[I] = ResultReg;
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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return true;
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}
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}
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@ -234,7 +249,7 @@ bool FastISel::SelectBitCast(Instruction *I,
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unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
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unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
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if (Reg == 0)
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if (Reg == 0)
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return false;
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return false;
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ValueMap[I] = Reg;
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UpdateValueMap(I, Reg, ValueMap);
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return true;
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return true;
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}
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}
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@ -274,7 +289,7 @@ bool FastISel::SelectBitCast(Instruction *I,
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if (!ResultReg)
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if (!ResultReg)
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return false;
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return false;
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ValueMap[I] = ResultReg;
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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return true;
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}
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}
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@ -384,7 +399,7 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
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MVT DstVT = TLI.getValueType(I->getType());
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MVT DstVT = TLI.getValueType(I->getType());
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if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
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if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
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if (ValueMap[I->getOperand(0)]) {
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if (ValueMap[I->getOperand(0)]) {
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ValueMap[I] = ValueMap[I->getOperand(0)];
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UpdateValueMap(I, ValueMap[I->getOperand(0)], ValueMap);
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break;
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break;
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} else
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} else
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// Unhandled operand
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// Unhandled operand
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